add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arc/mm/tlbex.S
..
..
@@ -1,11 +1,8 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
1
2
 /*
2
3
  * TLB Exception Handling for ARC
3
4
  *
4
5
  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License version 2 as
8
- * published by the Free Software Foundation.
9
6
  *
10
7
  * Vineetg: April 2011 :
11
8
  *  -MMU v1: moved out legacy code into a seperate file
..
..
@@ -36,9 +33,9 @@
36
33
  */
37
34
 
38
35
 #include <linux/linkage.h>
36
+#include <linux/pgtable.h>
39
37
 #include <asm/entry.h>
40
38
 #include <asm/mmu.h>
41
-#include <asm/pgtable.h>
42
39
 #include <asm/arcregs.h>
43
40
 #include <asm/cache.h>
44
41
 #include <asm/processor.h>
..
..
@@ -125,17 +122,27 @@
125
122
 #else	/* ARCv2 */
126
123
 
127
124
 .macro TLBMISS_FREEUP_REGS
125
+#ifdef CONFIG_ARC_HAS_LL64
126
+	std   r0, [sp, -16]
127
+	std   r2, [sp, -8]
128
+#else
128
129
 	PUSH  r0
129
130
 	PUSH  r1
130
131
 	PUSH  r2
131
132
 	PUSH  r3
133
+#endif
132
134
 .endm
133
135
 
134
136
 .macro TLBMISS_RESTORE_REGS
137
+#ifdef CONFIG_ARC_HAS_LL64
138
+	ldd   r0, [sp, -16]
139
+	ldd   r2, [sp, -8]
140
+#else
135
141
 	POP   r3
136
142
 	POP   r2
137
143
 	POP   r1
138
144
 	POP   r0
145
+#endif
139
146
 .endm
140
147
 
141
148
 #endif
..
..
@@ -196,7 +203,7 @@
196
203
 
197
204
 	lr  r2, [efa]
198
205
 
199
-#ifndef CONFIG_SMP
206
+#ifdef ARC_USE_SCRATCH_REG
200
207
 	lr  r1, [ARC_REG_SCRATCH_DATA0] ; current pgd
201
208
 #else
202
209
 	GET_CURR_TASK_ON_CPU  r1
..
..
@@ -274,22 +281,11 @@
274
281
 .macro COMMIT_ENTRY_TO_MMU
275
282
 #if (CONFIG_ARC_MMU_VER < 4)
276
283
 
277
-#ifdef CONFIG_EZNPS_MTM_EXT
278
-	/* verify if entry for this vaddr+ASID already exists */
279
-	sr    TLBProbe, [ARC_REG_TLBCOMMAND]
280
-	lr    r0, [ARC_REG_TLBINDEX]
281
-	bbit0 r0, 31, 88f
282
-#endif
283
-
284
284
 	/* Get free TLB slot: Set = computed from vaddr, way = random */
285
285
 	sr  TLBGetIndex, [ARC_REG_TLBCOMMAND]
286
286
 
287
287
 	/* Commit the Write */
288
-#if (CONFIG_ARC_MMU_VER >= 2)   /* introduced in v2 */
289
288
 	sr TLBWriteNI, [ARC_REG_TLBCOMMAND]
290
-#else
291
-	sr TLBWrite, [ARC_REG_TLBCOMMAND]
292
-#endif
293
289
 
294
290
 #else
295
291
 	sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
..
..
@@ -373,9 +369,7 @@
373
369
 
374
370
 	;----------------------------------------------------------------
375
371
 	; UPDATE_PTE: Let Linux VM know that page was accessed/dirty
376
-	lr      r3, [ecr]
377
372
 	or      r0, r0, _PAGE_ACCESSED        ; Accessed bit always
378
-	btst_s  r3,  ECR_C_BIT_DTLB_ST_MISS   ; See if it was a Write Access ?
379
373
 	or.nz   r0, r0, _PAGE_DIRTY           ; if Write, set Dirty bit as well
380
374
 	st_s    r0, [r1]                      ; Write back PTE
381
375
 
..
..
@@ -396,6 +390,17 @@
396
390
 ;-------- Common routine to call Linux Page Fault Handler -----------
397
391
 do_slow_path_pf:
398
392
 
393
+#ifdef CONFIG_ISA_ARCV2
394
+	; Set Z flag if exception in U mode. Hardware micro-ops do this on any
395
+	; taken interrupt/exception, and thus is already the case at the entry
396
+	; above, but ensuing code would have already clobbered.
397
+	; EXCEPTION_PROLOGUE called in slow path, relies on correct Z flag set
398
+
399
+	lr	r2, [erstatus]
400
+	and	r2, r2, STATUS_U_MASK
401
+	bxor.f	0, r2, STATUS_U_BIT
402
+#endif
403
+
399
404
 	; Restore the 4-scratch regs saved by fast path miss handler
400
405
 	TLBMISS_RESTORE_REGS
401
406