.. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * Abilis Systems TB10X SOC device tree |
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3 | 4 | * |
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4 | 5 | * Copyright (C) Abilis Systems 2013 |
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5 | 6 | * |
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6 | 7 | * Author: Christian Ruppert <christian.ruppert@abilis.com> |
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7 | | - * |
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8 | | - * This program is free software; you can redistribute it and/or modify |
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9 | | - * it under the terms of the GNU General Public License version 2 as |
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10 | | - * published by the Free Software Foundation. |
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11 | | - * |
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12 | | - * This program is distributed in the hope that it will be useful, |
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13 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 | | - * GNU General Public License for more details. |
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16 | | - * |
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17 | | - * You should have received a copy of the GNU General Public License |
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18 | | - * along with this program; if not, write to the Free Software |
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19 | | - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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20 | 8 | */ |
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21 | 9 | |
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22 | 10 | |
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.. | .. |
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54 | 42 | #size-cells = <1>; |
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55 | 43 | device_type = "soc"; |
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56 | 44 | ranges = <0xfe000000 0xfe000000 0x02000000 |
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57 | | - 0x000F0000 0x000F0000 0x00010000>; |
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| 45 | + 0x000f0000 0x000f0000 0x00010000>; |
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58 | 46 | compatible = "abilis,tb10x", "simple-bus"; |
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59 | 47 | |
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60 | 48 | pll0: oscillator { |
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.. | .. |
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75 | 63 | clock-output-names = "ahb_clk"; |
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76 | 64 | }; |
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77 | 65 | |
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78 | | - iomux: iomux@FF10601c { |
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| 66 | + iomux: iomux@ff10601c { |
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79 | 67 | compatible = "abilis,tb10x-iomux"; |
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80 | 68 | #gpio-range-cells = <3>; |
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81 | | - reg = <0xFF10601c 0x4>; |
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| 69 | + reg = <0xff10601c 0x4>; |
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82 | 70 | }; |
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83 | 71 | |
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84 | 72 | intc: interrupt-controller { |
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.. | .. |
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88 | 76 | }; |
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89 | 77 | tb10x_ictl: pic@fe002000 { |
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90 | 78 | compatible = "abilis,tb10x-ictl"; |
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91 | | - reg = <0xFE002000 0x20>; |
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| 79 | + reg = <0xfe002000 0x20>; |
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92 | 80 | interrupt-controller; |
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93 | 81 | #interrupt-cells = <2>; |
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94 | 82 | interrupt-parent = <&intc>; |
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.. | .. |
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96 | 84 | 20 21 22 23 24 25 26 27 28 29 30 31>; |
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97 | 85 | }; |
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98 | 86 | |
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99 | | - uart@FF100000 { |
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| 87 | + uart@ff100000 { |
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100 | 88 | compatible = "snps,dw-apb-uart"; |
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101 | | - reg = <0xFF100000 0x100>; |
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| 89 | + reg = <0xff100000 0x100>; |
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102 | 90 | clock-frequency = <166666666>; |
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103 | 91 | interrupts = <25 8>; |
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104 | 92 | reg-shift = <2>; |
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105 | 93 | reg-io-width = <4>; |
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106 | 94 | interrupt-parent = <&tb10x_ictl>; |
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107 | 95 | }; |
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108 | | - ethernet@FE100000 { |
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| 96 | + ethernet@fe100000 { |
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109 | 97 | compatible = "snps,dwmac-3.70a","snps,dwmac"; |
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110 | | - reg = <0xFE100000 0x1058>; |
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| 98 | + reg = <0xfe100000 0x1058>; |
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111 | 99 | interrupt-parent = <&tb10x_ictl>; |
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112 | 100 | interrupts = <6 8>; |
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113 | 101 | interrupt-names = "macirq"; |
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114 | 102 | clocks = <&ahb_clk>; |
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115 | 103 | clock-names = "stmmaceth"; |
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116 | 104 | }; |
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117 | | - dma@FE000000 { |
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| 105 | + dma@fe000000 { |
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118 | 106 | compatible = "snps,dma-spear1340"; |
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119 | | - reg = <0xFE000000 0x400>; |
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| 107 | + reg = <0xfe000000 0x400>; |
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120 | 108 | interrupt-parent = <&tb10x_ictl>; |
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121 | 109 | interrupts = <14 8>; |
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122 | 110 | dma-channels = <6>; |
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.. | .. |
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132 | 120 | multi-block = <1 1 1 1 1 1>; |
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133 | 121 | }; |
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134 | 122 | |
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135 | | - i2c0: i2c@FF120000 { |
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| 123 | + i2c0: i2c@ff120000 { |
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136 | 124 | #address-cells = <1>; |
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137 | 125 | #size-cells = <0>; |
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138 | 126 | compatible = "snps,designware-i2c"; |
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139 | | - reg = <0xFF120000 0x1000>; |
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| 127 | + reg = <0xff120000 0x1000>; |
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140 | 128 | interrupt-parent = <&tb10x_ictl>; |
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141 | 129 | interrupts = <12 8>; |
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142 | 130 | clocks = <&ahb_clk>; |
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143 | 131 | }; |
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144 | | - i2c1: i2c@FF121000 { |
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| 132 | + i2c1: i2c@ff121000 { |
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145 | 133 | #address-cells = <1>; |
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146 | 134 | #size-cells = <0>; |
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147 | 135 | compatible = "snps,designware-i2c"; |
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148 | | - reg = <0xFF121000 0x1000>; |
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| 136 | + reg = <0xff121000 0x1000>; |
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149 | 137 | interrupt-parent = <&tb10x_ictl>; |
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150 | 138 | interrupts = <12 8>; |
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151 | 139 | clocks = <&ahb_clk>; |
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152 | 140 | }; |
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153 | | - i2c2: i2c@FF122000 { |
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| 141 | + i2c2: i2c@ff122000 { |
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154 | 142 | #address-cells = <1>; |
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155 | 143 | #size-cells = <0>; |
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156 | 144 | compatible = "snps,designware-i2c"; |
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157 | | - reg = <0xFF122000 0x1000>; |
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| 145 | + reg = <0xff122000 0x1000>; |
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158 | 146 | interrupt-parent = <&tb10x_ictl>; |
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159 | 147 | interrupts = <12 8>; |
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160 | 148 | clocks = <&ahb_clk>; |
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161 | 149 | }; |
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162 | | - i2c3: i2c@FF123000 { |
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| 150 | + i2c3: i2c@ff123000 { |
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163 | 151 | #address-cells = <1>; |
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164 | 152 | #size-cells = <0>; |
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165 | 153 | compatible = "snps,designware-i2c"; |
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166 | | - reg = <0xFF123000 0x1000>; |
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| 154 | + reg = <0xff123000 0x1000>; |
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167 | 155 | interrupt-parent = <&tb10x_ictl>; |
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168 | 156 | interrupts = <12 8>; |
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169 | 157 | clocks = <&ahb_clk>; |
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170 | 158 | }; |
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171 | | - i2c4: i2c@FF124000 { |
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| 159 | + i2c4: i2c@ff124000 { |
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172 | 160 | #address-cells = <1>; |
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173 | 161 | #size-cells = <0>; |
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174 | 162 | compatible = "snps,designware-i2c"; |
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175 | | - reg = <0xFF124000 0x1000>; |
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| 163 | + reg = <0xff124000 0x1000>; |
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176 | 164 | interrupt-parent = <&tb10x_ictl>; |
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177 | 165 | interrupts = <12 8>; |
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178 | 166 | clocks = <&ahb_clk>; |
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179 | 167 | }; |
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180 | 168 | |
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181 | | - spi0: spi@0xFE010000 { |
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| 169 | + spi0: spi@fe010000 { |
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182 | 170 | #address-cells = <1>; |
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183 | 171 | #size-cells = <0>; |
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184 | 172 | cell-index = <0>; |
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185 | 173 | compatible = "abilis,tb100-spi"; |
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186 | 174 | num-cs = <1>; |
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187 | | - reg = <0xFE010000 0x20>; |
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| 175 | + reg = <0xfe010000 0x20>; |
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188 | 176 | interrupt-parent = <&tb10x_ictl>; |
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189 | 177 | interrupts = <26 8>; |
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190 | 178 | clocks = <&ahb_clk>; |
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191 | 179 | }; |
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192 | | - spi1: spi@0xFE011000 { |
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| 180 | + spi1: spi@fe011000 { |
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193 | 181 | #address-cells = <1>; |
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194 | 182 | #size-cells = <0>; |
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195 | 183 | cell-index = <1>; |
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196 | 184 | compatible = "abilis,tb100-spi"; |
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197 | 185 | num-cs = <2>; |
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198 | | - reg = <0xFE011000 0x20>; |
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| 186 | + reg = <0xfe011000 0x20>; |
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199 | 187 | interrupt-parent = <&tb10x_ictl>; |
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200 | 188 | interrupts = <10 8>; |
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201 | 189 | clocks = <&ahb_clk>; |
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.. | .. |
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226 | 214 | interrupts = <20 2>, <19 2>; |
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227 | 215 | interrupt-names = "cmd_irq", "event_irq"; |
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228 | 216 | }; |
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229 | | - tb10x_mdsc0: tb10x-mdscr@FF300000 { |
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| 217 | + tb10x_mdsc0: tb10x-mdscr@ff300000 { |
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230 | 218 | compatible = "abilis,tb100-mdscr"; |
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231 | | - reg = <0xFF300000 0x7000>; |
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| 219 | + reg = <0xff300000 0x7000>; |
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232 | 220 | tb100-mdscr-manage-tsin; |
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233 | 221 | }; |
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234 | | - tb10x_mscr0: tb10x-mdscr@FF307000 { |
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| 222 | + tb10x_mscr0: tb10x-mdscr@ff307000 { |
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235 | 223 | compatible = "abilis,tb100-mdscr"; |
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236 | | - reg = <0xFF307000 0x7000>; |
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| 224 | + reg = <0xff307000 0x7000>; |
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237 | 225 | }; |
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238 | 226 | tb10x_scr0: tb10x-mdscr@ff30e000 { |
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239 | 227 | compatible = "abilis,tb100-mdscr"; |
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240 | | - reg = <0xFF30e000 0x4000>; |
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| 228 | + reg = <0xff30e000 0x4000>; |
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241 | 229 | tb100-mdscr-manage-tsin; |
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242 | 230 | }; |
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243 | 231 | tb10x_scr1: tb10x-mdscr@ff312000 { |
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244 | 232 | compatible = "abilis,tb100-mdscr"; |
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245 | | - reg = <0xFF312000 0x4000>; |
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| 233 | + reg = <0xff312000 0x4000>; |
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246 | 234 | tb100-mdscr-manage-tsin; |
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247 | 235 | }; |
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248 | 236 | tb10x_wfb: tb10x-wfb@ff319000 { |
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