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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/arch/arc/Kconfig
....@@ -1,24 +1,23 @@
1
+# SPDX-License-Identifier: GPL-2.0-only
12 #
23 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
3
-#
4
-# This program is free software; you can redistribute it and/or modify
5
-# it under the terms of the GNU General Public License version 2 as
6
-# published by the Free Software Foundation.
74 #
85 
96 config ARC
107 	def_bool y
118 	select ARC_TIMERS
9
+	select ARCH_HAS_DEBUG_VM_PGTABLE
10
+	select ARCH_HAS_DMA_PREP_COHERENT
1211 	select ARCH_HAS_PTE_SPECIAL
12
+	select ARCH_HAS_SETUP_DMA_OPS
1313 	select ARCH_HAS_SYNC_DMA_FOR_CPU
1414 	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
15
-	select ARCH_HAS_SG_CHAIN
1615 	select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
17
-	select BUILDTIME_EXTABLE_SORT
16
+	select ARCH_32BIT_OFF_T
17
+	select BUILDTIME_TABLE_SORT
1818 	select CLONE_BACKWARDS
1919 	select COMMON_CLK
20
-	select DMA_NONCOHERENT_OPS
21
-	select DMA_NONCOHERENT_MMAP
20
+	select DMA_DIRECT_REMAP
2221 	select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
2322 	select GENERIC_CLOCKEVENTS
2423 	select GENERIC_FIND_FIRST_BIT
....@@ -31,31 +30,28 @@
3130 	select HAVE_ARCH_KGDB
3231 	select HAVE_ARCH_TRACEHOOK
3332 	select HAVE_DEBUG_STACKOVERFLOW
33
+	select HAVE_DEBUG_KMEMLEAK
3434 	select HAVE_FUTEX_CMPXCHG if FUTEX
35
-	select HAVE_GENERIC_DMA_COHERENT
3635 	select HAVE_IOREMAP_PROT
3736 	select HAVE_KERNEL_GZIP
3837 	select HAVE_KERNEL_LZMA
3938 	select HAVE_KPROBES
4039 	select HAVE_KRETPROBES
41
-	select HAVE_MEMBLOCK
4240 	select HAVE_MOD_ARCH_SPECIFIC
4341 	select HAVE_OPROFILE
4442 	select HAVE_PERF_EVENTS
4543 	select HANDLE_DOMAIN_IRQ
4644 	select IRQ_DOMAIN
4745 	select MODULES_USE_ELF_RELA
48
-	select NO_BOOTMEM
4946 	select OF
5047 	select OF_EARLY_FLATTREE
51
-	select OF_RESERVED_MEM
48
+	select PCI_SYSCALL if PCI
5249 	select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
50
+	select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
51
+	select SET_FS
5352 
5453 config ARCH_HAS_CACHE_LINE_SIZE
5554 	def_bool y
56
-
57
-config MIGHT_HAVE_PCI
58
-	bool
5955 
6056 config TRACE_IRQFLAGS_SUPPORT
6157 	def_bool y
....@@ -67,9 +63,6 @@
6763 	def_bool y
6864 
6965 config GENERIC_CSUM
70
-	def_bool y
71
-
72
-config RWSEM_GENERIC_SPINLOCK
7366 	def_bool y
7467 
7568 config ARCH_DISCONTIGMEM_ENABLE
....@@ -104,8 +97,6 @@
10497 
10598 source "arch/arc/plat-tb10x/Kconfig"
10699 source "arch/arc/plat-axs10x/Kconfig"
107
-#New platform adds here
108
-source "arch/arc/plat-eznps/Kconfig"
109100 source "arch/arc/plat-hsdk/Kconfig"
110101 
111102 endmenu
....@@ -150,11 +141,11 @@
150141 	  Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
151142 	  This core has a bunch of cool new features:
152143 	  -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
153
-                   Shared Address Spaces (for sharing TLB entries in MMU)
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+	           Shared Address Spaces (for sharing TLB entries in MMU)
154145 	  -Caches: New Prog Model, Region Flush
155146 	  -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
156147 
157
-endif	#ISA_ARCOMPACT
148
+endif #ISA_ARCOMPACT
158149 
159150 config ARC_CPU_HS
160151 	bool "ARC-HS"
....@@ -162,7 +153,7 @@
162153 	help
163154 	  Support for ARC HS38x Cores based on ARCv2 ISA
164155 	  The notable features are:
165
-	    - SMP configurations of upto 4 core with coherency
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+	    - SMP configurations of up to 4 cores with coherency
166157 	    - Optional L2 Cache and IO-Coherency
167158 	    - Revised Interrupt Architecture (multiple priorites, reg banks,
168159 	        auto stack switch, auto regfile save/restore)
....@@ -177,15 +168,22 @@
177168 
178169 endchoice
179170 
171
+config ARC_TUNE_MCPU
172
+	string "Override default -mcpu compiler flag"
173
+	default ""
174
+	help
175
+	  Override default -mcpu=xxx compiler flag (which is set depending on
176
+	  the ISA version) with the specified value.
177
+	  NOTE: If specified flag isn't supported by current compiler the
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+	  ISA default value will be used as a fallback.
179
+
180180 config CPU_BIG_ENDIAN
181181 	bool "Enable Big Endian Mode"
182
-	default n
183182 	help
184183 	  Build kernel for Big Endian Mode of ARC CPU
185184 
186185 config SMP
187186 	bool "Symmetric Multi-Processing"
188
-	default n
189187 	select ARC_MCIP if ISA_ARCV2
190188 	help
191189 	  This enables support for systems with more than one CPU.
....@@ -202,11 +200,11 @@
202200 	help
203201 	  In SMP configuration cores can be configured as Halt-on-reset
204202 	  or they could all start at same time. For Halt-on-reset, non
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-	  masters are parked until Master kicks them so they can start of
203
+	  masters are parked until Master kicks them so they can start off
206204 	  at designated entry point. For other case, all jump to common
207205 	  entry point and spin wait for Master's signal.
208206 
209
-endif	#SMP
207
+endif #SMP
210208 
211209 config ARC_MCIP
212210 	bool "ARConnect Multicore IP (MCIP) Support "
....@@ -256,15 +254,13 @@
256254 config ARC_CACHE_VIPT_ALIASING
257255 	bool "Support VIPT Aliasing D$"
258256 	depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
259
-	default n
260257 
261
-endif	#ARC_CACHE
258
+endif #ARC_CACHE
262259 
263260 config ARC_HAS_ICCM
264261 	bool "Use ICCM"
265262 	help
266263 	  Single Cycle RAMS to store Fast Path Code
267
-	default n
268264 
269265 config ARC_ICCM_SZ
270266 	int "ICCM Size in KB"
....@@ -275,7 +271,6 @@
275271 	bool "Use DCCM"
276272 	help
277273 	  Single Cycle RAMS to store Fast Path Data
278
-	default n
279274 
280275 config ARC_DCCM_SZ
281276 	int "DCCM Size in KB"
....@@ -360,30 +355,23 @@
360355 	default "0" if !DISCONTIGMEM
361356 	default "1" if DISCONTIGMEM
362357 	depends on NEED_MULTIPLE_NODES
363
-	---help---
358
+	help
364359 	  Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
365360 	  zones.
366361 
367
-if ISA_ARCOMPACT
368
-
369362 config ARC_COMPACT_IRQ_LEVELS
363
+	depends on ISA_ARCOMPACT
370364 	bool "Setup Timer IRQ as high Priority"
371
-	default n
372365 	# if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
373366 	depends on !SMP
374367 
375368 config ARC_FPU_SAVE_RESTORE
376369 	bool "Enable FPU state persistence across context switch"
377
-	default n
378370 	help
379
-	  Double Precision Floating Point unit had dedicated regs which
380
-	  need to be saved/restored across context-switch.
381
-	  Note that ARC FPU is overly simplistic, unlike say x86, which has
382
-	  hardware pieces to allow software to conditionally save/restore,
383
-	  based on actual usage of FPU by a task. Thus our implemn does
384
-	  this for all tasks in system.
385
-
386
-endif	#ISA_ARCOMPACT
371
+	  ARCompact FPU has internal registers to assist with Double precision
372
+	  Floating Point operations. There are control and stauts registers
373
+	  for floating point exceptions and rounding modes. These are
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+	  preserved across task context switch when enabled.
387375 
388376 config ARC_CANT_LLSC
389377 	def_bool n
....@@ -399,6 +387,15 @@
399387 
400388 if ISA_ARCV2
401389 
390
+config ARC_USE_UNALIGNED_MEM_ACCESS
391
+	bool "Enable unaligned access in HW"
392
+	default y
393
+	select HAVE_EFFICIENT_UNALIGNED_ACCESS
394
+	help
395
+	  The ARC HS architecture supports unaligned memory access
396
+	  which is disabled by default. Enable unaligned access in
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+	  hardware and use software to use it
398
+
402399 config ARC_HAS_LL64
403400 	bool "Insn: 64bit LDD/STD"
404401 	help
....@@ -412,12 +409,60 @@
412409 	default y
413410 
414411 config ARC_HAS_ACCL_REGS
415
-	bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)"
412
+	bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
416413 	default y
417414 	help
418415 	  Depending on the configuration, CPU can contain accumulator reg-pair
419416 	  (also referred to as r58:r59). These can also be used by gcc as GPR so
420417 	  kernel needs to save/restore per process
418
+
419
+config ARC_DSP_HANDLED
420
+	def_bool n
421
+
422
+config ARC_DSP_SAVE_RESTORE_REGS
423
+	def_bool n
424
+
425
+choice
426
+	prompt "DSP support"
427
+	default ARC_DSP_NONE
428
+	help
429
+	  Depending on the configuration, CPU can contain DSP registers
430
+	  (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL).
431
+	  Bellow is options describing how to handle these registers in
432
+	  interrupt entry / exit and in context switch.
433
+
434
+config ARC_DSP_NONE
435
+	bool "No DSP extension presence in HW"
436
+	help
437
+	  No DSP extension presence in HW
438
+
439
+config ARC_DSP_KERNEL
440
+	bool "DSP extension in HW, no support for userspace"
441
+	select ARC_HAS_ACCL_REGS
442
+	select ARC_DSP_HANDLED
443
+	help
444
+	  DSP extension presence in HW, no support for DSP-enabled userspace
445
+	  applications. We don't save / restore DSP registers and only do
446
+	  some minimal preparations so userspace won't be able to break kernel
447
+
448
+config ARC_DSP_USERSPACE
449
+	bool "Support DSP for userspace apps"
450
+	select ARC_HAS_ACCL_REGS
451
+	select ARC_DSP_HANDLED
452
+	select ARC_DSP_SAVE_RESTORE_REGS
453
+	help
454
+	  DSP extension presence in HW, support save / restore DSP registers to
455
+	  run DSP-enabled userspace applications
456
+
457
+config ARC_DSP_AGU_USERSPACE
458
+	bool "Support DSP with AGU for userspace apps"
459
+	select ARC_HAS_ACCL_REGS
460
+	select ARC_DSP_HANDLED
461
+	select ARC_DSP_SAVE_RESTORE_REGS
462
+	help
463
+	  DSP and AGU extensions presence in HW, support save / restore DSP
464
+	  and AGU registers to run DSP-enabled userspace applications
465
+endchoice
421466 
422467 config ARC_IRQ_NO_AUTOSAVE
423468 	bool "Disable hardware autosave regfile on interrupts"
....@@ -427,7 +472,13 @@
427472 	  This is programmable and can be optionally disabled in which case
428473 	  software INTERRUPT_PROLOGUE/EPILGUE do the needed work
429474 
430
-endif	# ISA_ARCV2
475
+config ARC_LPB_DISABLE
476
+	bool "Disable loop buffer (LPB)"
477
+	help
478
+	  On HS cores, loop buffer (LPB) is programmable in runtime and can
479
+	  be optionally disabled.
480
+
481
+endif # ISA_ARCV2
431482 
432483 endmenu   # "ARC CPU Configuration"
433484 
....@@ -456,6 +507,7 @@
456507 config HIGHMEM
457508 	bool "High Memory Support"
458509 	select ARCH_DISCONTIGMEM_ENABLE
510
+	select KMAP_LOCAL
459511 	help
460512 	  With ARC 2G:2G address split, only upper 2G is directly addressable by
461513 	  kernel. Enable this to potentially allow access to rest of 2G and PAE
....@@ -463,7 +515,6 @@
463515 
464516 config ARC_HAS_PAE40
465517 	bool "Support for the 40-bit Physical Address Extension"
466
-	default n
467518 	depends on ISA_ARCV2
468519 	select HIGHMEM
469520 	select PHYS_ADDR_T_64BIT
....@@ -506,7 +557,6 @@
506557 
507558 config ARC_METAWARE_HLINK
508559 	bool "Support for Metaware debugger assisted Host access"
509
-	default n
510560 	help
511561 	  This options allows a Linux userland apps to directly access
512562 	  host file system (open/creat/read/write etc) with help from
....@@ -534,8 +584,14 @@
534584 
535585 config ARC_DBG_TLB_PARANOIA
536586 	bool "Paranoia Checks in Low Level TLB Handlers"
537
-	default n
538587 
588
+config ARC_DBG_JUMP_LABEL
589
+	bool "Paranoid checks in Static Keys (jump labels) code"
590
+	depends on JUMP_LABEL
591
+	default y if STATIC_KEYS_SELFTEST
592
+	help
593
+	  Enable paranoid checks and self-test of both ARC-specific and generic
594
+	  part of static keys (jump labels) related code.
539595 endif
540596 
541597 config ARC_BUILTIN_DTB_NAME
....@@ -550,25 +606,5 @@
550606 	int "Maximum zone order"
551607 	default "12" if ARC_HUGEPAGE_16M
552608 	default "11"
553
-
554
-menu "Bus Support"
555
-
556
-config PCI
557
-	bool "PCI support" if MIGHT_HAVE_PCI
558
-	help
559
-	  PCI is the name of a bus system, i.e., the way the CPU talks to
560
-	  the other stuff inside your box.  Find out if your board/platform
561
-	  has PCI.
562
-
563
-	  Note: PCIe support for Synopsys Device will be available only
564
-	  when HAPS DX is configured with PCIe RC bitmap. If you have PCI,
565
-	  say Y, otherwise N.
566
-
567
-config PCI_SYSCALL
568
-	def_bool PCI
569
-
570
-source "drivers/pci/Kconfig"
571
-
572
-endmenu
573609 
574610 source "kernel/power/Kconfig"