.. | .. |
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630 | 630 | return ev; |
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631 | 631 | } |
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632 | 632 | |
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633 | | - /* The EV67 does not support mode exclusion */ |
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634 | | - if (attr->exclude_kernel || attr->exclude_user |
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635 | | - || attr->exclude_hv || attr->exclude_idle) { |
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636 | | - return -EPERM; |
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637 | | - } |
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638 | | - |
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639 | 633 | /* |
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640 | 634 | * We place the event type in event_base here and leave calculation |
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641 | 635 | * of the codes to programme the PMU for alpha_pmu_enable() because |
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.. | .. |
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771 | 765 | .start = alpha_pmu_start, |
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772 | 766 | .stop = alpha_pmu_stop, |
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773 | 767 | .read = alpha_pmu_read, |
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| 768 | + .capabilities = PERF_PMU_CAP_NO_EXCLUDE, |
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774 | 769 | }; |
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775 | 770 | |
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776 | 771 | |
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.. | .. |
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829 | 824 | if (unlikely(la_ptr >= alpha_pmu->num_pmcs)) { |
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830 | 825 | /* This should never occur! */ |
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831 | 826 | irq_err_count++; |
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832 | | - pr_warning("PMI: silly index %ld\n", la_ptr); |
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| 827 | + pr_warn("PMI: silly index %ld\n", la_ptr); |
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833 | 828 | wrperfmon(PERFMON_CMD_ENABLE, cpuc->idx_mask); |
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834 | 829 | return; |
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835 | 830 | } |
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.. | .. |
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852 | 847 | if (unlikely(!event)) { |
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853 | 848 | /* This should never occur! */ |
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854 | 849 | irq_err_count++; |
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855 | | - pr_warning("PMI: No event at index %d!\n", idx); |
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| 850 | + pr_warn("PMI: No event at index %d!\n", idx); |
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856 | 851 | wrperfmon(PERFMON_CMD_ENABLE, cpuc->idx_mask); |
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857 | 852 | return; |
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858 | 853 | } |
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