.. | .. |
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60 | 60 | Spectre variant 1 attacks take advantage of speculative execution of |
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61 | 61 | conditional branches, while Spectre variant 2 attacks use speculative |
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62 | 62 | execution of indirect branches to leak privileged memory. |
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63 | | -See :ref:`[1] <spec_ref1>` :ref:`[5] <spec_ref5>` :ref:`[7] <spec_ref7>` |
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64 | | -:ref:`[10] <spec_ref10>` :ref:`[11] <spec_ref11>`. |
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| 63 | +See :ref:`[1] <spec_ref1>` :ref:`[5] <spec_ref5>` :ref:`[6] <spec_ref6>` |
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| 64 | +:ref:`[7] <spec_ref7>` :ref:`[10] <spec_ref10>` :ref:`[11] <spec_ref11>`. |
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65 | 65 | |
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66 | 66 | Spectre variant 1 (Bounds Check Bypass) |
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67 | 67 | --------------------------------------- |
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.. | .. |
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130 | 130 | steer its indirect branch speculations to gadget code, and measure the |
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131 | 131 | speculative execution's side effects left in level 1 cache to infer the |
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132 | 132 | victim's data. |
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| 133 | + |
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| 134 | +Yet another variant 2 attack vector is for the attacker to poison the |
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| 135 | +Branch History Buffer (BHB) to speculatively steer an indirect branch |
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| 136 | +to a specific Branch Target Buffer (BTB) entry, even if the entry isn't |
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| 137 | +associated with the source address of the indirect branch. Specifically, |
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| 138 | +the BHB might be shared across privilege levels even in the presence of |
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| 139 | +Enhanced IBRS. |
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| 140 | + |
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| 141 | +Currently the only known real-world BHB attack vector is via |
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| 142 | +unprivileged eBPF. Therefore, it's highly recommended to not enable |
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| 143 | +unprivileged eBPF, especially when eIBRS is used (without retpolines). |
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| 144 | +For a full mitigation against BHB attacks, it's recommended to use |
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| 145 | +retpolines (or eIBRS combined with retpolines). |
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133 | 146 | |
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134 | 147 | Attack scenarios |
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135 | 148 | ---------------- |
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.. | .. |
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364 | 377 | |
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365 | 378 | - Kernel status: |
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366 | 379 | |
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367 | | - ==================================== ================================= |
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368 | | - 'Not affected' The processor is not vulnerable |
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369 | | - 'Vulnerable' Vulnerable, no mitigation |
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370 | | - 'Mitigation: Full generic retpoline' Software-focused mitigation |
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371 | | - 'Mitigation: Full AMD retpoline' AMD-specific software mitigation |
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372 | | - 'Mitigation: Enhanced IBRS' Hardware-focused mitigation |
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373 | | - ==================================== ================================= |
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| 380 | + ======================================== ================================= |
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| 381 | + 'Not affected' The processor is not vulnerable |
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| 382 | + 'Mitigation: None' Vulnerable, no mitigation |
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| 383 | + 'Mitigation: Retpolines' Use Retpoline thunks |
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| 384 | + 'Mitigation: LFENCE' Use LFENCE instructions |
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| 385 | + 'Mitigation: Enhanced IBRS' Hardware-focused mitigation |
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| 386 | + 'Mitigation: Enhanced IBRS + Retpolines' Hardware-focused + Retpolines |
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| 387 | + 'Mitigation: Enhanced IBRS + LFENCE' Hardware-focused + LFENCE |
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| 388 | + ======================================== ================================= |
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374 | 389 | |
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375 | 390 | - Firmware status: Show if Indirect Branch Restricted Speculation (IBRS) is |
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376 | 391 | used to protect against Spectre variant 2 attacks when calling firmware (x86 only). |
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.. | .. |
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406 | 421 | ============= =========================================== |
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407 | 422 | 'RSB filling' Protection of RSB on context switch enabled |
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408 | 423 | ============= =========================================== |
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| 424 | + |
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| 425 | + - EIBRS Post-barrier Return Stack Buffer (PBRSB) protection status: |
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| 426 | + |
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| 427 | + =========================== ======================================================= |
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| 428 | + 'PBRSB-eIBRS: SW sequence' CPU is affected and protection of RSB on VMEXIT enabled |
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| 429 | + 'PBRSB-eIBRS: Vulnerable' CPU is vulnerable |
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| 430 | + 'PBRSB-eIBRS: Not affected' CPU is not affected by PBRSB |
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| 431 | + =========================== ======================================================= |
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409 | 432 | |
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410 | 433 | Full mitigation might require a microcode update from the CPU |
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411 | 434 | vendor. When the necessary microcode is not available, the kernel will |
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.. | .. |
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584 | 607 | |
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585 | 608 | Specific mitigations can also be selected manually: |
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586 | 609 | |
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587 | | - retpoline |
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588 | | - replace indirect branches |
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589 | | - retpoline,generic |
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590 | | - google's original retpoline |
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591 | | - retpoline,amd |
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592 | | - AMD-specific minimal thunk |
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| 610 | + retpoline auto pick between generic,lfence |
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| 611 | + retpoline,generic Retpolines |
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| 612 | + retpoline,lfence LFENCE; indirect branch |
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| 613 | + retpoline,amd alias for retpoline,lfence |
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| 614 | + eibrs enhanced IBRS |
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| 615 | + eibrs,retpoline enhanced IBRS + Retpolines |
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| 616 | + eibrs,lfence enhanced IBRS + LFENCE |
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593 | 617 | |
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594 | 618 | Not specifying this option is equivalent to |
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595 | 619 | spectre_v2=auto. |
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.. | .. |
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730 | 754 | |
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731 | 755 | .. _spec_ref6: |
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732 | 756 | |
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733 | | -[6] `Software techniques for managing speculation on AMD processors <https://developer.amd.com/wp-content/resources/90343-B_SoftwareTechniquesforManagingSpeculation_WP_7-18Update_FNL.pdf>`_. |
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| 757 | +[6] `Software techniques for managing speculation on AMD processors <https://developer.amd.com/wp-content/resources/Managing-Speculation-on-AMD-Processors.pdf>`_. |
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734 | 758 | |
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735 | 759 | ARM white papers: |
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736 | 760 | |
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