forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-09-20 cf4ce59b3b70238352c7f1729f0f7223214828ad 
 kernel/sound/soc/rockchip/rockchip_sai.c
....@@ -19,14 +19,19 @@
1919 #include <sound/tlv.h>
2020 
2121 #include "rockchip_sai.h"
22
+#include "rockchip_dlp_pcm.h"
23
+#include "rockchip_utils.h"
2224 
2325 #define DRV_NAME		"rockchip-sai"
2426 
27
+#define CLK_SHIFT_RATE_HZ_MAX	5
2528 #define FW_RATIO_MAX		8
2629 #define FW_RATIO_MIN		1
2730 #define MAXBURST_PER_FIFO	8
2831 
2932 #define DEFAULT_FS		48000
33
+#define TIMEOUT_US		1000
34
+#define WAIT_TIME_MS_MAX	10000
3035 #define QUIRK_ALWAYS_ON		BIT(0)
3136 
3237 enum fpw_mode {
....@@ -45,6 +50,7 @@
4550 	struct snd_dmaengine_dai_dma_data capture_dma_data;
4651 	struct snd_dmaengine_dai_dma_data playback_dma_data;
4752 	struct snd_pcm_substream *substreams[SNDRV_PCM_STREAM_LAST + 1];
53
+	unsigned int wait_time[SNDRV_PCM_STREAM_LAST + 1];
4854 	unsigned int tx_lanes;
4955 	unsigned int rx_lanes;
5056 	unsigned int quirks;
....@@ -54,6 +60,7 @@
5460 	bool has_playback;
5561 	bool is_master_mode;
5662 	bool is_tdm;
63
+	bool is_clk_auto;
5764 };
5865 
5966 static const struct sai_of_quirks {
....@@ -80,11 +87,26 @@
8087 				   SAI_XFER_FSS_DIS);
8188 
8289 	ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_XFER, val,
83
-					      (val & SAI_XFER_FS_IDLE), 10, 100);
90
+					      (val & SAI_XFER_FS_IDLE), 10, TIMEOUT_US);
8491 	if (ret < 0)
8592 		dev_warn(sai->dev, "Failed to idle FS\n");
8693 
8794 	regcache_cache_only(sai->regmap, true);
95
+	/*
96
+	 * After FS idle, should wait at least 2 BCLK cycle to make sure
97
+	 * the CLK gate operation done, and then disable mclk.
98
+	 *
99
+	 * Otherwise, the BCLK is still ungated. once the mclk is enabled,
100
+	 * there maybe a risk that a few BCLK cycle leak. especially for
101
+	 * low speed situation, such as 8k samplerate.
102
+	 *
103
+	 * The best way is to use delay per samplerate, but, the max time
104
+	 * is quite a tiny value, so, let's make it simple to use the max
105
+	 * time.
106
+	 *
107
+	 * The max BCLK cycle time is: 31us @ 8K-8Bit (64K BCLK)
108
+	 */
109
+	udelay(40);
88110 	clk_disable_unprepare(sai->mclk);
89111 	clk_disable_unprepare(sai->hclk);
90112 
....@@ -110,7 +132,7 @@
110132 	if (ret)
111133 		goto err_regmap;
112134 
113
-	if (sai->is_master_mode)
135
+	if (sai->quirks & QUIRK_ALWAYS_ON && sai->is_master_mode)
114136 		regmap_update_bits(sai->regmap, SAI_XFER,
115137 				   SAI_XFER_CLK_MASK |
116138 				   SAI_XFER_FSS_MASK,
....@@ -203,7 +225,7 @@
203225 
204226 	regmap_update_bits(sai->regmap, SAI_CLR, clr, clr);
205227 	ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_CLR, val,
206
-					      !(val & clr), 10, 100);
228
+					      !(val & clr), 10, TIMEOUT_US);
207229 	if (ret < 0) {
208230 		dev_warn(sai->dev, "Failed to clear %u\n", clr);
209231 		goto reset;
....@@ -249,7 +271,7 @@
249271 
250272 	regmap_update_bits(sai->regmap, SAI_XFER, msk, val);
251273 	ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_XFER, val,
252
-					      (val & idle), 10, 100);
274
+					      (val & idle), 10, TIMEOUT_US);
253275 	if (ret < 0)
254276 		dev_warn(sai->dev, "Failed to idle stream %d\n", stream);
255277 
....@@ -402,23 +424,27 @@
402424 {
403425 	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
404426 	struct snd_dmaengine_dai_dma_data *dma_data;
405
-	unsigned int mclk_rate, bclk_rate, div_bclk;
427
+	unsigned int mclk_rate, mclk_req_rate, bclk_rate, div_bclk;
406428 	unsigned int ch_per_lane, lanes, slot_width;
407
-	unsigned int val, fscr, reg;
429
+	unsigned int val, fscr, reg, fifo;
408430 
409431 	dma_data = snd_soc_dai_get_dma_data(dai, substream);
410432 	dma_data->maxburst = MAXBURST_PER_FIFO * params_channels(params) / 2;
411433 
412434 	lanes = rockchip_sai_lanes_auto(params, dai);
413435 
436
+	regmap_read(sai->regmap, SAI_DMACR, &val);
437
+
414438 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
415439 		reg = SAI_TXCR;
416440 		if (sai->tx_lanes)
417441 			lanes = sai->tx_lanes;
442
+		fifo = SAI_DMACR_TDL_V(val) * lanes;
418443 	} else {
419444 		reg = SAI_RXCR;
420445 		if (sai->rx_lanes)
421446 			lanes = sai->rx_lanes;
447
+		fifo = SAI_DMACR_TDL_V(val) * lanes;
422448 	}
423449 
424450 	switch (params_format(params)) {
....@@ -433,6 +459,7 @@
433459 		val = SAI_XCR_VDW(24);
434460 		break;
435461 	case SNDRV_PCM_FORMAT_S32_LE:
462
+	case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
436463 		val = SAI_XCR_VDW(32);
437464 		break;
438465 	default:
....@@ -473,17 +500,58 @@
473500 
474501 	if (sai->is_master_mode) {
475502 		bclk_rate = sai->fw_ratio * slot_width * ch_per_lane * params_rate(params);
503
+		if (sai->is_clk_auto)
504
+			clk_set_rate(sai->mclk, bclk_rate);
476505 		mclk_rate = clk_get_rate(sai->mclk);
477
-		if (mclk_rate < bclk_rate) {
478
-			dev_err(sai->dev, "Mismatch mclk: %u, expected %u at least\n",
479
-				mclk_rate, bclk_rate);
506
+		div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
507
+		mclk_req_rate = bclk_rate * div_bclk;
508
+
509
+		if (mclk_rate < mclk_req_rate - CLK_SHIFT_RATE_HZ_MAX ||
510
+		    mclk_rate > mclk_req_rate + CLK_SHIFT_RATE_HZ_MAX) {
511
+			dev_err(sai->dev, "Mismatch mclk: %u, expected %u (+/- %dHz)\n",
512
+				mclk_rate, mclk_req_rate, CLK_SHIFT_RATE_HZ_MAX);
480513 			return -EINVAL;
481514 		}
482515 
483
-		div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
484
-
485516 		regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK,
486517 				   SAI_CKR_MDIV(div_bclk));
518
+	}
519
+
520
+	rockchip_utils_get_performance(substream, params, dai, fifo);
521
+
522
+	return 0;
523
+}
524
+
525
+static int rockchip_sai_hw_free(struct snd_pcm_substream *substream,
526
+				struct snd_soc_dai *dai)
527
+{
528
+	rockchip_utils_put_performance(substream, dai);
529
+
530
+	return 0;
531
+}
532
+
533
+static int rockchip_sai_prepare(struct snd_pcm_substream *substream,
534
+				struct snd_soc_dai *dai)
535
+{
536
+	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
537
+
538
+	if (sai->is_master_mode) {
539
+		/*
540
+		 * Should wait for one BCLK ready after DIV and then ungate
541
+		 * output clk to achieve the clean clk.
542
+		 *
543
+		 * The best way is to use delay per samplerate, but, the max time
544
+		 * is quite a tiny value, so, let's make it simple to use the max
545
+		 * time.
546
+		 *
547
+		 * The max BCLK cycle time is: 15.6us @ 8K-8Bit (64K BCLK)
548
+		 */
549
+		udelay(20);
550
+		regmap_update_bits(sai->regmap, SAI_XFER,
551
+				   SAI_XFER_CLK_MASK |
552
+				   SAI_XFER_FSS_MASK,
553
+				   SAI_XFER_CLK_EN |
554
+				   SAI_XFER_FSS_EN);
487555 	}
488556 
489557 	return 0;
....@@ -520,7 +588,7 @@
520588 	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
521589 	int ret;
522590 
523
-	if (!freq)
591
+	if (!freq || sai->is_clk_auto)
524592 		return 0;
525593 
526594 	ret = clk_set_rate(sai->mclk, freq);
....@@ -545,11 +613,15 @@
545613 				    struct snd_soc_dai *dai)
546614 {
547615 	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
616
+	int stream = substream->stream;
548617 
549
-	if (sai->substreams[substream->stream])
618
+	if (sai->substreams[stream])
550619 		return -EBUSY;
551620 
552
-	sai->substreams[substream->stream] = substream;
621
+	if (sai->wait_time[stream])
622
+		substream->wait_time = msecs_to_jiffies(sai->wait_time[stream]);
623
+
624
+	sai->substreams[stream] = substream;
553625 
554626 	return 0;
555627 }
....@@ -584,8 +656,10 @@
584656 	.startup = rockchip_sai_startup,
585657 	.shutdown = rockchip_sai_shutdown,
586658 	.hw_params = rockchip_sai_hw_params,
659
+	.hw_free = rockchip_sai_hw_free,
587660 	.set_sysclk = rockchip_sai_set_sysclk,
588661 	.set_fmt = rockchip_sai_set_fmt,
662
+	.prepare = rockchip_sai_prepare,
589663 	.trigger = rockchip_sai_trigger,
590664 	.set_tdm_slot = rockchip_sai_set_tdm_slot,
591665 };
....@@ -741,12 +815,13 @@
741815 	if (sai->has_playback) {
742816 		dai->playback.stream_name = "Playback";
743817 		dai->playback.channels_min = 1;
744
-		dai->playback.channels_max = 128;
745
-		dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
818
+		dai->playback.channels_max = 512;
819
+		dai->playback.rates = SNDRV_PCM_RATE_8000_384000;
746820 		dai->playback.formats = SNDRV_PCM_FMTBIT_S8 |
747821 					SNDRV_PCM_FMTBIT_S16_LE |
748822 					SNDRV_PCM_FMTBIT_S24_LE |
749
-					SNDRV_PCM_FMTBIT_S32_LE;
823
+					SNDRV_PCM_FMTBIT_S32_LE |
824
+					SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
750825 
751826 		sai->playback_dma_data.addr = res->start + SAI_TXDR;
752827 		sai->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
....@@ -756,12 +831,13 @@
756831 	if (sai->has_capture) {
757832 		dai->capture.stream_name = "Capture";
758833 		dai->capture.channels_min = 1;
759
-		dai->capture.channels_max = 128;
760
-		dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
834
+		dai->capture.channels_max = 512;
835
+		dai->capture.rates = SNDRV_PCM_RATE_8000_384000;
761836 		dai->capture.formats = SNDRV_PCM_FMTBIT_S8 |
762837 				       SNDRV_PCM_FMTBIT_S16_LE |
763838 				       SNDRV_PCM_FMTBIT_S24_LE |
764
-				       SNDRV_PCM_FMTBIT_S32_LE;
839
+				       SNDRV_PCM_FMTBIT_S32_LE |
840
+				       SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
765841 
766842 		sai->capture_dma_data.addr = res->start + SAI_RXDR;
767843 		sai->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
....@@ -794,8 +870,8 @@
794870 static const char * const vdj_text[] = { "Right J", "Left J" };
795871 
796872 static const char * const sbw_text[] = {
797
-	" 0", " 0", " 0", " 0", " 0", " 0", " 0", " 8",
798
-	" 9", "10", "11", "12", "13", "14", "15", "16",
873
+	 "0",  "0",  "0",  "0",  "0",  "0",  "0",  "8",
874
+	 "9", "10", "11", "12", "13", "14", "15", "16",
799875 	"17", "18", "19", "20", "21", "22", "23", "24",
800876 	"25", "26", "27", "28", "29", "30", "31", "32", };
801877 
....@@ -803,7 +879,7 @@
803879 
804880 static DECLARE_TLV_DB_SCALE(rmss_tlv, 0, 128, 0);
805881 
806
-static const char * const mss_text[] = { "Master", "Slave" };
882
+static const char * const mss_text[] = { "Slave", "Master" };
807883 
808884 static const char * const ckp_text[] = { "Normal", "Inverted" };
809885 
....@@ -811,48 +887,49 @@
811887 	"From SDO0", "From SDO1", "From SDO2", "From SDO3" };
812888 
813889 static const char * const lps_text[] = { "Disable", "Enable" };
814
-static const char * const sync_out_text[] = { "External", "Internal" };
815
-static const char * const sync_in_text[] = { "External", "Internal" };
890
+static const char * const sync_out_text[] = { "From CRU", "From IO" };
891
+static const char * const sync_in_text[] = { "From IO", "From Sync Port" };
816892 
817893 static const char * const rpaths_text[] = {
818894 	"From SDI0", "From SDI1", "From SDI2", "From SDI3" };
819895 
820896 static const char * const tpaths_text[] = {
821
-	"To SDO0", "To SDO1", "To SDO2", "To SDO3" };
897
+	"From PATH0", "From PATH1", "From PATH2", "From PATH3" };
822898 
823899 /* TXCR */
824
-static SOC_ENUM_SINGLE_DECL(tsft_enum, SAI_TXCR, 22, edge_shift_text);
900
+static SOC_ENUM_SINGLE_DECL(__maybe_unused tsft_enum, SAI_TXCR, 22, edge_shift_text);
825901 static const struct soc_enum tx_lanes_enum =
826902 	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_lanes_text), tx_lanes_text);
827
-static SOC_ENUM_SINGLE_DECL(tsjm_enum, SAI_TXCR, 19, sjm_text);
828
-static SOC_ENUM_SINGLE_DECL(tfbm_enum, SAI_TXCR, 18, fbm_text);
829
-static SOC_ENUM_SINGLE_DECL(tvdj_enum, SAI_TXCR, 10, vdj_text);
830
-static SOC_ENUM_SINGLE_DECL(tsbw_enum, SAI_TXCR,  5, sbw_text);
903
+static SOC_ENUM_SINGLE_DECL(__maybe_unused tsjm_enum, SAI_TXCR, 19, sjm_text);
904
+static SOC_ENUM_SINGLE_DECL(__maybe_unused tfbm_enum, SAI_TXCR, 18, fbm_text);
905
+static SOC_ENUM_SINGLE_DECL(__maybe_unused tvdj_enum, SAI_TXCR, 10, vdj_text);
906
+static SOC_ENUM_SINGLE_DECL(__maybe_unused tsbw_enum, SAI_TXCR,  5, sbw_text);
831907 
832908 /* FSCR */
833
-static SOC_ENUM_SINGLE_DECL(edge_enum, SAI_FSCR, 24, edge_text);
834
-static const struct soc_enum fpw_enum =
909
+static SOC_ENUM_SINGLE_DECL(__maybe_unused edge_enum, SAI_FSCR, 24, edge_text);
910
+static const struct soc_enum __maybe_unused fpw_enum =
835911 	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fpw_text), fpw_text);
836
-static const struct soc_enum fw_ratio_enum =
912
+static const struct soc_enum __maybe_unused fw_ratio_enum =
837913 	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fw_ratio_text), fw_ratio_text);
838914 
839915 /* RXCR */
840
-static SOC_ENUM_SINGLE_DECL(rsft_enum, SAI_RXCR, 22, edge_shift_text);
916
+static SOC_ENUM_SINGLE_DECL(__maybe_unused rsft_enum, SAI_RXCR, 22, edge_shift_text);
841917 static const struct soc_enum rx_lanes_enum =
842918 	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_lanes_text), rx_lanes_text);
843
-static SOC_ENUM_SINGLE_DECL(rsjm_enum, SAI_RXCR, 19, sjm_text);
844
-static SOC_ENUM_SINGLE_DECL(rfbm_enum, SAI_RXCR, 18, fbm_text);
845
-static SOC_ENUM_SINGLE_DECL(rvdj_enum, SAI_RXCR, 10, vdj_text);
846
-static SOC_ENUM_SINGLE_DECL(rsbw_enum, SAI_RXCR,  5, sbw_text);
919
+static SOC_ENUM_SINGLE_DECL(__maybe_unused rsjm_enum, SAI_RXCR, 19, sjm_text);
920
+static SOC_ENUM_SINGLE_DECL(__maybe_unused rfbm_enum, SAI_RXCR, 18, fbm_text);
921
+static SOC_ENUM_SINGLE_DECL(__maybe_unused rvdj_enum, SAI_RXCR, 10, vdj_text);
922
+static SOC_ENUM_SINGLE_DECL(__maybe_unused rsbw_enum, SAI_RXCR,  5, sbw_text);
847923 
848924 /* MONO_CR */
849925 static SOC_ENUM_SINGLE_DECL(rmono_switch, SAI_MONO_CR, 1, mono_text);
850926 static SOC_ENUM_SINGLE_DECL(tmono_switch, SAI_MONO_CR, 0, mono_text);
851927 
852928 /* CKR */
853
-static SOC_ENUM_SINGLE_DECL(mss_switch, SAI_CKR, 2, mss_text);
854
-static SOC_ENUM_SINGLE_DECL(sp_switch,  SAI_CKR, 1, ckp_text);
855
-static SOC_ENUM_SINGLE_DECL(fp_switch,  SAI_CKR, 0, ckp_text);
929
+static const struct soc_enum __maybe_unused mss_switch =
930
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mss_text), mss_text);
931
+static SOC_ENUM_SINGLE_DECL(__maybe_unused sp_switch,  SAI_CKR, 1, ckp_text);
932
+static SOC_ENUM_SINGLE_DECL(__maybe_unused fp_switch,  SAI_CKR, 0, ckp_text);
856933 
857934 /* PATH_SEL */
858935 static SOC_ENUM_SINGLE_DECL(lp3_enum, SAI_PATH_SEL, 28, lpx_text);
....@@ -874,8 +951,8 @@
874951 static SOC_ENUM_SINGLE_DECL(tpath1_enum, SAI_PATH_SEL, 2, tpaths_text);
875952 static SOC_ENUM_SINGLE_DECL(tpath0_enum, SAI_PATH_SEL, 0, tpaths_text);
876953 
877
-static int rockchip_sai_fpw_get(struct snd_kcontrol *kcontrol,
878
-				struct snd_ctl_elem_value *ucontrol)
954
+static int __maybe_unused rockchip_sai_fpw_get(struct snd_kcontrol *kcontrol,
955
+					       struct snd_ctl_elem_value *ucontrol)
879956 {
880957 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
881958 	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
....@@ -885,8 +962,8 @@
885962 	return 0;
886963 }
887964 
888
-static int rockchip_sai_fpw_put(struct snd_kcontrol *kcontrol,
889
-				struct snd_ctl_elem_value *ucontrol)
965
+static int __maybe_unused rockchip_sai_fpw_put(struct snd_kcontrol *kcontrol,
966
+					       struct snd_ctl_elem_value *ucontrol)
890967 {
891968 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
892969 	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
....@@ -901,8 +978,8 @@
901978 	return 1;
902979 }
903980 
904
-static int rockchip_sai_fw_ratio_get(struct snd_kcontrol *kcontrol,
905
-				     struct snd_ctl_elem_value *ucontrol)
981
+static int __maybe_unused rockchip_sai_fw_ratio_get(struct snd_kcontrol *kcontrol,
982
+						    struct snd_ctl_elem_value *ucontrol)
906983 {
907984 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
908985 	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
....@@ -912,8 +989,8 @@
912989 	return 0;
913990 }
914991 
915
-static int rockchip_sai_fw_ratio_put(struct snd_kcontrol *kcontrol,
916
-				     struct snd_ctl_elem_value *ucontrol)
992
+static int __maybe_unused rockchip_sai_fw_ratio_put(struct snd_kcontrol *kcontrol,
993
+						    struct snd_ctl_elem_value *ucontrol)
917994 {
918995 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
919996 	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
....@@ -981,21 +1058,165 @@
9811058 	return 1;
9821059 }
9831060 
984
-static DECLARE_TLV_DB_SCALE(fs_shift_tlv, 0, 8192, 0);
1061
+static int __maybe_unused rockchip_sai_mss_get(struct snd_kcontrol *kcontrol,
1062
+					       struct snd_ctl_elem_value *ucontrol)
1063
+{
1064
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1065
+	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1066
+
1067
+	ucontrol->value.enumerated.item[0] = sai->is_master_mode;
1068
+
1069
+	return 0;
1070
+}
1071
+
1072
+static int __maybe_unused rockchip_sai_mss_put(struct snd_kcontrol *kcontrol,
1073
+					       struct snd_ctl_elem_value *ucontrol)
1074
+{
1075
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1076
+	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1077
+	bool mss;
1078
+
1079
+	/* MUST: do not update mode while stream is running */
1080
+	if (snd_soc_component_active(component))
1081
+		return -EPERM;
1082
+
1083
+	mss = !!ucontrol->value.enumerated.item[0];
1084
+	if (mss == sai->is_master_mode)
1085
+		return 0;
1086
+
1087
+	sai->is_master_mode = mss;
1088
+
1089
+	pm_runtime_get_sync(sai->dev);
1090
+	if (sai->is_master_mode) {
1091
+		/* Switch from Slave to Master */
1092
+		regmap_update_bits(sai->regmap, SAI_CKR,
1093
+				   SAI_CKR_MSS_MASK,
1094
+				   SAI_CKR_MSS_MASTER);
1095
+		regmap_update_bits(sai->regmap, SAI_XFER,
1096
+				   SAI_XFER_CLK_MASK |
1097
+				   SAI_XFER_FSS_MASK,
1098
+				   SAI_XFER_CLK_EN |
1099
+				   SAI_XFER_FSS_EN);
1100
+	} else {
1101
+		/* Switch from Master to Slave */
1102
+		regmap_update_bits(sai->regmap, SAI_CKR,
1103
+				   SAI_CKR_MSS_MASK,
1104
+				   SAI_CKR_MSS_SLAVE);
1105
+		regmap_update_bits(sai->regmap, SAI_XFER,
1106
+				   SAI_XFER_CLK_MASK |
1107
+				   SAI_XFER_FSS_MASK,
1108
+				   SAI_XFER_CLK_DIS |
1109
+				   SAI_XFER_FSS_DIS);
1110
+	}
1111
+	pm_runtime_put(sai->dev);
1112
+
1113
+	return 1;
1114
+}
1115
+
1116
+static int rockchip_sai_clk_auto_get(struct snd_kcontrol *kcontrol,
1117
+				     struct snd_ctl_elem_value *ucontrol)
1118
+{
1119
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1120
+	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1121
+
1122
+	ucontrol->value.integer.value[0] = sai->is_clk_auto;
1123
+
1124
+	return 0;
1125
+}
1126
+
1127
+static int rockchip_sai_clk_auto_put(struct snd_kcontrol *kcontrol,
1128
+				     struct snd_ctl_elem_value *ucontrol)
1129
+{
1130
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1131
+	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1132
+	bool clk_auto = ucontrol->value.integer.value[0];
1133
+
1134
+	if (clk_auto == sai->is_clk_auto)
1135
+		return 0;
1136
+
1137
+	sai->is_clk_auto = clk_auto;
1138
+
1139
+	return 1;
1140
+}
1141
+
1142
+static int rockchip_sai_wait_time_info(struct snd_kcontrol *kcontrol,
1143
+				       struct snd_ctl_elem_info *uinfo)
1144
+{
1145
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1146
+	uinfo->count = 1;
1147
+	uinfo->value.integer.min = 0;
1148
+	uinfo->value.integer.max = WAIT_TIME_MS_MAX;
1149
+	uinfo->value.integer.step = 1;
1150
+
1151
+	return 0;
1152
+}
1153
+
1154
+static int rockchip_sai_rd_wait_time_get(struct snd_kcontrol *kcontrol,
1155
+					 struct snd_ctl_elem_value *ucontrol)
1156
+{
1157
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1158
+	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1159
+
1160
+	ucontrol->value.integer.value[0] = sai->wait_time[SNDRV_PCM_STREAM_CAPTURE];
1161
+
1162
+	return 0;
1163
+}
1164
+
1165
+static int rockchip_sai_rd_wait_time_put(struct snd_kcontrol *kcontrol,
1166
+					 struct snd_ctl_elem_value *ucontrol)
1167
+{
1168
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1169
+	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1170
+
1171
+	if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX)
1172
+		return -EINVAL;
1173
+
1174
+	sai->wait_time[SNDRV_PCM_STREAM_CAPTURE] = ucontrol->value.integer.value[0];
1175
+
1176
+	return 1;
1177
+}
1178
+
1179
+static int rockchip_sai_wr_wait_time_get(struct snd_kcontrol *kcontrol,
1180
+					 struct snd_ctl_elem_value *ucontrol)
1181
+{
1182
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1183
+	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1184
+
1185
+	ucontrol->value.integer.value[0] = sai->wait_time[SNDRV_PCM_STREAM_PLAYBACK];
1186
+
1187
+	return 0;
1188
+}
1189
+
1190
+static int rockchip_sai_wr_wait_time_put(struct snd_kcontrol *kcontrol,
1191
+					 struct snd_ctl_elem_value *ucontrol)
1192
+{
1193
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1194
+	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1195
+
1196
+	if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX)
1197
+		return -EINVAL;
1198
+
1199
+	sai->wait_time[SNDRV_PCM_STREAM_PLAYBACK] = ucontrol->value.integer.value[0];
1200
+
1201
+	return 1;
1202
+}
1203
+
1204
+#define SAI_PCM_WAIT_TIME(xname, xhandler_get, xhandler_put)	\
1205
+{	.iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname,	\
1206
+	.info = rockchip_sai_wait_time_info,			\
1207
+	.get = xhandler_get, .put = xhandler_put }
1208
+
1209
+static __maybe_unused DECLARE_TLV_DB_SCALE(fs_shift_tlv, 0, 8192, 0);
9851210 
9861211 static const struct snd_kcontrol_new rockchip_sai_controls[] = {
987
-
1212
+#ifdef CONFIG_SND_SOC_ROCKCHIP_SAI_VERBOSE
9881213 	SOC_ENUM("Transmit Edge Shift", tsft_enum),
989
-	SOC_ENUM_EXT("Transmit SDOx Select", tx_lanes_enum,
990
-		     rockchip_sai_tx_lanes_get, rockchip_sai_tx_lanes_put),
9911214 	SOC_ENUM("Transmit Store Justified Mode", tsjm_enum),
9921215 	SOC_ENUM("Transmit First Bit Mode", tfbm_enum),
9931216 	SOC_ENUM("Transmit Valid Data Justified", tvdj_enum),
9941217 	SOC_ENUM("Transmit Slot Bit Width", tsbw_enum),
9951218 
9961219 	SOC_ENUM("Receive Edge Shift", rsft_enum),
997
-	SOC_ENUM_EXT("Receive SDIx Select", rx_lanes_enum,
998
-		     rockchip_sai_rx_lanes_get, rockchip_sai_rx_lanes_put),
9991220 	SOC_ENUM("Receive Store Justified Mode", rsjm_enum),
10001221 	SOC_ENUM("Receive First Bit Mode", rfbm_enum),
10011222 	SOC_ENUM("Receive Valid Data Justified", rvdj_enum),
....@@ -1007,14 +1228,24 @@
10071228 	SOC_ENUM_EXT("Frame Width Ratio", fw_ratio_enum,
10081229 		     rockchip_sai_fw_ratio_get, rockchip_sai_fw_ratio_put),
10091230 
1231
+	SOC_ENUM_EXT("Master Slave Mode Select", mss_switch,
1232
+		     rockchip_sai_mss_get, rockchip_sai_mss_put),
1233
+	SOC_ENUM("Sclk Polarity", sp_switch),
1234
+	SOC_ENUM("Frame Sync Polarity", fp_switch),
1235
+
1236
+	SOC_SINGLE_TLV("Transmit Frame Shift Select", SAI_TX_SHIFT,
1237
+		       0, 8192, 0, fs_shift_tlv),
1238
+	SOC_SINGLE_TLV("Receive Frame Shift Select", SAI_RX_SHIFT,
1239
+		       0, 8192, 0, fs_shift_tlv),
1240
+#endif
1241
+	SOC_ENUM_EXT("Transmit SDOx Select", tx_lanes_enum,
1242
+		     rockchip_sai_tx_lanes_get, rockchip_sai_tx_lanes_put),
1243
+	SOC_ENUM_EXT("Receive SDIx Select", rx_lanes_enum,
1244
+		     rockchip_sai_rx_lanes_get, rockchip_sai_rx_lanes_put),
10101245 	SOC_SINGLE_TLV("Receive Mono Slot Select", SAI_MONO_CR,
10111246 		       2, 128, 0, rmss_tlv),
10121247 	SOC_ENUM("Receive Mono Switch", rmono_switch),
10131248 	SOC_ENUM("Transmit Mono Switch", tmono_switch),
1014
-
1015
-	SOC_ENUM("Master / Slave Mode Select", mss_switch),
1016
-	SOC_ENUM("Sclk Polarity", sp_switch),
1017
-	SOC_ENUM("Frame Sync Polarity", fp_switch),
10181249 
10191250 	SOC_ENUM("SDI3 Loopback Src Select", lp3_enum),
10201251 	SOC_ENUM("SDI2 Loopback Src Select", lp2_enum),
....@@ -1030,15 +1261,21 @@
10301261 	SOC_ENUM("Receive PATH2 Source Select", rpath2_enum),
10311262 	SOC_ENUM("Receive PATH1 Source Select", rpath1_enum),
10321263 	SOC_ENUM("Receive PATH0 Source Select", rpath0_enum),
1033
-	SOC_ENUM("Transmit PATH3 Sink Select", tpath3_enum),
1034
-	SOC_ENUM("Transmit PATH2 Sink Select", tpath2_enum),
1035
-	SOC_ENUM("Transmit PATH1 Sink Select", tpath1_enum),
1036
-	SOC_ENUM("Transmit PATH0 Sink Select", tpath0_enum),
1264
+	SOC_ENUM("Transmit SDO3 Source Select", tpath3_enum),
1265
+	SOC_ENUM("Transmit SDO2 Source Select", tpath2_enum),
1266
+	SOC_ENUM("Transmit SDO1 Source Select", tpath1_enum),
1267
+	SOC_ENUM("Transmit SDO0 Source Select", tpath0_enum),
10371268 
1038
-	SOC_SINGLE_TLV("Transmit Frame Shift Select", SAI_TX_SHIFT,
1039
-		       0, 8192, 0, fs_shift_tlv),
1040
-	SOC_SINGLE_TLV("Receive Frame Shift Select", SAI_RX_SHIFT,
1041
-		       0, 8192, 0, fs_shift_tlv),
1269
+	SOC_SINGLE_BOOL_EXT("Clk Auto Switch", 0,
1270
+			    rockchip_sai_clk_auto_get,
1271
+			    rockchip_sai_clk_auto_put),
1272
+
1273
+	SAI_PCM_WAIT_TIME("PCM Read Wait Time MS",
1274
+			  rockchip_sai_rd_wait_time_get,
1275
+			  rockchip_sai_rd_wait_time_put),
1276
+	SAI_PCM_WAIT_TIME("PCM Write Wait Time MS",
1277
+			  rockchip_sai_wr_wait_time_get,
1278
+			  rockchip_sai_wr_wait_time_put),
10421279 };
10431280 
10441281 static const struct snd_soc_component_driver rockchip_sai_component = {
....@@ -1058,6 +1295,9 @@
10581295 		dev_warn_ratelimited(sai->dev, "TX FIFO Underrun\n");
10591296 		regmap_update_bits(sai->regmap, SAI_INTCR,
10601297 				   SAI_INTCR_TXUIC, SAI_INTCR_TXUIC);
1298
+		regmap_update_bits(sai->regmap, SAI_INTCR,
1299
+				   SAI_INTCR_TXUIE_MASK,
1300
+				   SAI_INTCR_TXUIE(0));
10611301 		substream = sai->substreams[SNDRV_PCM_STREAM_PLAYBACK];
10621302 		if (substream)
10631303 			snd_pcm_stop_xrun(substream);
....@@ -1067,6 +1307,9 @@
10671307 		dev_warn_ratelimited(sai->dev, "RX FIFO Overrun\n");
10681308 		regmap_update_bits(sai->regmap, SAI_INTCR,
10691309 				   SAI_INTCR_RXOIC, SAI_INTCR_RXOIC);
1310
+		regmap_update_bits(sai->regmap, SAI_INTCR,
1311
+				   SAI_INTCR_RXOIE_MASK,
1312
+				   SAI_INTCR_RXOIE(0));
10701313 		substream = sai->substreams[SNDRV_PCM_STREAM_CAPTURE];
10711314 		if (substream)
10721315 			snd_pcm_stop_xrun(substream);
....@@ -1110,7 +1353,7 @@
11101353 	int ret = 0, i = 0;
11111354 
11121355 	for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
1113
-		if (of_property_read_bool(sai->dev->of_node, of_quirks[i].quirk))
1356
+		if (device_property_read_bool(sai->dev, of_quirks[i].quirk))
11141357 			sai->quirks |= of_quirks[i].id;
11151358 
11161359 	if (sai->quirks & QUIRK_ALWAYS_ON)
....@@ -1118,6 +1361,29 @@
11181361 
11191362 	return ret;
11201363 }
1364
+
1365
+static int rockchip_sai_get_fifo_count(struct device *dev,
1366
+				       struct snd_pcm_substream *substream)
1367
+{
1368
+	struct rk_sai_dev *sai = dev_get_drvdata(dev);
1369
+	int val = 0;
1370
+
1371
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1372
+		regmap_read(sai->regmap, SAI_TXFIFOLR, &val);
1373
+	else
1374
+		regmap_read(sai->regmap, SAI_RXFIFOLR, &val);
1375
+
1376
+	val = ((val & SAI_FIFOLR_XFL3_MASK) >> SAI_FIFOLR_XFL3_SHIFT) +
1377
+	      ((val & SAI_FIFOLR_XFL2_MASK) >> SAI_FIFOLR_XFL2_SHIFT) +
1378
+	      ((val & SAI_FIFOLR_XFL1_MASK) >> SAI_FIFOLR_XFL1_SHIFT) +
1379
+	      ((val & SAI_FIFOLR_XFL0_MASK) >> SAI_FIFOLR_XFL0_SHIFT);
1380
+
1381
+	return val;
1382
+}
1383
+
1384
+static const struct snd_dlp_config dconfig = {
1385
+	.get_fifo_count = rockchip_sai_get_fifo_count,
1386
+};
11211387 
11221388 static int rockchip_sai_probe(struct platform_device *pdev)
11231389 {
....@@ -1134,6 +1400,8 @@
11341400 
11351401 	sai->dev = &pdev->dev;
11361402 	sai->fw_ratio = 1;
1403
+	/* match to register default */
1404
+	sai->is_master_mode = true;
11371405 	dev_set_drvdata(&pdev->dev, sai);
11381406 
11391407 	sai->rst_h = devm_reset_control_get_optional_exclusive(&pdev->dev, "h");
....@@ -1153,7 +1421,7 @@
11531421 	if (IS_ERR(sai->regmap))
11541422 		return PTR_ERR(sai->regmap);
11551423 
1156
-	irq = platform_get_irq(pdev, 0);
1424
+	irq = platform_get_irq_optional(pdev, 0);
11571425 	if (irq > 0) {
11581426 		ret = devm_request_irq(&pdev->dev, irq, rockchip_sai_isr,
11591427 				       IRQF_SHARED, node->name, sai);
....@@ -1179,6 +1447,20 @@
11791447 	if (ret)
11801448 		return ret;
11811449 
1450
+	ret = rockchip_sai_init_dai(sai, res, &dai);
1451
+	if (ret)
1452
+		return ret;
1453
+
1454
+	/*
1455
+	 * MUST: after pm_runtime_enable step, any register R/W
1456
+	 * should be wrapped with pm_runtime_get_sync/put.
1457
+	 *
1458
+	 * Another approach is to enable the regcache true to
1459
+	 * avoid access HW registers.
1460
+	 *
1461
+	 * Alternatively, performing the registers R/W before
1462
+	 * pm_runtime_enable is also a good option.
1463
+	 */
11821464 	pm_runtime_enable(&pdev->dev);
11831465 	if (!pm_runtime_enabled(&pdev->dev)) {
11841466 		ret = rockchip_sai_runtime_resume(&pdev->dev);
....@@ -1186,17 +1468,22 @@
11861468 			goto err_runtime_disable;
11871469 	}
11881470 
1189
-	ret = rockchip_sai_init_dai(sai, res, &dai);
1190
-	if (ret)
1191
-		goto err_runtime_suspend;
1192
-
11931471 	ret = devm_snd_soc_register_component(&pdev->dev,
11941472 					      &rockchip_sai_component,
11951473 					      dai, 1);
11961474 	if (ret)
11971475 		goto err_runtime_suspend;
11981476 
1199
-	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1477
+	if (device_property_read_bool(&pdev->dev, "rockchip,no-dmaengine")) {
1478
+		dev_info(&pdev->dev, "Used for Multi-DAI\n");
1479
+		return 0;
1480
+	}
1481
+
1482
+	if (device_property_read_bool(&pdev->dev, "rockchip,digital-loopback"))
1483
+		ret = devm_snd_dmaengine_dlp_register(&pdev->dev, &dconfig);
1484
+	else
1485
+		ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1486
+
12001487 	if (ret)
12011488 		goto err_runtime_suspend;
12021489 
....@@ -1220,36 +1507,9 @@
12201507 	return 0;
12211508 }
12221509 
1223
-#ifdef CONFIG_PM_SLEEP
1224
-static int rockchip_sai_suspend(struct device *dev)
1225
-{
1226
-	struct rk_sai_dev *sai = dev_get_drvdata(dev);
1227
-
1228
-	regcache_mark_dirty(sai->regmap);
1229
-
1230
-	return 0;
1231
-}
1232
-
1233
-static int rockchip_sai_resume(struct device *dev)
1234
-{
1235
-	struct rk_sai_dev *sai = dev_get_drvdata(dev);
1236
-	int ret = pm_runtime_get_sync(dev);
1237
-
1238
-	if (ret < 0) {
1239
-		pm_runtime_put_noidle(dev);
1240
-		return ret;
1241
-	}
1242
-
1243
-	ret = regcache_sync(sai->regmap);
1244
-	pm_runtime_put(dev);
1245
-
1246
-	return ret;
1247
-}
1248
-#endif /* CONFIG_PM_SLEEP */
1249
-
12501510 static const struct dev_pm_ops rockchip_sai_pm_ops = {
12511511 	SET_RUNTIME_PM_OPS(rockchip_sai_runtime_suspend, rockchip_sai_runtime_resume, NULL)
1252
-	SET_SYSTEM_SLEEP_PM_OPS(rockchip_sai_suspend, rockchip_sai_resume)
1512
+	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
12531513 };
12541514 
12551515 static struct platform_driver rockchip_sai_driver = {