forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-09-20 cf4ce59b3b70238352c7f1729f0f7223214828ad 
 kernel/sound/soc/rockchip/rockchip_sai.c
....@@ -19,9 +19,12 @@
1919 #include <sound/tlv.h>
2020 
2121 #include "rockchip_sai.h"
22
+#include "rockchip_dlp_pcm.h"
23
+#include "rockchip_utils.h"
2224 
2325 #define DRV_NAME		"rockchip-sai"
2426 
27
+#define CLK_SHIFT_RATE_HZ_MAX	5
2528 #define FW_RATIO_MAX		8
2629 #define FW_RATIO_MIN		1
2730 #define MAXBURST_PER_FIFO	8
....@@ -421,23 +424,27 @@
421424 {
422425 	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
423426 	struct snd_dmaengine_dai_dma_data *dma_data;
424
-	unsigned int mclk_rate, bclk_rate, div_bclk;
427
+	unsigned int mclk_rate, mclk_req_rate, bclk_rate, div_bclk;
425428 	unsigned int ch_per_lane, lanes, slot_width;
426
-	unsigned int val, fscr, reg;
429
+	unsigned int val, fscr, reg, fifo;
427430 
428431 	dma_data = snd_soc_dai_get_dma_data(dai, substream);
429432 	dma_data->maxburst = MAXBURST_PER_FIFO * params_channels(params) / 2;
430433 
431434 	lanes = rockchip_sai_lanes_auto(params, dai);
432435 
436
+	regmap_read(sai->regmap, SAI_DMACR, &val);
437
+
433438 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
434439 		reg = SAI_TXCR;
435440 		if (sai->tx_lanes)
436441 			lanes = sai->tx_lanes;
442
+		fifo = SAI_DMACR_TDL_V(val) * lanes;
437443 	} else {
438444 		reg = SAI_RXCR;
439445 		if (sai->rx_lanes)
440446 			lanes = sai->rx_lanes;
447
+		fifo = SAI_DMACR_TDL_V(val) * lanes;
441448 	}
442449 
443450 	switch (params_format(params)) {
....@@ -496,16 +503,39 @@
496503 		if (sai->is_clk_auto)
497504 			clk_set_rate(sai->mclk, bclk_rate);
498505 		mclk_rate = clk_get_rate(sai->mclk);
499
-		if (mclk_rate < bclk_rate) {
500
-			dev_err(sai->dev, "Mismatch mclk: %u, expected %u at least\n",
501
-				mclk_rate, bclk_rate);
506
+		div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
507
+		mclk_req_rate = bclk_rate * div_bclk;
508
+
509
+		if (mclk_rate < mclk_req_rate - CLK_SHIFT_RATE_HZ_MAX ||
510
+		    mclk_rate > mclk_req_rate + CLK_SHIFT_RATE_HZ_MAX) {
511
+			dev_err(sai->dev, "Mismatch mclk: %u, expected %u (+/- %dHz)\n",
512
+				mclk_rate, mclk_req_rate, CLK_SHIFT_RATE_HZ_MAX);
502513 			return -EINVAL;
503514 		}
504515 
505
-		div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
506
-
507516 		regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK,
508517 				   SAI_CKR_MDIV(div_bclk));
518
+	}
519
+
520
+	rockchip_utils_get_performance(substream, params, dai, fifo);
521
+
522
+	return 0;
523
+}
524
+
525
+static int rockchip_sai_hw_free(struct snd_pcm_substream *substream,
526
+				struct snd_soc_dai *dai)
527
+{
528
+	rockchip_utils_put_performance(substream, dai);
529
+
530
+	return 0;
531
+}
532
+
533
+static int rockchip_sai_prepare(struct snd_pcm_substream *substream,
534
+				struct snd_soc_dai *dai)
535
+{
536
+	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
537
+
538
+	if (sai->is_master_mode) {
509539 		/*
510540 		 * Should wait for one BCLK ready after DIV and then ungate
511541 		 * output clk to achieve the clean clk.
....@@ -626,8 +656,10 @@
626656 	.startup = rockchip_sai_startup,
627657 	.shutdown = rockchip_sai_shutdown,
628658 	.hw_params = rockchip_sai_hw_params,
659
+	.hw_free = rockchip_sai_hw_free,
629660 	.set_sysclk = rockchip_sai_set_sysclk,
630661 	.set_fmt = rockchip_sai_set_fmt,
662
+	.prepare = rockchip_sai_prepare,
631663 	.trigger = rockchip_sai_trigger,
632664 	.set_tdm_slot = rockchip_sai_set_tdm_slot,
633665 };
....@@ -783,8 +815,8 @@
783815 	if (sai->has_playback) {
784816 		dai->playback.stream_name = "Playback";
785817 		dai->playback.channels_min = 1;
786
-		dai->playback.channels_max = 128;
787
-		dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
818
+		dai->playback.channels_max = 512;
819
+		dai->playback.rates = SNDRV_PCM_RATE_8000_384000;
788820 		dai->playback.formats = SNDRV_PCM_FMTBIT_S8 |
789821 					SNDRV_PCM_FMTBIT_S16_LE |
790822 					SNDRV_PCM_FMTBIT_S24_LE |
....@@ -799,8 +831,8 @@
799831 	if (sai->has_capture) {
800832 		dai->capture.stream_name = "Capture";
801833 		dai->capture.channels_min = 1;
802
-		dai->capture.channels_max = 128;
803
-		dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
834
+		dai->capture.channels_max = 512;
835
+		dai->capture.rates = SNDRV_PCM_RATE_8000_384000;
804836 		dai->capture.formats = SNDRV_PCM_FMTBIT_S8 |
805837 				       SNDRV_PCM_FMTBIT_S16_LE |
806838 				       SNDRV_PCM_FMTBIT_S24_LE |
....@@ -855,49 +887,49 @@
855887 	"From SDO0", "From SDO1", "From SDO2", "From SDO3" };
856888 
857889 static const char * const lps_text[] = { "Disable", "Enable" };
858
-static const char * const sync_out_text[] = { "External", "Internal" };
859
-static const char * const sync_in_text[] = { "External", "Internal" };
890
+static const char * const sync_out_text[] = { "From CRU", "From IO" };
891
+static const char * const sync_in_text[] = { "From IO", "From Sync Port" };
860892 
861893 static const char * const rpaths_text[] = {
862894 	"From SDI0", "From SDI1", "From SDI2", "From SDI3" };
863895 
864896 static const char * const tpaths_text[] = {
865
-	"To SDO0", "To SDO1", "To SDO2", "To SDO3" };
897
+	"From PATH0", "From PATH1", "From PATH2", "From PATH3" };
866898 
867899 /* TXCR */
868
-static SOC_ENUM_SINGLE_DECL(tsft_enum, SAI_TXCR, 22, edge_shift_text);
900
+static SOC_ENUM_SINGLE_DECL(__maybe_unused tsft_enum, SAI_TXCR, 22, edge_shift_text);
869901 static const struct soc_enum tx_lanes_enum =
870902 	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_lanes_text), tx_lanes_text);
871
-static SOC_ENUM_SINGLE_DECL(tsjm_enum, SAI_TXCR, 19, sjm_text);
872
-static SOC_ENUM_SINGLE_DECL(tfbm_enum, SAI_TXCR, 18, fbm_text);
873
-static SOC_ENUM_SINGLE_DECL(tvdj_enum, SAI_TXCR, 10, vdj_text);
874
-static SOC_ENUM_SINGLE_DECL(tsbw_enum, SAI_TXCR,  5, sbw_text);
903
+static SOC_ENUM_SINGLE_DECL(__maybe_unused tsjm_enum, SAI_TXCR, 19, sjm_text);
904
+static SOC_ENUM_SINGLE_DECL(__maybe_unused tfbm_enum, SAI_TXCR, 18, fbm_text);
905
+static SOC_ENUM_SINGLE_DECL(__maybe_unused tvdj_enum, SAI_TXCR, 10, vdj_text);
906
+static SOC_ENUM_SINGLE_DECL(__maybe_unused tsbw_enum, SAI_TXCR,  5, sbw_text);
875907 
876908 /* FSCR */
877
-static SOC_ENUM_SINGLE_DECL(edge_enum, SAI_FSCR, 24, edge_text);
878
-static const struct soc_enum fpw_enum =
909
+static SOC_ENUM_SINGLE_DECL(__maybe_unused edge_enum, SAI_FSCR, 24, edge_text);
910
+static const struct soc_enum __maybe_unused fpw_enum =
879911 	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fpw_text), fpw_text);
880
-static const struct soc_enum fw_ratio_enum =
912
+static const struct soc_enum __maybe_unused fw_ratio_enum =
881913 	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fw_ratio_text), fw_ratio_text);
882914 
883915 /* RXCR */
884
-static SOC_ENUM_SINGLE_DECL(rsft_enum, SAI_RXCR, 22, edge_shift_text);
916
+static SOC_ENUM_SINGLE_DECL(__maybe_unused rsft_enum, SAI_RXCR, 22, edge_shift_text);
885917 static const struct soc_enum rx_lanes_enum =
886918 	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_lanes_text), rx_lanes_text);
887
-static SOC_ENUM_SINGLE_DECL(rsjm_enum, SAI_RXCR, 19, sjm_text);
888
-static SOC_ENUM_SINGLE_DECL(rfbm_enum, SAI_RXCR, 18, fbm_text);
889
-static SOC_ENUM_SINGLE_DECL(rvdj_enum, SAI_RXCR, 10, vdj_text);
890
-static SOC_ENUM_SINGLE_DECL(rsbw_enum, SAI_RXCR,  5, sbw_text);
919
+static SOC_ENUM_SINGLE_DECL(__maybe_unused rsjm_enum, SAI_RXCR, 19, sjm_text);
920
+static SOC_ENUM_SINGLE_DECL(__maybe_unused rfbm_enum, SAI_RXCR, 18, fbm_text);
921
+static SOC_ENUM_SINGLE_DECL(__maybe_unused rvdj_enum, SAI_RXCR, 10, vdj_text);
922
+static SOC_ENUM_SINGLE_DECL(__maybe_unused rsbw_enum, SAI_RXCR,  5, sbw_text);
891923 
892924 /* MONO_CR */
893925 static SOC_ENUM_SINGLE_DECL(rmono_switch, SAI_MONO_CR, 1, mono_text);
894926 static SOC_ENUM_SINGLE_DECL(tmono_switch, SAI_MONO_CR, 0, mono_text);
895927 
896928 /* CKR */
897
-static const struct soc_enum mss_switch =
929
+static const struct soc_enum __maybe_unused mss_switch =
898930 	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mss_text), mss_text);
899
-static SOC_ENUM_SINGLE_DECL(sp_switch,  SAI_CKR, 1, ckp_text);
900
-static SOC_ENUM_SINGLE_DECL(fp_switch,  SAI_CKR, 0, ckp_text);
931
+static SOC_ENUM_SINGLE_DECL(__maybe_unused sp_switch,  SAI_CKR, 1, ckp_text);
932
+static SOC_ENUM_SINGLE_DECL(__maybe_unused fp_switch,  SAI_CKR, 0, ckp_text);
901933 
902934 /* PATH_SEL */
903935 static SOC_ENUM_SINGLE_DECL(lp3_enum, SAI_PATH_SEL, 28, lpx_text);
....@@ -919,8 +951,8 @@
919951 static SOC_ENUM_SINGLE_DECL(tpath1_enum, SAI_PATH_SEL, 2, tpaths_text);
920952 static SOC_ENUM_SINGLE_DECL(tpath0_enum, SAI_PATH_SEL, 0, tpaths_text);
921953 
922
-static int rockchip_sai_fpw_get(struct snd_kcontrol *kcontrol,
923
-				struct snd_ctl_elem_value *ucontrol)
954
+static int __maybe_unused rockchip_sai_fpw_get(struct snd_kcontrol *kcontrol,
955
+					       struct snd_ctl_elem_value *ucontrol)
924956 {
925957 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
926958 	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
....@@ -930,8 +962,8 @@
930962 	return 0;
931963 }
932964 
933
-static int rockchip_sai_fpw_put(struct snd_kcontrol *kcontrol,
934
-				struct snd_ctl_elem_value *ucontrol)
965
+static int __maybe_unused rockchip_sai_fpw_put(struct snd_kcontrol *kcontrol,
966
+					       struct snd_ctl_elem_value *ucontrol)
935967 {
936968 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
937969 	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
....@@ -946,8 +978,8 @@
946978 	return 1;
947979 }
948980 
949
-static int rockchip_sai_fw_ratio_get(struct snd_kcontrol *kcontrol,
950
-				     struct snd_ctl_elem_value *ucontrol)
981
+static int __maybe_unused rockchip_sai_fw_ratio_get(struct snd_kcontrol *kcontrol,
982
+						    struct snd_ctl_elem_value *ucontrol)
951983 {
952984 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
953985 	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
....@@ -957,8 +989,8 @@
957989 	return 0;
958990 }
959991 
960
-static int rockchip_sai_fw_ratio_put(struct snd_kcontrol *kcontrol,
961
-				     struct snd_ctl_elem_value *ucontrol)
992
+static int __maybe_unused rockchip_sai_fw_ratio_put(struct snd_kcontrol *kcontrol,
993
+						    struct snd_ctl_elem_value *ucontrol)
962994 {
963995 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
964996 	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
....@@ -1026,8 +1058,8 @@
10261058 	return 1;
10271059 }
10281060 
1029
-static int rockchip_sai_mss_get(struct snd_kcontrol *kcontrol,
1030
-				struct snd_ctl_elem_value *ucontrol)
1061
+static int __maybe_unused rockchip_sai_mss_get(struct snd_kcontrol *kcontrol,
1062
+					       struct snd_ctl_elem_value *ucontrol)
10311063 {
10321064 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
10331065 	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
....@@ -1037,8 +1069,8 @@
10371069 	return 0;
10381070 }
10391071 
1040
-static int rockchip_sai_mss_put(struct snd_kcontrol *kcontrol,
1041
-				struct snd_ctl_elem_value *ucontrol)
1072
+static int __maybe_unused rockchip_sai_mss_put(struct snd_kcontrol *kcontrol,
1073
+					       struct snd_ctl_elem_value *ucontrol)
10421074 {
10431075 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
10441076 	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
....@@ -1174,21 +1206,17 @@
11741206 	.info = rockchip_sai_wait_time_info,			\
11751207 	.get = xhandler_get, .put = xhandler_put }
11761208 
1177
-static DECLARE_TLV_DB_SCALE(fs_shift_tlv, 0, 8192, 0);
1209
+static __maybe_unused DECLARE_TLV_DB_SCALE(fs_shift_tlv, 0, 8192, 0);
11781210 
11791211 static const struct snd_kcontrol_new rockchip_sai_controls[] = {
1180
-
1212
+#ifdef CONFIG_SND_SOC_ROCKCHIP_SAI_VERBOSE
11811213 	SOC_ENUM("Transmit Edge Shift", tsft_enum),
1182
-	SOC_ENUM_EXT("Transmit SDOx Select", tx_lanes_enum,
1183
-		     rockchip_sai_tx_lanes_get, rockchip_sai_tx_lanes_put),
11841214 	SOC_ENUM("Transmit Store Justified Mode", tsjm_enum),
11851215 	SOC_ENUM("Transmit First Bit Mode", tfbm_enum),
11861216 	SOC_ENUM("Transmit Valid Data Justified", tvdj_enum),
11871217 	SOC_ENUM("Transmit Slot Bit Width", tsbw_enum),
11881218 
11891219 	SOC_ENUM("Receive Edge Shift", rsft_enum),
1190
-	SOC_ENUM_EXT("Receive SDIx Select", rx_lanes_enum,
1191
-		     rockchip_sai_rx_lanes_get, rockchip_sai_rx_lanes_put),
11921220 	SOC_ENUM("Receive Store Justified Mode", rsjm_enum),
11931221 	SOC_ENUM("Receive First Bit Mode", rfbm_enum),
11941222 	SOC_ENUM("Receive Valid Data Justified", rvdj_enum),
....@@ -1200,15 +1228,24 @@
12001228 	SOC_ENUM_EXT("Frame Width Ratio", fw_ratio_enum,
12011229 		     rockchip_sai_fw_ratio_get, rockchip_sai_fw_ratio_put),
12021230 
1231
+	SOC_ENUM_EXT("Master Slave Mode Select", mss_switch,
1232
+		     rockchip_sai_mss_get, rockchip_sai_mss_put),
1233
+	SOC_ENUM("Sclk Polarity", sp_switch),
1234
+	SOC_ENUM("Frame Sync Polarity", fp_switch),
1235
+
1236
+	SOC_SINGLE_TLV("Transmit Frame Shift Select", SAI_TX_SHIFT,
1237
+		       0, 8192, 0, fs_shift_tlv),
1238
+	SOC_SINGLE_TLV("Receive Frame Shift Select", SAI_RX_SHIFT,
1239
+		       0, 8192, 0, fs_shift_tlv),
1240
+#endif
1241
+	SOC_ENUM_EXT("Transmit SDOx Select", tx_lanes_enum,
1242
+		     rockchip_sai_tx_lanes_get, rockchip_sai_tx_lanes_put),
1243
+	SOC_ENUM_EXT("Receive SDIx Select", rx_lanes_enum,
1244
+		     rockchip_sai_rx_lanes_get, rockchip_sai_rx_lanes_put),
12031245 	SOC_SINGLE_TLV("Receive Mono Slot Select", SAI_MONO_CR,
12041246 		       2, 128, 0, rmss_tlv),
12051247 	SOC_ENUM("Receive Mono Switch", rmono_switch),
12061248 	SOC_ENUM("Transmit Mono Switch", tmono_switch),
1207
-
1208
-	SOC_ENUM_EXT("Master / Slave Mode Select", mss_switch,
1209
-		     rockchip_sai_mss_get, rockchip_sai_mss_put),
1210
-	SOC_ENUM("Sclk Polarity", sp_switch),
1211
-	SOC_ENUM("Frame Sync Polarity", fp_switch),
12121249 
12131250 	SOC_ENUM("SDI3 Loopback Src Select", lp3_enum),
12141251 	SOC_ENUM("SDI2 Loopback Src Select", lp2_enum),
....@@ -1224,15 +1261,10 @@
12241261 	SOC_ENUM("Receive PATH2 Source Select", rpath2_enum),
12251262 	SOC_ENUM("Receive PATH1 Source Select", rpath1_enum),
12261263 	SOC_ENUM("Receive PATH0 Source Select", rpath0_enum),
1227
-	SOC_ENUM("Transmit PATH3 Sink Select", tpath3_enum),
1228
-	SOC_ENUM("Transmit PATH2 Sink Select", tpath2_enum),
1229
-	SOC_ENUM("Transmit PATH1 Sink Select", tpath1_enum),
1230
-	SOC_ENUM("Transmit PATH0 Sink Select", tpath0_enum),
1231
-
1232
-	SOC_SINGLE_TLV("Transmit Frame Shift Select", SAI_TX_SHIFT,
1233
-		       0, 8192, 0, fs_shift_tlv),
1234
-	SOC_SINGLE_TLV("Receive Frame Shift Select", SAI_RX_SHIFT,
1235
-		       0, 8192, 0, fs_shift_tlv),
1264
+	SOC_ENUM("Transmit SDO3 Source Select", tpath3_enum),
1265
+	SOC_ENUM("Transmit SDO2 Source Select", tpath2_enum),
1266
+	SOC_ENUM("Transmit SDO1 Source Select", tpath1_enum),
1267
+	SOC_ENUM("Transmit SDO0 Source Select", tpath0_enum),
12361268 
12371269 	SOC_SINGLE_BOOL_EXT("Clk Auto Switch", 0,
12381270 			    rockchip_sai_clk_auto_get,
....@@ -1263,6 +1295,9 @@
12631295 		dev_warn_ratelimited(sai->dev, "TX FIFO Underrun\n");
12641296 		regmap_update_bits(sai->regmap, SAI_INTCR,
12651297 				   SAI_INTCR_TXUIC, SAI_INTCR_TXUIC);
1298
+		regmap_update_bits(sai->regmap, SAI_INTCR,
1299
+				   SAI_INTCR_TXUIE_MASK,
1300
+				   SAI_INTCR_TXUIE(0));
12661301 		substream = sai->substreams[SNDRV_PCM_STREAM_PLAYBACK];
12671302 		if (substream)
12681303 			snd_pcm_stop_xrun(substream);
....@@ -1272,6 +1307,9 @@
12721307 		dev_warn_ratelimited(sai->dev, "RX FIFO Overrun\n");
12731308 		regmap_update_bits(sai->regmap, SAI_INTCR,
12741309 				   SAI_INTCR_RXOIC, SAI_INTCR_RXOIC);
1310
+		regmap_update_bits(sai->regmap, SAI_INTCR,
1311
+				   SAI_INTCR_RXOIE_MASK,
1312
+				   SAI_INTCR_RXOIE(0));
12751313 		substream = sai->substreams[SNDRV_PCM_STREAM_CAPTURE];
12761314 		if (substream)
12771315 			snd_pcm_stop_xrun(substream);
....@@ -1323,6 +1361,29 @@
13231361 
13241362 	return ret;
13251363 }
1364
+
1365
+static int rockchip_sai_get_fifo_count(struct device *dev,
1366
+				       struct snd_pcm_substream *substream)
1367
+{
1368
+	struct rk_sai_dev *sai = dev_get_drvdata(dev);
1369
+	int val = 0;
1370
+
1371
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1372
+		regmap_read(sai->regmap, SAI_TXFIFOLR, &val);
1373
+	else
1374
+		regmap_read(sai->regmap, SAI_RXFIFOLR, &val);
1375
+
1376
+	val = ((val & SAI_FIFOLR_XFL3_MASK) >> SAI_FIFOLR_XFL3_SHIFT) +
1377
+	      ((val & SAI_FIFOLR_XFL2_MASK) >> SAI_FIFOLR_XFL2_SHIFT) +
1378
+	      ((val & SAI_FIFOLR_XFL1_MASK) >> SAI_FIFOLR_XFL1_SHIFT) +
1379
+	      ((val & SAI_FIFOLR_XFL0_MASK) >> SAI_FIFOLR_XFL0_SHIFT);
1380
+
1381
+	return val;
1382
+}
1383
+
1384
+static const struct snd_dlp_config dconfig = {
1385
+	.get_fifo_count = rockchip_sai_get_fifo_count,
1386
+};
13261387 
13271388 static int rockchip_sai_probe(struct platform_device *pdev)
13281389 {
....@@ -1386,16 +1447,26 @@
13861447 	if (ret)
13871448 		return ret;
13881449 
1450
+	ret = rockchip_sai_init_dai(sai, res, &dai);
1451
+	if (ret)
1452
+		return ret;
1453
+
1454
+	/*
1455
+	 * MUST: after pm_runtime_enable step, any register R/W
1456
+	 * should be wrapped with pm_runtime_get_sync/put.
1457
+	 *
1458
+	 * Another approach is to enable the regcache true to
1459
+	 * avoid access HW registers.
1460
+	 *
1461
+	 * Alternatively, performing the registers R/W before
1462
+	 * pm_runtime_enable is also a good option.
1463
+	 */
13891464 	pm_runtime_enable(&pdev->dev);
13901465 	if (!pm_runtime_enabled(&pdev->dev)) {
13911466 		ret = rockchip_sai_runtime_resume(&pdev->dev);
13921467 		if (ret)
13931468 			goto err_runtime_disable;
13941469 	}
1395
-
1396
-	ret = rockchip_sai_init_dai(sai, res, &dai);
1397
-	if (ret)
1398
-		goto err_runtime_suspend;
13991470 
14001471 	ret = devm_snd_soc_register_component(&pdev->dev,
14011472 					      &rockchip_sai_component,
....@@ -1408,7 +1479,11 @@
14081479 		return 0;
14091480 	}
14101481 
1411
-	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1482
+	if (device_property_read_bool(&pdev->dev, "rockchip,digital-loopback"))
1483
+		ret = devm_snd_dmaengine_dlp_register(&pdev->dev, &dconfig);
1484
+	else
1485
+		ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1486
+
14121487 	if (ret)
14131488 		goto err_runtime_suspend;
14141489 
....@@ -1432,33 +1507,9 @@
14321507 	return 0;
14331508 }
14341509 
1435
-#ifdef CONFIG_PM_SLEEP
1436
-static int rockchip_sai_suspend(struct device *dev)
1437
-{
1438
-	struct rk_sai_dev *sai = dev_get_drvdata(dev);
1439
-
1440
-	regcache_mark_dirty(sai->regmap);
1441
-
1442
-	return 0;
1443
-}
1444
-
1445
-static int rockchip_sai_resume(struct device *dev)
1446
-{
1447
-	struct rk_sai_dev *sai = dev_get_drvdata(dev);
1448
-	int ret = pm_runtime_resume_and_get(dev);
1449
-
1450
-	if (ret < 0)
1451
-		return ret;
1452
-	ret = regcache_sync(sai->regmap);
1453
-	pm_runtime_put(dev);
1454
-
1455
-	return ret;
1456
-}
1457
-#endif /* CONFIG_PM_SLEEP */
1458
-
14591510 static const struct dev_pm_ops rockchip_sai_pm_ops = {
14601511 	SET_RUNTIME_PM_OPS(rockchip_sai_runtime_suspend, rockchip_sai_runtime_resume, NULL)
1461
-	SET_SYSTEM_SLEEP_PM_OPS(rockchip_sai_suspend, rockchip_sai_resume)
1512
+	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
14621513 };
14631514 
14641515 static struct platform_driver rockchip_sai_driver = {