forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-09-20 cf4ce59b3b70238352c7f1729f0f7223214828ad 
 kernel/sound/soc/rockchip/rockchip_i2s_tdm.h
....@@ -24,8 +24,9 @@
2424 #define I2S_TXCR_RCNT_SHIFT	17
2525 #define I2S_TXCR_RCNT_MASK	(0x3f << I2S_TXCR_RCNT_SHIFT)
2626 #define I2S_TXCR_CSR_SHIFT	15
27
-#define I2S_TXCR_CSR(x)		((x) << I2S_TXCR_CSR_SHIFT)
2827 #define I2S_TXCR_CSR_MASK	(3 << I2S_TXCR_CSR_SHIFT)
28
+#define I2S_TXCR_CSR(x)		((x) << I2S_TXCR_CSR_SHIFT)
29
+#define I2S_TXCR_CSR_V(v)	((((v) & I2S_TXCR_CSR_MASK) >> 15) + 1)
2930 #define I2S_TXCR_HWT		BIT(14)
3031 #define I2S_TXCR_SJM_SHIFT	12
3132 #define I2S_TXCR_SJM_R		(0 << I2S_TXCR_SJM_SHIFT)
....@@ -59,8 +60,9 @@
5960 #define I2S_RXCR_PATH_MASK(x)	(0x3 << I2S_RXCR_PATH_SHIFT(x))
6061 #define I2S_RXCR_PATH(x, v)	((v) << I2S_RXCR_PATH_SHIFT(x))
6162 #define I2S_RXCR_CSR_SHIFT	15
62
-#define I2S_RXCR_CSR(x)		((x) << I2S_RXCR_CSR_SHIFT)
6363 #define I2S_RXCR_CSR_MASK	(3 << I2S_RXCR_CSR_SHIFT)
64
+#define I2S_RXCR_CSR(x)		((x) << I2S_RXCR_CSR_SHIFT)
65
+#define I2S_RXCR_CSR_V(v)	((((v) & I2S_RXCR_CSR_MASK) >> 15) + 1)
6466 #define I2S_RXCR_HWT		BIT(14)
6567 #define I2S_RXCR_SJM_SHIFT	12
6668 #define I2S_RXCR_SJM_R		(0 << I2S_RXCR_SJM_SHIFT)
....@@ -144,15 +146,21 @@
144146 #define I2S_DMACR_RDE_SHIFT	24
145147 #define I2S_DMACR_RDE_DISABLE	(0 << I2S_DMACR_RDE_SHIFT)
146148 #define I2S_DMACR_RDE_ENABLE	(1 << I2S_DMACR_RDE_SHIFT)
149
+#define I2S_DMACR_RDE_MASK	(1 << I2S_DMACR_RDE_SHIFT)
150
+#define I2S_DMACR_RDE(x)	((x) << I2S_DMACR_RDE_SHIFT)
147151 #define I2S_DMACR_RDL_SHIFT	16
148
-#define I2S_DMACR_RDL(x)	(((x) - 1) << I2S_DMACR_RDL_SHIFT)
149152 #define I2S_DMACR_RDL_MASK	(0x1f << I2S_DMACR_RDL_SHIFT)
153
+#define I2S_DMACR_RDL(x)	(((x) - 1) << I2S_DMACR_RDL_SHIFT)
154
+#define I2S_DMACR_RDL_V(v)	((((v) & I2S_DMACR_RDL_MASK) >> 16) + 1)
150155 #define I2S_DMACR_TDE_SHIFT	8
151156 #define I2S_DMACR_TDE_DISABLE	(0 << I2S_DMACR_TDE_SHIFT)
152157 #define I2S_DMACR_TDE_ENABLE	(1 << I2S_DMACR_TDE_SHIFT)
158
+#define I2S_DMACR_TDE_MASK	(1 << I2S_DMACR_TDE_SHIFT)
159
+#define I2S_DMACR_TDE(x)	((x) << I2S_DMACR_TDE_SHIFT)
153160 #define I2S_DMACR_TDL_SHIFT	0
154
-#define I2S_DMACR_TDL(x)	((x) << I2S_DMACR_TDL_SHIFT)
155161 #define I2S_DMACR_TDL_MASK	(0x1f << I2S_DMACR_TDL_SHIFT)
162
+#define I2S_DMACR_TDL(x)	((x) << I2S_DMACR_TDL_SHIFT)
163
+#define I2S_DMACR_TDL_V(v)	(((v) & I2S_DMACR_TDL_MASK) >> 0)
156164 
157165 /*
158166  * INTCR
....@@ -162,8 +170,8 @@
162170 #define I2S_INTCR_RFT(x)	(((x) - 1) << I2S_INTCR_RFT_SHIFT)
163171 #define I2S_INTCR_RXOIC		BIT(18)
164172 #define I2S_INTCR_RXOIE_SHIFT	17
165
-#define I2S_INTCR_RXOIE_DISABLE	(0 << I2S_INTCR_RXOIE_SHIFT)
166
-#define I2S_INTCR_RXOIE_ENABLE	(1 << I2S_INTCR_RXOIE_SHIFT)
173
+#define I2S_INTCR_RXOIE_MASK	(1 << I2S_INTCR_RXOIE_SHIFT)
174
+#define I2S_INTCR_RXOIE(x)	((x) << I2S_INTCR_RXOIE_SHIFT)
167175 #define I2S_INTCR_RXFIE_SHIFT	16
168176 #define I2S_INTCR_RXFIE_DISABLE	(0 << I2S_INTCR_RXFIE_SHIFT)
169177 #define I2S_INTCR_RXFIE_ENABLE	(1 << I2S_INTCR_RXFIE_SHIFT)
....@@ -172,8 +180,8 @@
172180 #define I2S_INTCR_TFT_MASK	(0x1f << I2S_INTCR_TFT_SHIFT)
173181 #define I2S_INTCR_TXUIC		BIT(2)
174182 #define I2S_INTCR_TXUIE_SHIFT	1
175
-#define I2S_INTCR_TXUIE_DISABLE	(0 << I2S_INTCR_TXUIE_SHIFT)
176
-#define I2S_INTCR_TXUIE_ENABLE	(1 << I2S_INTCR_TXUIE_SHIFT)
183
+#define I2S_INTCR_TXUIE_MASK	(1 << I2S_INTCR_TXUIE_SHIFT)
184
+#define I2S_INTCR_TXUIE(x)	((x) << I2S_INTCR_TXUIE_SHIFT)
177185 
178186 /*
179187  * INTSR
....@@ -199,12 +207,37 @@
199207  * XFER
200208  * Transfer start register
201209  */
210
+/*
211
+ * lp mode2 swap:
212
+ * i2s sdi0_l <- i2s sdo0_l
213
+ * i2s sdi0_r <- codec sdo_r
214
+ *
215
+ * lp mode2:
216
+ * i2s sdi0_l <- codec sdo_l
217
+ * i2s sdi0_r <- i2s sdo0_r
218
+ *
219
+ * lp mode1:
220
+ * i2s sdi0_l <- codec sdo_l
221
+ * i2s sdi0_r <- codec sdo_r
222
+ * i2s sdi1_l <- i2s sdo0_l
223
+ * i2s sdi1_r <- i2s sdo0_r
224
+ *
225
+ */
226
+#define I2S_XFER_LP_MODE_MASK	GENMASK(4, 2)
227
+#define I2S_XFER_LP_MODE_2_SWAP	(BIT(4) | BIT(3))
228
+#define I2S_XFER_LP_MODE_2	BIT(3)
229
+#define I2S_XFER_LP_MODE_1	BIT(2)
230
+#define I2S_XFER_LP_MODE_DIS	0
202231 #define I2S_XFER_RXS_SHIFT	1
203232 #define I2S_XFER_RXS_STOP	(0 << I2S_XFER_RXS_SHIFT)
204233 #define I2S_XFER_RXS_START	(1 << I2S_XFER_RXS_SHIFT)
234
+#define I2S_XFER_RXS_MASK	(1 << I2S_XFER_RXS_SHIFT)
235
+#define I2S_XFER_RXS(x)		((x) << I2S_XFER_RXS_SHIFT)
205236 #define I2S_XFER_TXS_SHIFT	0
206237 #define I2S_XFER_TXS_STOP	(0 << I2S_XFER_TXS_SHIFT)
207238 #define I2S_XFER_TXS_START	(1 << I2S_XFER_TXS_SHIFT)
239
+#define I2S_XFER_TXS_MASK	(1 << I2S_XFER_TXS_SHIFT)
240
+#define I2S_XFER_TXS(x)		((x) << I2S_XFER_TXS_SHIFT)
208241 
209242 /*
210243  * CLR