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2024-09-20 cf4ce59b3b70238352c7f1729f0f7223214828ad 
 kernel/drivers/net/dsa/mv88e6xxx/global2.h
....@@ -1,3 +1,4 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23  * Marvell 88E6xxx Switch Global 2 Registers support
34  *
....@@ -5,11 +6,6 @@
56  *
67  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
78  *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
8
- *
9
- * This program is free software; you can redistribute it and/or modify
10
- * it under the terms of the GNU General Public License as published by
11
- * the Free Software Foundation; either version 2 of the License, or
12
- * (at your option) any later version.
139  */
1410 
1511 #ifndef _MV88E6XXX_GLOBAL2_H
....@@ -117,7 +113,16 @@
117113 #define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK	0x00ff
118114 
119115 /* Offset 0x0E: ATU Stats Register */
120
-#define MV88E6XXX_G2_ATU_STATS		0x0e
116
+#define MV88E6XXX_G2_ATU_STATS				0x0e
117
+#define MV88E6XXX_G2_ATU_STATS_BIN_0			(0x0 << 14)
118
+#define MV88E6XXX_G2_ATU_STATS_BIN_1			(0x1 << 14)
119
+#define MV88E6XXX_G2_ATU_STATS_BIN_2			(0x2 << 14)
120
+#define MV88E6XXX_G2_ATU_STATS_BIN_3			(0x3 << 14)
121
+#define MV88E6XXX_G2_ATU_STATS_MODE_ALL			(0x0 << 12)
122
+#define MV88E6XXX_G2_ATU_STATS_MODE_ALL_DYNAMIC		(0x1 << 12)
123
+#define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL		(0x2 << 12)
124
+#define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL_DYNAMIC	(0x3 << 12)
125
+#define MV88E6XXX_G2_ATU_STATS_MASK			0x0fff
121126 
122127 /* Offset 0x0F: Priority Override Table */
123128 #define MV88E6XXX_G2_PRIO_OVERRIDE		0x0f
....@@ -206,6 +211,18 @@
206211 #define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK	0x00ff
207212 
208213 /* Offset 0x1B: Watch Dog Control Register */
214
+#define MV88E6250_G2_WDOG_CTL			0x1b
215
+#define MV88E6250_G2_WDOG_CTL_QC_HISTORY	0x0100
216
+#define MV88E6250_G2_WDOG_CTL_QC_EVENT		0x0080
217
+#define MV88E6250_G2_WDOG_CTL_QC_ENABLE		0x0040
218
+#define MV88E6250_G2_WDOG_CTL_EGRESS_HISTORY	0x0020
219
+#define MV88E6250_G2_WDOG_CTL_EGRESS_EVENT	0x0010
220
+#define MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE	0x0008
221
+#define MV88E6250_G2_WDOG_CTL_FORCE_IRQ		0x0004
222
+#define MV88E6250_G2_WDOG_CTL_HISTORY		0x0002
223
+#define MV88E6250_G2_WDOG_CTL_SWRESET		0x0001
224
+
225
+/* Offset 0x1B: Watch Dog Control Register */
209226 #define MV88E6352_G2_WDOG_CTL			0x1b
210227 #define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT	0x0080
211228 #define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT	0x0040
....@@ -287,8 +304,8 @@
287304 
288305 int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
289306 int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
290
-int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update);
291
-int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask);
307
+int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg,
308
+			  int bit, int val);
292309 
293310 int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
294311 int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
....@@ -332,8 +349,10 @@
332349 
333350 int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target,
334351 				      int port);
352
+int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip);
335353 
336354 extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops;
355
+extern const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops;
337356 extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops;
338357 
339358 extern const struct mv88e6xxx_avb_ops mv88e6165_avb_ops;
....@@ -344,6 +363,8 @@
344363 
345364 int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
346365 				      bool external);
366
+int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin);
367
+int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats);
347368 
348369 #else /* !CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */
349370 
....@@ -367,12 +388,8 @@
367388 	return -EOPNOTSUPP;
368389 }
369390 
370
-static inline int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update)
371
-{
372
-	return -EOPNOTSUPP;
373
-}
374
-
375
-static inline int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
391
+static inline int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip,
392
+					int reg, int bit, int val)
376393 {
377394 	return -EOPNOTSUPP;
378395 }
....@@ -484,6 +501,7 @@
484501 }
485502 
486503 static const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {};
504
+static const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops = {};
487505 static const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {};
488506 
489507 static const struct mv88e6xxx_avb_ops mv88e6165_avb_ops = {};
....@@ -509,6 +527,18 @@
509527 	return -EOPNOTSUPP;
510528 }
511529 
530
+static inline int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip,
531
+					     u16 kind, u16 bin)
532
+{
533
+	return -EOPNOTSUPP;
534
+}
535
+
536
+static inline int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip,
537
+					     u16 *stats)
538
+{
539
+	return -EOPNOTSUPP;
540
+}
541
+
512542 #endif /* CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */
513543 
514544 #endif /* _MV88E6XXX_GLOBAL2_H */