rtl88x2CE_WiFi_linux add concurrent mode

hc

2024-09-20 cf4ce59b3b70238352c7f1729f0f7223214828ad

 kernel/drivers/net/dsa/mv88e6xxx/global1.h
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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 /*
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  * Marvell 88E6xxx Switch Global (1) Registers support
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  *
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@@ -5,11 +6,6 @@
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  *
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  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
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  *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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  */
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 #ifndef _MV88E6XXX_GLOBAL1_H
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@@ -113,6 +109,7 @@
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 /* Offset 0x0A: ATU Control Register */
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 #define MV88E6XXX_G1_ATU_CTL		0x0a
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 #define MV88E6XXX_G1_ATU_CTL_LEARN2ALL	0x0008
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+#define MV88E6161_G1_ATU_CTL_HASH_MASK	0x0003
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 /* Offset 0x0B: ATU Operation Register */
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 #define MV88E6XXX_G1_ATU_OP				0x0b
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 #define MV88E6XXX_G1_ATU_OP_FULL_VIOLATION		BIT(4)
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 /* Offset 0x0C: ATU Data Register */
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-#define MV88E6XXX_G1_ATU_DATA				0x0c
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-#define MV88E6XXX_G1_ATU_DATA_TRUNK			0x8000
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-#define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK		0x00f0
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-#define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK		0x3ff0
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-#define MV88E6XXX_G1_ATU_DATA_STATE_MASK		0x000f
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-#define MV88E6XXX_G1_ATU_DATA_STATE_UNUSED		0x0000
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-#define MV88E6XXX_G1_ATU_DATA_STATE_UC_MGMT		0x000d
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-#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC		0x000e
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-#define MV88E6XXX_G1_ATU_DATA_STATE_UC_PRIO_OVER	0x000f
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-#define MV88E6XXX_G1_ATU_DATA_STATE_MC_NONE_RATE	0x0005
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-#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC		0x0007
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-#define MV88E6XXX_G1_ATU_DATA_STATE_MC_MGMT		0x000e
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-#define MV88E6XXX_G1_ATU_DATA_STATE_MC_PRIO_OVER	0x000f
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+#define MV88E6XXX_G1_ATU_DATA					0x0c
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+#define MV88E6XXX_G1_ATU_DATA_TRUNK				0x8000
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+#define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK			0x00f0
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+#define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK			0x3ff0
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+#define MV88E6XXX_G1_ATU_DATA_STATE_MASK			0x000f
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+#define MV88E6XXX_G1_ATU_DATA_STATE_UC_UNUSED			0x0000
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+#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_1_OLDEST		0x0001
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+#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_2			0x0002
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+#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_3			0x0003
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+#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_4			0x0004
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+#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_5			0x0005
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+#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_6			0x0006
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+#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_7_NEWEST		0x0007
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+#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY		0x0008
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+#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY_PO		0x0009
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+#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL		0x000a
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+#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL_PO	0x000b
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+#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT		0x000c
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+#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT_PO	0x000d
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+#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC			0x000e
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+#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_PO		0x000f
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+#define MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED			0x0000
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+#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY		0x0004
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+#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL		0x0005
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+#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT		0x0006
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+#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC			0x0007
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+#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY_PO		0x000c
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+#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL_PO	0x000d
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+#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT_PO	0x000e
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+#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_PO		0x000f
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 /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
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  * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
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 #define MV88E6390_G1_MONITOR_MGMT_CTL				0x1a
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 #define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE			0x8000
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 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK			0x3f00
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-#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XLO	0x0000
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-#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XHI	0x0100
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-#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XLO	0x0200
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-#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XHI	0x0300
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+#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO	0x0000
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+#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI	0x0100
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+#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO	0x0200
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+#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI	0x0300
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 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST		0x2000
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 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST		0x2100
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 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST		0x3000
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@@ -254,17 +268,22 @@
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 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
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 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
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-int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask);
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+int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
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+			  bit, int val);
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+int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
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+			   u16 mask, u16 val);
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 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);
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 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip);
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 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip);
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+int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip);
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 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip);
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 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip);
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-int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip);
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+int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu);
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+
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 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
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 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
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 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
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 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
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 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val);
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 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip);
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-int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port);
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-int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port);
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+int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,
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+				 enum mv88e6xxx_egress_direction direction,
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+				 int port);
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+int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,
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+				 enum mv88e6xxx_egress_direction direction,
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+				 int port);
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 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
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 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
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 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
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 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip);
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+
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 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);
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+int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);
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 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port);
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 			    bool all);
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 int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip);
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 void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip);
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+int mv88e6165_g1_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash);
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+int mv88e6165_g1_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash);
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 int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
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 			     struct mv88e6xxx_vtu_entry *entry);
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 int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
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+			       struct mv88e6xxx_vtu_entry *entry);
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+int mv88e6250_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
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+			     struct mv88e6xxx_vtu_entry *entry);
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+int mv88e6250_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
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 			       struct mv88e6xxx_vtu_entry *entry);
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 int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
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 			     struct mv88e6xxx_vtu_entry *entry);
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 int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip);
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 int mv88e6xxx_g1_vtu_prob_irq_setup(struct mv88e6xxx_chip *chip);
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 void mv88e6xxx_g1_vtu_prob_irq_free(struct mv88e6xxx_chip *chip);
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+int mv88e6xxx_g1_atu_get_next(struct mv88e6xxx_chip *chip, u16 fid);
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 #endif /* _MV88E6XXX_GLOBAL1_H */