~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,3 +1,4 @@
	1	+// SPDX-License-Identifier: GPL-2.0-or-later
1	2	/*
2	3	* Marvell 88e6xxx Ethernet switch single-chip support
3	4	*
..	..	@@ -7,13 +8,9 @@
7	8	*
8	9	* Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9	10	* Vivien Didelot <vivien.didelot@savoirfairelinux.com>
10		- *
11		- * This program is free software; you can redistribute it and/or modify
12		- * it under the terms of the GNU General Public License as published by
13		- * the Free Software Foundation; either version 2 of the License, or
14		- * (at your option) any later version.
15	11	*/
16	12
	13	+#include <linux/bitfield.h>
17	14	#include <linux/delay.h>
18	15	#include <linux/etherdevice.h>
19	16	#include <linux/ethtool.h>
..	..	@@ -31,11 +28,11 @@
31	28	#include <linux/platform_data/mv88e6xxx.h>
32	29	#include <linux/netdevice.h>
33	30	#include <linux/gpio/consumer.h>
34		-#include <linux/phy.h>
35	31	#include <linux/phylink.h>
36	32	#include <net/dsa.h>
37	33
38	34	#include "chip.h"
	35	+#include "devlink.h"
39	36	#include "global1.h"
40	37	#include "global2.h"
41	38	#include "hwtstamp.h"
..	..	@@ -43,6 +40,7 @@
43	40	#include "port.h"
44	41	#include "ptp.h"
45	42	#include "serdes.h"
	43	+#include "smi.h"
46	44
47	45	static void assert_reg_lock(struct mv88e6xxx_chip *chip)
48	46	{
..	..	@@ -51,149 +49,6 @@
51	49	dump_stack();
52	50	}
53	51	}
54		-
55		-/* The switch ADDR[4:1] configuration pins define the chip SMI device address
56		- * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
57		- *
58		- * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
59		- * is the only device connected to the SMI master. In this mode it responds to
60		- * all 32 possible SMI addresses, and thus maps directly the internal devices.
61		- *
62		- * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
63		- * multiple devices to share the SMI interface. In this mode it responds to only
64		- * 2 registers, used to indirectly access the internal SMI devices.
65		- */
66		-
67		-static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
68		- int addr, int reg, u16 *val)
69		-{
70		- if (!chip->smi_ops)
71		- return -EOPNOTSUPP;
72		-
73		- return chip->smi_ops->read(chip, addr, reg, val);
74		-}
75		-
76		-static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
77		- int addr, int reg, u16 val)
78		-{
79		- if (!chip->smi_ops)
80		- return -EOPNOTSUPP;
81		-
82		- return chip->smi_ops->write(chip, addr, reg, val);
83		-}
84		-
85		-static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
86		- int addr, int reg, u16 *val)
87		-{
88		- int ret;
89		-
90		- ret = mdiobus_read_nested(chip->bus, addr, reg);
91		- if (ret < 0)
92		- return ret;
93		-
94		- *val = ret & 0xffff;
95		-
96		- return 0;
97		-}
98		-
99		-static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
100		- int addr, int reg, u16 val)
101		-{
102		- int ret;
103		-
104		- ret = mdiobus_write_nested(chip->bus, addr, reg, val);
105		- if (ret < 0)
106		- return ret;
107		-
108		- return 0;
109		-}
110		-
111		-static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
112		- .read = mv88e6xxx_smi_single_chip_read,
113		- .write = mv88e6xxx_smi_single_chip_write,
114		-};
115		-
116		-static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
117		-{
118		- int ret;
119		- int i;
120		-
121		- for (i = 0; i < 16; i++) {
122		- ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
123		- if (ret < 0)
124		- return ret;
125		-
126		- if ((ret & SMI_CMD_BUSY) == 0)
127		- return 0;
128		- }
129		-
130		- return -ETIMEDOUT;
131		-}
132		-
133		-static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
134		- int addr, int reg, u16 *val)
135		-{
136		- int ret;
137		-
138		- /* Wait for the bus to become free. */
139		- ret = mv88e6xxx_smi_multi_chip_wait(chip);
140		- if (ret < 0)
141		- return ret;
142		-
143		- /* Transmit the read command. */
144		- ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
145		- SMI_CMD_OP_22_READ \| (addr << 5) \| reg);
146		- if (ret < 0)
147		- return ret;
148		-
149		- /* Wait for the read command to complete. */
150		- ret = mv88e6xxx_smi_multi_chip_wait(chip);
151		- if (ret < 0)
152		- return ret;
153		-
154		- /* Read the data. */
155		- ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
156		- if (ret < 0)
157		- return ret;
158		-
159		- *val = ret & 0xffff;
160		-
161		- return 0;
162		-}
163		-
164		-static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
165		- int addr, int reg, u16 val)
166		-{
167		- int ret;
168		-
169		- /* Wait for the bus to become free. */
170		- ret = mv88e6xxx_smi_multi_chip_wait(chip);
171		- if (ret < 0)
172		- return ret;
173		-
174		- /* Transmit the data to write. */
175		- ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
176		- if (ret < 0)
177		- return ret;
178		-
179		- /* Transmit the write command. */
180		- ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
181		- SMI_CMD_OP_22_WRITE \| (addr << 5) \| reg);
182		- if (ret < 0)
183		- return ret;
184		-
185		- /* Wait for the write command to complete. */
186		- ret = mv88e6xxx_smi_multi_chip_wait(chip);
187		- if (ret < 0)
188		- return ret;
189		-
190		- return 0;
191		-}
192		-
193		-static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
194		- .read = mv88e6xxx_smi_multi_chip_read,
195		- .write = mv88e6xxx_smi_multi_chip_write,
196		-};
197	52
198	53	int mv88e6xxx_read(struct mv88e6xxx_chip chip, int addr, int reg, u16 val)
199	54	{
..	..	@@ -225,6 +80,36 @@
225	80	addr, reg, val);
226	81
227	82	return 0;
	83	+}
	84	+
	85	+int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
	86	+ u16 mask, u16 val)
	87	+{
	88	+ u16 data;
	89	+ int err;
	90	+ int i;
	91	+
	92	+ /* There's no bus specific operation to wait for a mask */
	93	+ for (i = 0; i < 16; i++) {
	94	+ err = mv88e6xxx_read(chip, addr, reg, &data);
	95	+ if (err)
	96	+ return err;
	97	+
	98	+ if ((data & mask) == val)
	99	+ return 0;
	100	+
	101	+ usleep_range(1000, 2000);
	102	+ }
	103	+
	104	+ dev_err(chip->dev, "Timeout while waiting for switch\n");
	105	+ return -ETIMEDOUT;
	106	+}
	107	+
	108	+int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
	109	+ int bit, int val)
	110	+{
	111	+ return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
	112	+ val ? BIT(bit) : 0x0000);
228	113	}
229	114
230	115	struct mii_bus mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip chip)
..	..	@@ -264,9 +149,9 @@
264	149	u16 ctl1;
265	150	int err;
266	151
267		- mutex_lock(&chip->reg_lock);
	152	+ mv88e6xxx_reg_lock(chip);
268	153	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
269		- mutex_unlock(&chip->reg_lock);
	154	+ mv88e6xxx_reg_unlock(chip);
270	155
271	156	if (err)
272	157	goto out;
..	..	@@ -281,13 +166,13 @@
281	166	}
282	167	}
283	168
284		- mutex_lock(&chip->reg_lock);
	169	+ mv88e6xxx_reg_lock(chip);
285	170	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
286	171	if (err)
287	172	goto unlock;
288	173	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
289	174	unlock:
290		- mutex_unlock(&chip->reg_lock);
	175	+ mv88e6xxx_reg_unlock(chip);
291	176	if (err)
292	177	goto out;
293	178	ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
..	..	@@ -308,7 +193,7 @@
308	193	{
309	194	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
310	195
311		- mutex_lock(&chip->reg_lock);
	196	+ mv88e6xxx_reg_lock(chip);
312	197	}
313	198
314	199	static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
..	..	@@ -330,7 +215,7 @@
330	215	goto out;
331	216
332	217	out:
333		- mutex_unlock(&chip->reg_lock);
	218	+ mv88e6xxx_reg_unlock(chip);
334	219	}
335	220
336	221	static const struct irq_chip mv88e6xxx_g1_irq_chip = {
..	..	@@ -385,9 +270,9 @@
385	270	*/
386	271	free_irq(chip->irq, chip);
387	272
388		- mutex_lock(&chip->reg_lock);
	273	+ mv88e6xxx_reg_lock(chip);
389	274	mv88e6xxx_g1_irq_free_common(chip);
390		- mutex_unlock(&chip->reg_lock);
	275	+ mv88e6xxx_reg_unlock(chip);
391	276	}
392	277
393	278	static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
..	..	@@ -456,12 +341,15 @@
456	341	*/
457	342	irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
458	343
459		- mutex_unlock(&chip->reg_lock);
	344	+ snprintf(chip->irq_name, sizeof(chip->irq_name),
	345	+ "mv88e6xxx-%s", dev_name(chip->dev));
	346	+
	347	+ mv88e6xxx_reg_unlock(chip);
460	348	err = request_threaded_irq(chip->irq, NULL,
461	349	mv88e6xxx_g1_irq_thread_fn,
462		- IRQF_ONESHOT,
463		- dev_name(chip->dev), chip);
464		- mutex_lock(&chip->reg_lock);
	350	+ IRQF_ONESHOT \| IRQF_SHARED,
	351	+ chip->irq_name, chip);
	352	+ mv88e6xxx_reg_lock(chip);
465	353	if (err)
466	354	mv88e6xxx_g1_irq_free_common(chip);
467	355
..	..	@@ -490,7 +378,7 @@
490	378	kthread_init_delayed_work(&chip->irq_poll_work,
491	379	mv88e6xxx_irq_poll);
492	380
493		- chip->kworker = kthread_create_worker(0, dev_name(chip->dev));
	381	+ chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
494	382	if (IS_ERR(chip->kworker))
495	383	return PTR_ERR(chip->kworker);
496	384
..	..	@@ -505,48 +393,31 @@
505	393	kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
506	394	kthread_destroy_worker(chip->kworker);
507	395
508		- mutex_lock(&chip->reg_lock);
	396	+ mv88e6xxx_reg_lock(chip);
509	397	mv88e6xxx_g1_irq_free_common(chip);
510		- mutex_unlock(&chip->reg_lock);
	398	+ mv88e6xxx_reg_unlock(chip);
511	399	}
512	400
513		-int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
	401	+static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
	402	+ int port, phy_interface_t interface)
514	403	{
515		- int i;
516		-
517		- for (i = 0; i < 16; i++) {
518		- u16 val;
519		- int err;
520		-
521		- err = mv88e6xxx_read(chip, addr, reg, &val);
522		- if (err)
523		- return err;
524		-
525		- if (!(val & mask))
526		- return 0;
527		-
528		- usleep_range(1000, 2000);
529		- }
530		-
531		- dev_err(chip->dev, "Timeout while waiting for switch\n");
532		- return -ETIMEDOUT;
533		-}
534		-
535		-/* Indirect write to single pointer-data register with an Update bit */
536		-int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
537		-{
538		- u16 val;
539	404	int err;
540	405
541		- /* Wait until the previous operation is completed */
542		- err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
543		- if (err)
544		- return err;
	406	+ if (chip->info->ops->port_set_rgmii_delay) {
	407	+ err = chip->info->ops->port_set_rgmii_delay(chip, port,
	408	+ interface);
	409	+ if (err && err != -EOPNOTSUPP)
	410	+ return err;
	411	+ }
545	412
546		- /* Set the Update bit to trigger a write operation */
547		- val = BIT(15) \| update;
	413	+ if (chip->info->ops->port_set_cmode) {
	414	+ err = chip->info->ops->port_set_cmode(chip, port,
	415	+ interface);
	416	+ if (err && err != -EOPNOTSUPP)
	417	+ return err;
	418	+ }
548	419
549		- return mv88e6xxx_write(chip, addr, reg, val);
	420	+ return 0;
550	421	}
551	422
552	423	static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
..	..	@@ -559,15 +430,19 @@
559	430	return 0;
560	431
561	432	/* Port's MAC control must not be changed unless the link is down */
562		- err = chip->info->ops->port_set_link(chip, port, 0);
	433	+ err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
563	434	if (err)
564	435	return err;
565	436
566		- if (chip->info->ops->port_set_speed) {
567		- err = chip->info->ops->port_set_speed(chip, port, speed);
	437	+ if (chip->info->ops->port_set_speed_duplex) {
	438	+ err = chip->info->ops->port_set_speed_duplex(chip, port,
	439	+ speed, duplex);
568	440	if (err && err != -EOPNOTSUPP)
569	441	goto restore_link;
570	442	}
	443	+
	444	+ if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
	445	+ mode = chip->info->ops->port_max_speed_mode(port);
571	446
572	447	if (chip->info->ops->port_set_pause) {
573	448	err = chip->info->ops->port_set_pause(chip, port, pause);
..	..	@@ -575,25 +450,7 @@
575	450	goto restore_link;
576	451	}
577	452
578		- if (chip->info->ops->port_set_duplex) {
579		- err = chip->info->ops->port_set_duplex(chip, port, duplex);
580		- if (err && err != -EOPNOTSUPP)
581		- goto restore_link;
582		- }
583		-
584		- if (chip->info->ops->port_set_rgmii_delay) {
585		- err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
586		- if (err && err != -EOPNOTSUPP)
587		- goto restore_link;
588		- }
589		-
590		- if (chip->info->ops->port_set_cmode) {
591		- err = chip->info->ops->port_set_cmode(chip, port, mode);
592		- if (err && err != -EOPNOTSUPP)
593		- goto restore_link;
594		- }
595		-
596		- err = 0;
	453	+ err = mv88e6xxx_port_config_interface(chip, port, mode);
597	454	restore_link:
598	455	if (chip->info->ops->port_set_link(chip, port, link))
599	456	dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
..	..	@@ -601,27 +458,102 @@
601	458	return err;
602	459	}
603	460
604		-/* We expect the switch to perform auto negotiation if there is a real
605		- * phy. However, in the case of a fixed link phy, we force the port
606		- * settings from the fixed link settings.
607		- */
608		-static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
609		- struct phy_device *phydev)
	461	+static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
610	462	{
611	463	struct mv88e6xxx_chip *chip = ds->priv;
	464	+
	465	+ return port < chip->info->num_internal_phys;
	466	+}
	467	+
	468	+static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
	469	+{
	470	+ u16 reg;
612	471	int err;
613	472
614		- if (!phy_is_pseudo_fixed_link(phydev))
615		- return;
	473	+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
	474	+ if (err) {
	475	+ dev_err(chip->dev,
	476	+ "p%d: %s: failed to read port status\n",
	477	+ port, __func__);
	478	+ return err;
	479	+ }
616	480
617		- mutex_lock(&chip->reg_lock);
618		- err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
619		- phydev->duplex, phydev->pause,
620		- phydev->interface);
621		- mutex_unlock(&chip->reg_lock);
	481	+ return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
	482	+}
622	483
623		- if (err && err != -EOPNOTSUPP)
624		- dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
	484	+static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
	485	+ struct phylink_link_state *state)
	486	+{
	487	+ struct mv88e6xxx_chip *chip = ds->priv;
	488	+ u8 lane;
	489	+ int err;
	490	+
	491	+ mv88e6xxx_reg_lock(chip);
	492	+ lane = mv88e6xxx_serdes_get_lane(chip, port);
	493	+ if (lane && chip->info->ops->serdes_pcs_get_state)
	494	+ err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
	495	+ state);
	496	+ else
	497	+ err = -EOPNOTSUPP;
	498	+ mv88e6xxx_reg_unlock(chip);
	499	+
	500	+ return err;
	501	+}
	502	+
	503	+static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
	504	+ unsigned int mode,
	505	+ phy_interface_t interface,
	506	+ const unsigned long *advertise)
	507	+{
	508	+ const struct mv88e6xxx_ops *ops = chip->info->ops;
	509	+ u8 lane;
	510	+
	511	+ if (ops->serdes_pcs_config) {
	512	+ lane = mv88e6xxx_serdes_get_lane(chip, port);
	513	+ if (lane)
	514	+ return ops->serdes_pcs_config(chip, port, lane, mode,
	515	+ interface, advertise);
	516	+ }
	517	+
	518	+ return 0;
	519	+}
	520	+
	521	+static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
	522	+{
	523	+ struct mv88e6xxx_chip *chip = ds->priv;
	524	+ const struct mv88e6xxx_ops *ops;
	525	+ int err = 0;
	526	+ u8 lane;
	527	+
	528	+ ops = chip->info->ops;
	529	+
	530	+ if (ops->serdes_pcs_an_restart) {
	531	+ mv88e6xxx_reg_lock(chip);
	532	+ lane = mv88e6xxx_serdes_get_lane(chip, port);
	533	+ if (lane)
	534	+ err = ops->serdes_pcs_an_restart(chip, port, lane);
	535	+ mv88e6xxx_reg_unlock(chip);
	536	+
	537	+ if (err)
	538	+ dev_err(ds->dev, "p%d: failed to restart AN\n", port);
	539	+ }
	540	+}
	541	+
	542	+static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
	543	+ unsigned int mode,
	544	+ int speed, int duplex)
	545	+{
	546	+ const struct mv88e6xxx_ops *ops = chip->info->ops;
	547	+ u8 lane;
	548	+
	549	+ if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
	550	+ lane = mv88e6xxx_serdes_get_lane(chip, port);
	551	+ if (lane)
	552	+ return ops->serdes_pcs_link_up(chip, port, lane,
	553	+ speed, duplex);
	554	+ }
	555	+
	556	+ return 0;
625	557	}
626	558
627	559	static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
..	..	@@ -650,6 +582,20 @@
650	582	mv88e6065_phylink_validate(chip, port, mask, state);
651	583	}
652	584
	585	+static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
	586	+ unsigned long *mask,
	587	+ struct phylink_link_state *state)
	588	+{
	589	+ if (port >= 5)
	590	+ phylink_set(mask, 2500baseX_Full);
	591	+
	592	+ /* No ethtool bits for 200Mbps */
	593	+ phylink_set(mask, 1000baseT_Full);
	594	+ phylink_set(mask, 1000baseX_Full);
	595	+
	596	+ mv88e6065_phylink_validate(chip, port, mask, state);
	597	+}
	598	+
653	599	static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
654	600	unsigned long *mask,
655	601	struct phylink_link_state *state)
..	..	@@ -665,8 +611,10 @@
665	611	unsigned long *mask,
666	612	struct phylink_link_state *state)
667	613	{
668		- if (port >= 9)
	614	+ if (port >= 9) {
669	615	phylink_set(mask, 2500baseX_Full);
	616	+ phylink_set(mask, 2500baseT_Full);
	617	+ }
670	618
671	619	/* No ethtool bits for 200Mbps */
672	620	phylink_set(mask, 1000baseT_Full);
..	..	@@ -712,79 +660,136 @@
712	660	phylink_helper_basex_speed(state);
713	661	}
714	662
715		-static int mv88e6xxx_link_state(struct dsa_switch *ds, int port,
716		- struct phylink_link_state *state)
717		-{
718		- struct mv88e6xxx_chip *chip = ds->priv;
719		- int err;
720		-
721		- mutex_lock(&chip->reg_lock);
722		- if (chip->info->ops->port_link_state)
723		- err = chip->info->ops->port_link_state(chip, port, state);
724		- else
725		- err = -EOPNOTSUPP;
726		- mutex_unlock(&chip->reg_lock);
727		-
728		- return err;
729		-}
730		-
731	663	static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
732	664	unsigned int mode,
733	665	const struct phylink_link_state *state)
734	666	{
735	667	struct mv88e6xxx_chip *chip = ds->priv;
736		- int speed, duplex, link, pause, err;
	668	+ struct mv88e6xxx_port *p;
	669	+ int err = 0;
737	670
738		- if (mode == MLO_AN_PHY)
739		- return;
	671	+ p = &chip->ports[port];
740	672
741		- if (mode == MLO_AN_FIXED) {
742		- link = LINK_FORCED_UP;
743		- speed = state->speed;
744		- duplex = state->duplex;
745		- } else {
746		- speed = SPEED_UNFORCED;
747		- duplex = DUPLEX_UNFORCED;
748		- link = LINK_UNFORCED;
	673	+ mv88e6xxx_reg_lock(chip);
	674	+
	675	+ if (mode != MLO_AN_PHY \|\| !mv88e6xxx_phy_is_internal(ds, port)) {
	676	+ /* In inband mode, the link may come up at any time while the
	677	+ * link is not forced down. Force the link down while we
	678	+ * reconfigure the interface mode.
	679	+ */
	680	+ if (mode == MLO_AN_INBAND &&
	681	+ p->interface != state->interface &&
	682	+ chip->info->ops->port_set_link)
	683	+ chip->info->ops->port_set_link(chip, port,
	684	+ LINK_FORCED_DOWN);
	685	+
	686	+ err = mv88e6xxx_port_config_interface(chip, port,
	687	+ state->interface);
	688	+ if (err && err != -EOPNOTSUPP)
	689	+ goto err_unlock;
	690	+
	691	+ err = mv88e6xxx_serdes_pcs_config(chip, port, mode,
	692	+ state->interface,
	693	+ state->advertising);
	694	+ /* FIXME: we should restart negotiation if something changed -
	695	+ * which is something we get if we convert to using phylinks
	696	+ * PCS operations.
	697	+ */
	698	+ if (err > 0)
	699	+ err = 0;
749	700	}
750		- pause = !!phylink_test(state->advertising, Pause);
751	701
752		- mutex_lock(&chip->reg_lock);
753		- err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause,
754		- state->interface);
755		- mutex_unlock(&chip->reg_lock);
	702	+ /* Undo the forced down state above after completing configuration
	703	+ * irrespective of its state on entry, which allows the link to come
	704	+ * up in the in-band case where there is no separate SERDES. Also
	705	+ * ensure that the link can come up if the PPU is in use and we are
	706	+ * in PHY mode (we treat the PPU as an effective in-band mechanism.)
	707	+ */
	708	+ if (chip->info->ops->port_set_link &&
	709	+ ((mode == MLO_AN_INBAND && p->interface != state->interface) \|\|
	710	+ (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
	711	+ chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
	712	+
	713	+ p->interface = state->interface;
	714	+
	715	+err_unlock:
	716	+ mv88e6xxx_reg_unlock(chip);
756	717
757	718	if (err && err != -EOPNOTSUPP)
758		- dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
759		-}
760		-
761		-static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link)
762		-{
763		- struct mv88e6xxx_chip *chip = ds->priv;
764		- int err;
765		-
766		- mutex_lock(&chip->reg_lock);
767		- err = chip->info->ops->port_set_link(chip, port, link);
768		- mutex_unlock(&chip->reg_lock);
769		-
770		- if (err)
771		- dev_err(chip->dev, "p%d: failed to force MAC link\n", port);
	719	+ dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
772	720	}
773	721
774	722	static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
775	723	unsigned int mode,
776	724	phy_interface_t interface)
777	725	{
778		- if (mode == MLO_AN_FIXED)
779		- mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN);
	726	+ struct mv88e6xxx_chip *chip = ds->priv;
	727	+ const struct mv88e6xxx_ops *ops;
	728	+ int err = 0;
	729	+
	730	+ ops = chip->info->ops;
	731	+
	732	+ mv88e6xxx_reg_lock(chip);
	733	+ /* Internal PHYs propagate their configuration directly to the MAC.
	734	+ * External PHYs depend on whether the PPU is enabled for this port.
	735	+ */
	736	+ if (((!mv88e6xxx_phy_is_internal(ds, port) &&
	737	+ !mv88e6xxx_port_ppu_updates(chip, port)) \|\|
	738	+ mode == MLO_AN_FIXED) && ops->port_set_link)
	739	+ err = ops->port_set_link(chip, port, LINK_FORCED_DOWN);
	740	+ mv88e6xxx_reg_unlock(chip);
	741	+
	742	+ if (err)
	743	+ dev_err(chip->dev,
	744	+ "p%d: failed to force MAC link down\n", port);
780	745	}
781	746
782	747	static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
783	748	unsigned int mode, phy_interface_t interface,
784		- struct phy_device *phydev)
	749	+ struct phy_device *phydev,
	750	+ int speed, int duplex,
	751	+ bool tx_pause, bool rx_pause)
785	752	{
786		- if (mode == MLO_AN_FIXED)
787		- mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP);
	753	+ struct mv88e6xxx_chip *chip = ds->priv;
	754	+ const struct mv88e6xxx_ops *ops;
	755	+ int err = 0;
	756	+
	757	+ ops = chip->info->ops;
	758	+
	759	+ mv88e6xxx_reg_lock(chip);
	760	+ /* Internal PHYs propagate their configuration directly to the MAC.
	761	+ * External PHYs depend on whether the PPU is enabled for this port.
	762	+ */
	763	+ if ((!mv88e6xxx_phy_is_internal(ds, port) &&
	764	+ !mv88e6xxx_port_ppu_updates(chip, port)) \|\|
	765	+ mode == MLO_AN_FIXED) {
	766	+ /* FIXME: for an automedia port, should we force the link
	767	+ * down here - what if the link comes up due to "other" media
	768	+ * while we're bringing the port up, how is the exclusivity
	769	+ * handled in the Marvell hardware? E.g. port 2 on 88E6390
	770	+ * shared between internal PHY and Serdes.
	771	+ */
	772	+ err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
	773	+ duplex);
	774	+ if (err)
	775	+ goto error;
	776	+
	777	+ if (ops->port_set_speed_duplex) {
	778	+ err = ops->port_set_speed_duplex(chip, port,
	779	+ speed, duplex);
	780	+ if (err && err != -EOPNOTSUPP)
	781	+ goto error;
	782	+ }
	783	+
	784	+ if (ops->port_set_link)
	785	+ err = ops->port_set_link(chip, port, LINK_FORCED_UP);
	786	+ }
	787	+error:
	788	+ mv88e6xxx_reg_unlock(chip);
	789	+
	790	+ if (err && err != -EOPNOTSUPP)
	791	+ dev_err(ds->dev,
	792	+ "p%d: failed to configure MAC link up\n", port);
788	793	}
789	794
790	795	static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
..	..	@@ -884,7 +889,7 @@
884	889	break;
885	890	case STATS_TYPE_BANK1:
886	891	reg = bank1_select;
887		- /* fall through */
	892	+ fallthrough;
888	893	case STATS_TYPE_BANK0:
889	894	reg \|= s->reg \| histogram;
890	895	mv88e6xxx_g1_stats_read(chip, reg, &low);
..	..	@@ -923,6 +928,12 @@
923	928	STATS_TYPE_BANK0 \| STATS_TYPE_PORT);
924	929	}
925	930
	931	+static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
	932	+ uint8_t *data)
	933	+{
	934	+ return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
	935	+}
	936	+
926	937	static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
927	938	uint8_t *data)
928	939	{
..	..	@@ -957,7 +968,7 @@
957	968	if (stringset != ETH_SS_STATS)
958	969	return;
959	970
960		- mutex_lock(&chip->reg_lock);
	971	+ mv88e6xxx_reg_lock(chip);
961	972
962	973	if (chip->info->ops->stats_get_strings)
963	974	count = chip->info->ops->stats_get_strings(chip, data);
..	..	@@ -970,7 +981,7 @@
970	981	data += count * ETH_GSTRING_LEN;
971	982	mv88e6xxx_atu_vtu_get_strings(data);
972	983
973		- mutex_unlock(&chip->reg_lock);
	984	+ mv88e6xxx_reg_unlock(chip);
974	985	}
975	986
976	987	static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
..	..	@@ -993,6 +1004,11 @@
993	1004	STATS_TYPE_PORT);
994	1005	}
995	1006
	1007	+static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
	1008	+{
	1009	+ return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
	1010	+}
	1011	+
996	1012	static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
997	1013	{
998	1014	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 \|
..	..	@@ -1008,7 +1024,7 @@
1008	1024	if (sset != ETH_SS_STATS)
1009	1025	return 0;
1010	1026
1011		- mutex_lock(&chip->reg_lock);
	1027	+ mv88e6xxx_reg_lock(chip);
1012	1028	if (chip->info->ops->stats_get_sset_count)
1013	1029	count = chip->info->ops->stats_get_sset_count(chip);
1014	1030	if (count < 0)
..	..	@@ -1025,7 +1041,7 @@
1025	1041	count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1026	1042
1027	1043	out:
1028		- mutex_unlock(&chip->reg_lock);
	1044	+ mv88e6xxx_reg_unlock(chip);
1029	1045
1030	1046	return count;
1031	1047	}
..	..	@@ -1040,11 +1056,11 @@
1040	1056	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1041	1057	stat = &mv88e6xxx_hw_stats[i];
1042	1058	if (stat->type & types) {
1043		- mutex_lock(&chip->reg_lock);
	1059	+ mv88e6xxx_reg_lock(chip);
1044	1060	data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1045	1061	bank1_select,
1046	1062	histogram);
1047		- mutex_unlock(&chip->reg_lock);
	1063	+ mv88e6xxx_reg_unlock(chip);
1048	1064
1049	1065	j++;
1050	1066	}
..	..	@@ -1057,6 +1073,13 @@
1057	1073	{
1058	1074	return mv88e6xxx_stats_get_stats(chip, port, data,
1059	1075	STATS_TYPE_BANK0 \| STATS_TYPE_PORT,
	1076	+ 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
	1077	+}
	1078	+
	1079	+static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
	1080	+ uint64_t *data)
	1081	+{
	1082	+ return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1060	1083	0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1061	1084	}
1062	1085
..	..	@@ -1096,14 +1119,14 @@
1096	1119	if (chip->info->ops->stats_get_stats)
1097	1120	count = chip->info->ops->stats_get_stats(chip, port, data);
1098	1121
1099		- mutex_lock(&chip->reg_lock);
	1122	+ mv88e6xxx_reg_lock(chip);
1100	1123	if (chip->info->ops->serdes_get_stats) {
1101	1124	data += count;
1102	1125	count = chip->info->ops->serdes_get_stats(chip, port, data);
1103	1126	}
1104	1127	data += count;
1105	1128	mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1106		- mutex_unlock(&chip->reg_lock);
	1129	+ mv88e6xxx_reg_unlock(chip);
1107	1130	}
1108	1131
1109	1132	static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
..	..	@@ -1112,10 +1135,10 @@
1112	1135	struct mv88e6xxx_chip *chip = ds->priv;
1113	1136	int ret;
1114	1137
1115		- mutex_lock(&chip->reg_lock);
	1138	+ mv88e6xxx_reg_lock(chip);
1116	1139
1117	1140	ret = mv88e6xxx_stats_snapshot(chip, port);
1118		- mutex_unlock(&chip->reg_lock);
	1141	+ mv88e6xxx_reg_unlock(chip);
1119	1142
1120	1143	if (ret < 0)
1121	1144	return;
..	..	@@ -1126,7 +1149,14 @@
1126	1149
1127	1150	static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1128	1151	{
1129		- return 32 * sizeof(u16);
	1152	+ struct mv88e6xxx_chip *chip = ds->priv;
	1153	+ int len;
	1154	+
	1155	+ len = 32 * sizeof(u16);
	1156	+ if (chip->info->ops->serdes_get_regs_len)
	1157	+ len += chip->info->ops->serdes_get_regs_len(chip, port);
	1158	+
	1159	+ return len;
1130	1160	}
1131	1161
1132	1162	static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
..	..	@@ -1138,11 +1168,11 @@
1138	1168	u16 *p = _p;
1139	1169	int i;
1140	1170
1141		- regs->version = 0;
	1171	+ regs->version = chip->info->prod_num;
1142	1172
1143	1173	memset(p, 0xff, 32 * sizeof(u16));
1144	1174
1145		- mutex_lock(&chip->reg_lock);
	1175	+ mv88e6xxx_reg_lock(chip);
1146	1176
1147	1177	for (i = 0; i < 32; i++) {
1148	1178
..	..	@@ -1151,7 +1181,10 @@
1151	1181	p[i] = reg;
1152	1182	}
1153	1183
1154		- mutex_unlock(&chip->reg_lock);
	1184	+ if (chip->info->ops->serdes_get_regs)
	1185	+ chip->info->ops->serdes_get_regs(chip, port, &p[i]);
	1186	+
	1187	+ mv88e6xxx_reg_unlock(chip);
1155	1188	}
1156	1189
1157	1190	static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
..	..	@@ -1168,35 +1201,43 @@
1168	1201	return 0;
1169	1202	}
1170	1203
	1204	+/* Mask of the local ports allowed to receive frames from a given fabric port */
1171	1205	static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1172	1206	{
1173		- struct dsa_switch *ds = NULL;
	1207	+ struct dsa_switch *ds = chip->ds;
	1208	+ struct dsa_switch_tree *dst = ds->dst;
1174	1209	struct net_device *br;
	1210	+ struct dsa_port *dp;
	1211	+ bool found = false;
1175	1212	u16 pvlan;
1176		- int i;
1177	1213
1178		- if (dev < DSA_MAX_SWITCHES)
1179		- ds = chip->ds->dst->ds[dev];
	1214	+ list_for_each_entry(dp, &dst->ports, list) {
	1215	+ if (dp->ds->index == dev && dp->index == port) {
	1216	+ found = true;
	1217	+ break;
	1218	+ }
	1219	+ }
1180	1220
1181	1221	/* Prevent frames from unknown switch or port */
1182		- if (!ds \|\| port >= ds->num_ports)
	1222	+ if (!found)
1183	1223	return 0;
1184	1224
1185	1225	/* Frames from DSA links and CPU ports can egress any local port */
1186		- if (dsa_is_cpu_port(ds, port) \|\| dsa_is_dsa_port(ds, port))
	1226	+ if (dp->type == DSA_PORT_TYPE_CPU \|\| dp->type == DSA_PORT_TYPE_DSA)
1187	1227	return mv88e6xxx_port_mask(chip);
1188	1228
1189		- br = ds->ports[port].bridge_dev;
	1229	+ br = dp->bridge_dev;
1190	1230	pvlan = 0;
1191	1231
1192	1232	/* Frames from user ports can egress any local DSA links and CPU ports,
1193	1233	* as well as any local member of their bridge group.
1194	1234	*/
1195		- for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1196		- if (dsa_is_cpu_port(chip->ds, i) \|\|
1197		- dsa_is_dsa_port(chip->ds, i) \|\|
1198		- (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
1199		- pvlan \|= BIT(i);
	1235	+ list_for_each_entry(dp, &dst->ports, list)
	1236	+ if (dp->ds == ds &&
	1237	+ (dp->type == DSA_PORT_TYPE_CPU \|\|
	1238	+ dp->type == DSA_PORT_TYPE_DSA \|\|
	1239	+ (br && dp->bridge_dev == br)))
	1240	+ pvlan \|= BIT(dp->index);
1200	1241
1201	1242	return pvlan;
1202	1243	}
..	..	@@ -1217,9 +1258,9 @@
1217	1258	struct mv88e6xxx_chip *chip = ds->priv;
1218	1259	int err;
1219	1260
1220		- mutex_lock(&chip->reg_lock);
	1261	+ mv88e6xxx_reg_lock(chip);
1221	1262	err = mv88e6xxx_port_set_state(chip, port, state);
1222		- mutex_unlock(&chip->reg_lock);
	1263	+ mv88e6xxx_reg_unlock(chip);
1223	1264
1224	1265	if (err)
1225	1266	dev_err(ds->dev, "p%d: failed to update state\n", port);
..	..	@@ -1246,6 +1287,7 @@
1246	1287
1247	1288	static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1248	1289	{
	1290	+ struct dsa_switch *ds = chip->ds;
1249	1291	int target, port;
1250	1292	int err;
1251	1293
..	..	@@ -1254,10 +1296,9 @@
1254	1296
1255	1297	/* Initialize the routing port to the 32 possible target devices */
1256	1298	for (target = 0; target < 32; target++) {
1257		- port = 0x1f;
1258		- if (target < DSA_MAX_SWITCHES)
1259		- if (chip->ds->rtable[target] != DSA_RTABLE_NONE)
1260		- port = chip->ds->rtable[target];
	1299	+ port = dsa_routing_port(ds, target);
	1300	+ if (port == ds->num_ports)
	1301	+ port = 0x1f;
1261	1302
1262	1303	err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1263	1304	if (err)
..	..	@@ -1364,7 +1405,7 @@
1364	1405	u16 pvlan = 0;
1365	1406
1366	1407	if (!mv88e6xxx_has_pvt(chip))
1367		- return -EOPNOTSUPP;
	1408	+ return 0;
1368	1409
1369	1410	/* Skip the local source device, which uses in-chip port VLAN */
1370	1411	if (dev != chip->ds->index)
..	..	@@ -1404,9 +1445,9 @@
1404	1445	struct mv88e6xxx_chip *chip = ds->priv;
1405	1446	int err;
1406	1447
1407		- mutex_lock(&chip->reg_lock);
	1448	+ mv88e6xxx_reg_lock(chip);
1408	1449	err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1409		- mutex_unlock(&chip->reg_lock);
	1450	+ mv88e6xxx_reg_unlock(chip);
1410	1451
1411	1452	if (err)
1412	1453	dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
..	..	@@ -1438,26 +1479,27 @@
1438	1479	return chip->info->ops->vtu_loadpurge(chip, entry);
1439	1480	}
1440	1481
1441		-static int mv88e6xxx_atu_new(struct mv88e6xxx_chip chip, u16 fid)
	1482	+int mv88e6xxx_fid_map(struct mv88e6xxx_chip chip, unsigned long fid_bitmap)
1442	1483	{
1443		- DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1444		- struct mv88e6xxx_vtu_entry vlan = {
1445		- .vid = chip->info->max_vid,
1446		- };
	1484	+ struct mv88e6xxx_vtu_entry vlan;
1447	1485	int i, err;
	1486	+ u16 fid;
1448	1487
1449	1488	bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1450	1489
1451	1490	/* Set every FID bit used by the (un)bridged ports */
1452	1491	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1453		- err = mv88e6xxx_port_get_fid(chip, i, fid);
	1492	+ err = mv88e6xxx_port_get_fid(chip, i, &fid);
1454	1493	if (err)
1455	1494	return err;
1456	1495
1457		- set_bit(*fid, fid_bitmap);
	1496	+ set_bit(fid, fid_bitmap);
1458	1497	}
1459	1498
1460	1499	/* Set every FID bit used by the VLAN entries */
	1500	+ vlan.vid = chip->info->max_vid;
	1501	+ vlan.valid = false;
	1502	+
1461	1503	do {
1462	1504	err = mv88e6xxx_vtu_getnext(chip, &vlan);
1463	1505	if (err)
..	..	@@ -1468,6 +1510,18 @@
1468	1510
1469	1511	set_bit(vlan.fid, fid_bitmap);
1470	1512	} while (vlan.vid < chip->info->max_vid);
	1513	+
	1514	+ return 0;
	1515	+}
	1516	+
	1517	+static int mv88e6xxx_atu_new(struct mv88e6xxx_chip chip, u16 fid)
	1518	+{
	1519	+ DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
	1520	+ int err;
	1521	+
	1522	+ err = mv88e6xxx_fid_map(chip, fid_bitmap);
	1523	+ if (err)
	1524	+ return err;
1471	1525
1472	1526	/* The reset value 0x000 is used to indicate that multiple address
1473	1527	* databases are not needed. Return the next positive available.
..	..	@@ -1480,51 +1534,11 @@
1480	1534	return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1481	1535	}
1482	1536
1483		-static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1484		- struct mv88e6xxx_vtu_entry *entry, bool new)
1485		-{
1486		- int err;
1487		-
1488		- if (!vid)
1489		- return -EOPNOTSUPP;
1490		-
1491		- entry->vid = vid - 1;
1492		- entry->valid = false;
1493		-
1494		- err = mv88e6xxx_vtu_getnext(chip, entry);
1495		- if (err)
1496		- return err;
1497		-
1498		- if (entry->vid == vid && entry->valid)
1499		- return 0;
1500		-
1501		- if (new) {
1502		- int i;
1503		-
1504		- /* Initialize a fresh VLAN entry */
1505		- memset(entry, 0, sizeof(*entry));
1506		- entry->valid = true;
1507		- entry->vid = vid;
1508		-
1509		- /* Exclude all ports */
1510		- for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1511		- entry->member[i] =
1512		- MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1513		-
1514		- return mv88e6xxx_atu_new(chip, &entry->fid);
1515		- }
1516		-
1517		- /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1518		- return -EOPNOTSUPP;
1519		-}
1520		-
1521	1537	static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1522	1538	u16 vid_begin, u16 vid_end)
1523	1539	{
1524	1540	struct mv88e6xxx_chip *chip = ds->priv;
1525		- struct mv88e6xxx_vtu_entry vlan = {
1526		- .vid = vid_begin - 1,
1527		- };
	1541	+ struct mv88e6xxx_vtu_entry vlan;
1528	1542	int i, err;
1529	1543
1530	1544	/* DSA and CPU ports have to be members of multiple vlans */
..	..	@@ -1534,12 +1548,13 @@
1534	1548	if (!vid_begin)
1535	1549	return -EOPNOTSUPP;
1536	1550
1537		- mutex_lock(&chip->reg_lock);
	1551	+ vlan.vid = vid_begin - 1;
	1552	+ vlan.valid = false;
1538	1553
1539	1554	do {
1540	1555	err = mv88e6xxx_vtu_getnext(chip, &vlan);
1541	1556	if (err)
1542		- goto unlock;
	1557	+ return err;
1543	1558
1544	1559	if (!vlan.valid)
1545	1560	break;
..	..	@@ -1551,7 +1566,7 @@
1551	1566	if (dsa_is_dsa_port(ds, i) \|\| dsa_is_cpu_port(ds, i))
1552	1567	continue;
1553	1568
1554		- if (!ds->ports[i].slave)
	1569	+ if (!dsa_to_port(ds, i)->slave)
1555	1570	continue;
1556	1571
1557	1572	if (vlan.member[i] ==
..	..	@@ -1559,7 +1574,7 @@
1559	1574	continue;
1560	1575
1561	1576	if (dsa_to_port(ds, i)->bridge_dev ==
1562		- ds->ports[port].bridge_dev)
	1577	+ dsa_to_port(ds, port)->bridge_dev)
1563	1578	break; /* same bridge, check next VLAN */
1564	1579
1565	1580	if (!dsa_to_port(ds, i)->bridge_dev)
..	..	@@ -1568,31 +1583,28 @@
1568	1583	dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1569	1584	port, vlan.vid, i,
1570	1585	netdev_name(dsa_to_port(ds, i)->bridge_dev));
1571		- err = -EOPNOTSUPP;
1572		- goto unlock;
	1586	+ return -EOPNOTSUPP;
1573	1587	}
1574	1588	} while (vlan.vid < vid_end);
1575	1589
1576		-unlock:
1577		- mutex_unlock(&chip->reg_lock);
1578		-
1579		- return err;
	1590	+ return 0;
1580	1591	}
1581	1592
1582	1593	static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1583		- bool vlan_filtering)
	1594	+ bool vlan_filtering,
	1595	+ struct switchdev_trans *trans)
1584	1596	{
1585	1597	struct mv88e6xxx_chip *chip = ds->priv;
1586	1598	u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1587	1599	MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1588	1600	int err;
1589	1601
1590		- if (!chip->info->max_vid)
1591		- return -EOPNOTSUPP;
	1602	+ if (switchdev_trans_ph_prepare(trans))
	1603	+ return chip->info->max_vid ? 0 : -EOPNOTSUPP;
1592	1604
1593		- mutex_lock(&chip->reg_lock);
	1605	+ mv88e6xxx_reg_lock(chip);
1594	1606	err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1595		- mutex_unlock(&chip->reg_lock);
	1607	+ mv88e6xxx_reg_unlock(chip);
1596	1608
1597	1609	return err;
1598	1610	}
..	..	@@ -1610,53 +1622,65 @@
1610	1622	/* If the requested port doesn't belong to the same bridge as the VLAN
1611	1623	* members, do not support it (yet) and fallback to software VLAN.
1612	1624	*/
	1625	+ mv88e6xxx_reg_lock(chip);
1613	1626	err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1614	1627	vlan->vid_end);
1615		- if (err)
1616		- return err;
	1628	+ mv88e6xxx_reg_unlock(chip);
1617	1629
1618	1630	/* We don't need any dynamic resource from the kernel (yet),
1619	1631	* so skip the prepare phase.
1620	1632	*/
1621		- return 0;
	1633	+ return err;
1622	1634	}
1623	1635
1624	1636	static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1625	1637	const unsigned char *addr, u16 vid,
1626	1638	u8 state)
1627	1639	{
1628		- struct mv88e6xxx_vtu_entry vlan;
1629	1640	struct mv88e6xxx_atu_entry entry;
	1641	+ struct mv88e6xxx_vtu_entry vlan;
	1642	+ u16 fid;
1630	1643	int err;
1631	1644
1632	1645	/* Null VLAN ID corresponds to the port private database */
1633		- if (vid == 0)
1634		- err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1635		- else
1636		- err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1637		- if (err)
1638		- return err;
	1646	+ if (vid == 0) {
	1647	+ err = mv88e6xxx_port_get_fid(chip, port, &fid);
	1648	+ if (err)
	1649	+ return err;
	1650	+ } else {
	1651	+ vlan.vid = vid - 1;
	1652	+ vlan.valid = false;
1639	1653
1640		- entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	1654	+ err = mv88e6xxx_vtu_getnext(chip, &vlan);
	1655	+ if (err)
	1656	+ return err;
	1657	+
	1658	+ /* switchdev expects -EOPNOTSUPP to honor software VLANs */
	1659	+ if (vlan.vid != vid \|\| !vlan.valid)
	1660	+ return -EOPNOTSUPP;
	1661	+
	1662	+ fid = vlan.fid;
	1663	+ }
	1664	+
	1665	+ entry.state = 0;
1641	1666	ether_addr_copy(entry.mac, addr);
1642	1667	eth_addr_dec(entry.mac);
1643	1668
1644		- err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
	1669	+ err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
1645	1670	if (err)
1646	1671	return err;
1647	1672
1648	1673	/* Initialize a fresh ATU entry if it isn't found */
1649		- if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED \|\|
1650		- !ether_addr_equal(entry.mac, addr)) {
	1674	+ if (!entry.state \|\| !ether_addr_equal(entry.mac, addr)) {
1651	1675	memset(&entry, 0, sizeof(entry));
1652	1676	ether_addr_copy(entry.mac, addr);
1653	1677	}
1654	1678
1655	1679	/* Purge the ATU entry only if no port is using it anymore */
1656		- if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
	1680	+ if (!state) {
1657	1681	entry.portvec &= ~BIT(port);
1658	1682	if (!entry.portvec)
1659		- entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	1683	+ entry.state = 0;
1660	1684	} else {
1661	1685	if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1662	1686	entry.portvec = BIT(port);
..	..	@@ -1666,7 +1690,217 @@
1666	1690	entry.state = state;
1667	1691	}
1668	1692
1669		- return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
	1693	+ return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
	1694	+}
	1695	+
	1696	+static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
	1697	+ const struct mv88e6xxx_policy *policy)
	1698	+{
	1699	+ enum mv88e6xxx_policy_mapping mapping = policy->mapping;
	1700	+ enum mv88e6xxx_policy_action action = policy->action;
	1701	+ const u8 *addr = policy->addr;
	1702	+ u16 vid = policy->vid;
	1703	+ u8 state;
	1704	+ int err;
	1705	+ int id;
	1706	+
	1707	+ if (!chip->info->ops->port_set_policy)
	1708	+ return -EOPNOTSUPP;
	1709	+
	1710	+ switch (mapping) {
	1711	+ case MV88E6XXX_POLICY_MAPPING_DA:
	1712	+ case MV88E6XXX_POLICY_MAPPING_SA:
	1713	+ if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
	1714	+ state = 0; /* Dissociate the port and address */
	1715	+ else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
	1716	+ is_multicast_ether_addr(addr))
	1717	+ state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
	1718	+ else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
	1719	+ is_unicast_ether_addr(addr))
	1720	+ state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
	1721	+ else
	1722	+ return -EOPNOTSUPP;
	1723	+
	1724	+ err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
	1725	+ state);
	1726	+ if (err)
	1727	+ return err;
	1728	+ break;
	1729	+ default:
	1730	+ return -EOPNOTSUPP;
	1731	+ }
	1732	+
	1733	+ /* Skip the port's policy clearing if the mapping is still in use */
	1734	+ if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
	1735	+ idr_for_each_entry(&chip->policies, policy, id)
	1736	+ if (policy->port == port &&
	1737	+ policy->mapping == mapping &&
	1738	+ policy->action != action)
	1739	+ return 0;
	1740	+
	1741	+ return chip->info->ops->port_set_policy(chip, port, mapping, action);
	1742	+}
	1743	+
	1744	+static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
	1745	+ struct ethtool_rx_flow_spec *fs)
	1746	+{
	1747	+ struct ethhdr *mac_entry = &fs->h_u.ether_spec;
	1748	+ struct ethhdr *mac_mask = &fs->m_u.ether_spec;
	1749	+ enum mv88e6xxx_policy_mapping mapping;
	1750	+ enum mv88e6xxx_policy_action action;
	1751	+ struct mv88e6xxx_policy *policy;
	1752	+ u16 vid = 0;
	1753	+ u8 *addr;
	1754	+ int err;
	1755	+ int id;
	1756	+
	1757	+ if (fs->location != RX_CLS_LOC_ANY)
	1758	+ return -EINVAL;
	1759	+
	1760	+ if (fs->ring_cookie == RX_CLS_FLOW_DISC)
	1761	+ action = MV88E6XXX_POLICY_ACTION_DISCARD;
	1762	+ else
	1763	+ return -EOPNOTSUPP;
	1764	+
	1765	+ switch (fs->flow_type & ~FLOW_EXT) {
	1766	+ case ETHER_FLOW:
	1767	+ if (!is_zero_ether_addr(mac_mask->h_dest) &&
	1768	+ is_zero_ether_addr(mac_mask->h_source)) {
	1769	+ mapping = MV88E6XXX_POLICY_MAPPING_DA;
	1770	+ addr = mac_entry->h_dest;
	1771	+ } else if (is_zero_ether_addr(mac_mask->h_dest) &&
	1772	+ !is_zero_ether_addr(mac_mask->h_source)) {
	1773	+ mapping = MV88E6XXX_POLICY_MAPPING_SA;
	1774	+ addr = mac_entry->h_source;
	1775	+ } else {
	1776	+ /* Cannot support DA and SA mapping in the same rule */
	1777	+ return -EOPNOTSUPP;
	1778	+ }
	1779	+ break;
	1780	+ default:
	1781	+ return -EOPNOTSUPP;
	1782	+ }
	1783	+
	1784	+ if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
	1785	+ if (fs->m_ext.vlan_tci != htons(0xffff))
	1786	+ return -EOPNOTSUPP;
	1787	+ vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
	1788	+ }
	1789	+
	1790	+ idr_for_each_entry(&chip->policies, policy, id) {
	1791	+ if (policy->port == port && policy->mapping == mapping &&
	1792	+ policy->action == action && policy->vid == vid &&
	1793	+ ether_addr_equal(policy->addr, addr))
	1794	+ return -EEXIST;
	1795	+ }
	1796	+
	1797	+ policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
	1798	+ if (!policy)
	1799	+ return -ENOMEM;
	1800	+
	1801	+ fs->location = 0;
	1802	+ err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
	1803	+ GFP_KERNEL);
	1804	+ if (err) {
	1805	+ devm_kfree(chip->dev, policy);
	1806	+ return err;
	1807	+ }
	1808	+
	1809	+ memcpy(&policy->fs, fs, sizeof(*fs));
	1810	+ ether_addr_copy(policy->addr, addr);
	1811	+ policy->mapping = mapping;
	1812	+ policy->action = action;
	1813	+ policy->port = port;
	1814	+ policy->vid = vid;
	1815	+
	1816	+ err = mv88e6xxx_policy_apply(chip, port, policy);
	1817	+ if (err) {
	1818	+ idr_remove(&chip->policies, fs->location);
	1819	+ devm_kfree(chip->dev, policy);
	1820	+ return err;
	1821	+ }
	1822	+
	1823	+ return 0;
	1824	+}
	1825	+
	1826	+static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
	1827	+ struct ethtool_rxnfc rxnfc, u32 rule_locs)
	1828	+{
	1829	+ struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
	1830	+ struct mv88e6xxx_chip *chip = ds->priv;
	1831	+ struct mv88e6xxx_policy *policy;
	1832	+ int err;
	1833	+ int id;
	1834	+
	1835	+ mv88e6xxx_reg_lock(chip);
	1836	+
	1837	+ switch (rxnfc->cmd) {
	1838	+ case ETHTOOL_GRXCLSRLCNT:
	1839	+ rxnfc->data = 0;
	1840	+ rxnfc->data \|= RX_CLS_LOC_SPECIAL;
	1841	+ rxnfc->rule_cnt = 0;
	1842	+ idr_for_each_entry(&chip->policies, policy, id)
	1843	+ if (policy->port == port)
	1844	+ rxnfc->rule_cnt++;
	1845	+ err = 0;
	1846	+ break;
	1847	+ case ETHTOOL_GRXCLSRULE:
	1848	+ err = -ENOENT;
	1849	+ policy = idr_find(&chip->policies, fs->location);
	1850	+ if (policy) {
	1851	+ memcpy(fs, &policy->fs, sizeof(*fs));
	1852	+ err = 0;
	1853	+ }
	1854	+ break;
	1855	+ case ETHTOOL_GRXCLSRLALL:
	1856	+ rxnfc->data = 0;
	1857	+ rxnfc->rule_cnt = 0;
	1858	+ idr_for_each_entry(&chip->policies, policy, id)
	1859	+ if (policy->port == port)
	1860	+ rule_locs[rxnfc->rule_cnt++] = id;
	1861	+ err = 0;
	1862	+ break;
	1863	+ default:
	1864	+ err = -EOPNOTSUPP;
	1865	+ break;
	1866	+ }
	1867	+
	1868	+ mv88e6xxx_reg_unlock(chip);
	1869	+
	1870	+ return err;
	1871	+}
	1872	+
	1873	+static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
	1874	+ struct ethtool_rxnfc *rxnfc)
	1875	+{
	1876	+ struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
	1877	+ struct mv88e6xxx_chip *chip = ds->priv;
	1878	+ struct mv88e6xxx_policy *policy;
	1879	+ int err;
	1880	+
	1881	+ mv88e6xxx_reg_lock(chip);
	1882	+
	1883	+ switch (rxnfc->cmd) {
	1884	+ case ETHTOOL_SRXCLSRLINS:
	1885	+ err = mv88e6xxx_policy_insert(chip, port, fs);
	1886	+ break;
	1887	+ case ETHTOOL_SRXCLSRLDEL:
	1888	+ err = -ENOENT;
	1889	+ policy = idr_remove(&chip->policies, fs->location);
	1890	+ if (policy) {
	1891	+ policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
	1892	+ err = mv88e6xxx_policy_apply(chip, port, policy);
	1893	+ devm_kfree(chip->dev, policy);
	1894	+ }
	1895	+ break;
	1896	+ default:
	1897	+ err = -EOPNOTSUPP;
	1898	+ break;
	1899	+ }
	1900	+
	1901	+ mv88e6xxx_reg_unlock(chip);
	1902	+
	1903	+ return err;
1670	1904	}
1671	1905
1672	1906	static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
..	..	@@ -1692,23 +1926,58 @@
1692	1926	return 0;
1693	1927	}
1694	1928
1695		-static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1696		- u16 vid, u8 member)
	1929	+static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
	1930	+ u16 vid, u8 member, bool warn)
1697	1931	{
	1932	+ const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1698	1933	struct mv88e6xxx_vtu_entry vlan;
1699		- int err;
	1934	+ int i, err;
1700	1935
1701		- err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
	1936	+ if (!vid)
	1937	+ return -EOPNOTSUPP;
	1938	+
	1939	+ vlan.vid = vid - 1;
	1940	+ vlan.valid = false;
	1941	+
	1942	+ err = mv88e6xxx_vtu_getnext(chip, &vlan);
1702	1943	if (err)
1703	1944	return err;
1704	1945
1705		- vlan.member[port] = member;
	1946	+ if (vlan.vid != vid \|\| !vlan.valid) {
	1947	+ memset(&vlan, 0, sizeof(vlan));
1706	1948
1707		- err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1708		- if (err)
1709		- return err;
	1949	+ err = mv88e6xxx_atu_new(chip, &vlan.fid);
	1950	+ if (err)
	1951	+ return err;
1710	1952
1711		- return mv88e6xxx_broadcast_setup(chip, vid);
	1953	+ for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
	1954	+ if (i == port)
	1955	+ vlan.member[i] = member;
	1956	+ else
	1957	+ vlan.member[i] = non_member;
	1958	+
	1959	+ vlan.vid = vid;
	1960	+ vlan.valid = true;
	1961	+
	1962	+ err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
	1963	+ if (err)
	1964	+ return err;
	1965	+
	1966	+ err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
	1967	+ if (err)
	1968	+ return err;
	1969	+ } else if (vlan.member[port] != member) {
	1970	+ vlan.member[port] = member;
	1971	+
	1972	+ err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
	1973	+ if (err)
	1974	+ return err;
	1975	+ } else if (warn) {
	1976	+ dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
	1977	+ port, vid);
	1978	+ }
	1979	+
	1980	+ return 0;
1712	1981	}
1713	1982
1714	1983	static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
..	..	@@ -1717,6 +1986,7 @@
1717	1986	struct mv88e6xxx_chip *chip = ds->priv;
1718	1987	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1719	1988	bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
	1989	+ bool warn;
1720	1990	u8 member;
1721	1991	u16 vid;
1722	1992
..	..	@@ -1730,10 +2000,15 @@
1730	2000	else
1731	2001	member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1732	2002
1733		- mutex_lock(&chip->reg_lock);
	2003	+ /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
	2004	+ * and then the CPU port. Do not warn for duplicates for the CPU port.
	2005	+ */
	2006	+ warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
	2007	+
	2008	+ mv88e6xxx_reg_lock(chip);
1734	2009
1735	2010	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1736		- if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
	2011	+ if (mv88e6xxx_port_vlan_join(chip, port, vid, member, warn))
1737	2012	dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1738	2013	vid, untagged ? 'u' : 't');
1739	2014
..	..	@@ -1741,21 +2016,30 @@
1741	2016	dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1742	2017	vlan->vid_end);
1743	2018
1744		- mutex_unlock(&chip->reg_lock);
	2019	+ mv88e6xxx_reg_unlock(chip);
1745	2020	}
1746	2021
1747		-static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1748		- int port, u16 vid)
	2022	+static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
	2023	+ int port, u16 vid)
1749	2024	{
1750	2025	struct mv88e6xxx_vtu_entry vlan;
1751	2026	int i, err;
1752	2027
1753		- err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
	2028	+ if (!vid)
	2029	+ return -EOPNOTSUPP;
	2030	+
	2031	+ vlan.vid = vid - 1;
	2032	+ vlan.valid = false;
	2033	+
	2034	+ err = mv88e6xxx_vtu_getnext(chip, &vlan);
1754	2035	if (err)
1755	2036	return err;
1756	2037
1757		- /* Tell switchdev if this VLAN is handled in software */
1758		- if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
	2038	+ /* If the VLAN doesn't exist in hardware or the port isn't a member,
	2039	+ * tell switchdev that this VLAN is likely handled in software.
	2040	+ */
	2041	+ if (vlan.vid != vid \|\| !vlan.valid \|\|
	2042	+ vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1759	2043	return -EOPNOTSUPP;
1760	2044
1761	2045	vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
..	..	@@ -1787,14 +2071,14 @@
1787	2071	if (!chip->info->max_vid)
1788	2072	return -EOPNOTSUPP;
1789	2073
1790		- mutex_lock(&chip->reg_lock);
	2074	+ mv88e6xxx_reg_lock(chip);
1791	2075
1792	2076	err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1793	2077	if (err)
1794	2078	goto unlock;
1795	2079
1796	2080	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1797		- err = _mv88e6xxx_port_vlan_del(chip, port, vid);
	2081	+ err = mv88e6xxx_port_vlan_leave(chip, port, vid);
1798	2082	if (err)
1799	2083	goto unlock;
1800	2084
..	..	@@ -1806,7 +2090,7 @@
1806	2090	}
1807	2091
1808	2092	unlock:
1809		- mutex_unlock(&chip->reg_lock);
	2093	+ mv88e6xxx_reg_unlock(chip);
1810	2094
1811	2095	return err;
1812	2096	}
..	..	@@ -1817,10 +2101,10 @@
1817	2101	struct mv88e6xxx_chip *chip = ds->priv;
1818	2102	int err;
1819	2103
1820		- mutex_lock(&chip->reg_lock);
	2104	+ mv88e6xxx_reg_lock(chip);
1821	2105	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1822	2106	MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1823		- mutex_unlock(&chip->reg_lock);
	2107	+ mv88e6xxx_reg_unlock(chip);
1824	2108
1825	2109	return err;
1826	2110	}
..	..	@@ -1831,10 +2115,9 @@
1831	2115	struct mv88e6xxx_chip *chip = ds->priv;
1832	2116	int err;
1833	2117
1834		- mutex_lock(&chip->reg_lock);
1835		- err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1836		- MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1837		- mutex_unlock(&chip->reg_lock);
	2118	+ mv88e6xxx_reg_lock(chip);
	2119	+ err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
	2120	+ mv88e6xxx_reg_unlock(chip);
1838	2121
1839	2122	return err;
1840	2123	}
..	..	@@ -1847,17 +2130,15 @@
1847	2130	bool is_static;
1848	2131	int err;
1849	2132
1850		- addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	2133	+ addr.state = 0;
1851	2134	eth_broadcast_addr(addr.mac);
1852	2135
1853	2136	do {
1854		- mutex_lock(&chip->reg_lock);
1855	2137	err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1856		- mutex_unlock(&chip->reg_lock);
1857	2138	if (err)
1858	2139	return err;
1859	2140
1860		- if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
	2141	+ if (!addr.state)
1861	2142	break;
1862	2143
1863	2144	if (addr.trunk \|\| (addr.portvec & BIT(port)) == 0)
..	..	@@ -1879,17 +2160,12 @@
1879	2160	static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1880	2161	dsa_fdb_dump_cb_t cb, void data)
1881	2162	{
1882		- struct mv88e6xxx_vtu_entry vlan = {
1883		- .vid = chip->info->max_vid,
1884		- };
	2163	+ struct mv88e6xxx_vtu_entry vlan;
1885	2164	u16 fid;
1886	2165	int err;
1887	2166
1888	2167	/* Dump port's default Filtering Information Database (VLAN ID 0) */
1889		- mutex_lock(&chip->reg_lock);
1890	2168	err = mv88e6xxx_port_get_fid(chip, port, &fid);
1891		- mutex_unlock(&chip->reg_lock);
1892		-
1893	2169	if (err)
1894	2170	return err;
1895	2171
..	..	@@ -1898,10 +2174,11 @@
1898	2174	return err;
1899	2175
1900	2176	/* Dump VLANs' Filtering Information Databases */
	2177	+ vlan.vid = chip->info->max_vid;
	2178	+ vlan.valid = false;
	2179	+
1901	2180	do {
1902		- mutex_lock(&chip->reg_lock);
1903	2181	err = mv88e6xxx_vtu_getnext(chip, &vlan);
1904		- mutex_unlock(&chip->reg_lock);
1905	2182	if (err)
1906	2183	return err;
1907	2184
..	..	@@ -1921,39 +2198,38 @@
1921	2198	dsa_fdb_dump_cb_t cb, void data)
1922	2199	{
1923	2200	struct mv88e6xxx_chip *chip = ds->priv;
	2201	+ int err;
1924	2202
1925		- return mv88e6xxx_port_db_dump(chip, port, cb, data);
	2203	+ mv88e6xxx_reg_lock(chip);
	2204	+ err = mv88e6xxx_port_db_dump(chip, port, cb, data);
	2205	+ mv88e6xxx_reg_unlock(chip);
	2206	+
	2207	+ return err;
1926	2208	}
1927	2209
1928	2210	static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1929	2211	struct net_device *br)
1930	2212	{
1931		- struct dsa_switch *ds;
1932		- int port;
1933		- int dev;
	2213	+ struct dsa_switch *ds = chip->ds;
	2214	+ struct dsa_switch_tree *dst = ds->dst;
	2215	+ struct dsa_port *dp;
1934	2216	int err;
1935	2217
1936		- /* Remap the Port VLAN of each local bridge group member */
1937		- for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1938		- if (chip->ds->ports[port].bridge_dev == br) {
1939		- err = mv88e6xxx_port_vlan_map(chip, port);
1940		- if (err)
1941		- return err;
1942		- }
1943		- }
1944		-
1945		- if (!mv88e6xxx_has_pvt(chip))
1946		- return 0;
1947		-
1948		- /* Remap the Port VLAN of each cross-chip bridge group member */
1949		- for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1950		- ds = chip->ds->dst->ds[dev];
1951		- if (!ds)
1952		- break;
1953		-
1954		- for (port = 0; port < ds->num_ports; ++port) {
1955		- if (ds->ports[port].bridge_dev == br) {
1956		- err = mv88e6xxx_pvt_map(chip, dev, port);
	2218	+ list_for_each_entry(dp, &dst->ports, list) {
	2219	+ if (dp->bridge_dev == br) {
	2220	+ if (dp->ds == ds) {
	2221	+ /* This is a local bridge group member,
	2222	+ * remap its Port VLAN Map.
	2223	+ */
	2224	+ err = mv88e6xxx_port_vlan_map(chip, dp->index);
	2225	+ if (err)
	2226	+ return err;
	2227	+ } else {
	2228	+ /* This is an external bridge group member,
	2229	+ * remap its cross-chip Port VLAN Table entry.
	2230	+ */
	2231	+ err = mv88e6xxx_pvt_map(chip, dp->ds->index,
	2232	+ dp->index);
1957	2233	if (err)
1958	2234	return err;
1959	2235	}
..	..	@@ -1969,9 +2245,9 @@
1969	2245	struct mv88e6xxx_chip *chip = ds->priv;
1970	2246	int err;
1971	2247
1972		- mutex_lock(&chip->reg_lock);
	2248	+ mv88e6xxx_reg_lock(chip);
1973	2249	err = mv88e6xxx_bridge_map(chip, br);
1974		- mutex_unlock(&chip->reg_lock);
	2250	+ mv88e6xxx_reg_unlock(chip);
1975	2251
1976	2252	return err;
1977	2253	}
..	..	@@ -1981,41 +2257,43 @@
1981	2257	{
1982	2258	struct mv88e6xxx_chip *chip = ds->priv;
1983	2259
1984		- mutex_lock(&chip->reg_lock);
	2260	+ mv88e6xxx_reg_lock(chip);
1985	2261	if (mv88e6xxx_bridge_map(chip, br) \|\|
1986	2262	mv88e6xxx_port_vlan_map(chip, port))
1987	2263	dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1988		- mutex_unlock(&chip->reg_lock);
	2264	+ mv88e6xxx_reg_unlock(chip);
1989	2265	}
1990	2266
1991		-static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
	2267	+static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
	2268	+ int tree_index, int sw_index,
1992	2269	int port, struct net_device *br)
1993	2270	{
1994	2271	struct mv88e6xxx_chip *chip = ds->priv;
1995	2272	int err;
1996	2273
1997		- if (!mv88e6xxx_has_pvt(chip))
	2274	+ if (tree_index != ds->dst->index)
1998	2275	return 0;
1999	2276
2000		- mutex_lock(&chip->reg_lock);
2001		- err = mv88e6xxx_pvt_map(chip, dev, port);
2002		- mutex_unlock(&chip->reg_lock);
	2277	+ mv88e6xxx_reg_lock(chip);
	2278	+ err = mv88e6xxx_pvt_map(chip, sw_index, port);
	2279	+ mv88e6xxx_reg_unlock(chip);
2003	2280
2004	2281	return err;
2005	2282	}
2006	2283
2007		-static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
	2284	+static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
	2285	+ int tree_index, int sw_index,
2008	2286	int port, struct net_device *br)
2009	2287	{
2010	2288	struct mv88e6xxx_chip *chip = ds->priv;
2011	2289
2012		- if (!mv88e6xxx_has_pvt(chip))
	2290	+ if (tree_index != ds->dst->index)
2013	2291	return;
2014	2292
2015		- mutex_lock(&chip->reg_lock);
2016		- if (mv88e6xxx_pvt_map(chip, dev, port))
	2293	+ mv88e6xxx_reg_lock(chip);
	2294	+ if (mv88e6xxx_pvt_map(chip, sw_index, port))
2017	2295	dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2018		- mutex_unlock(&chip->reg_lock);
	2296	+ mv88e6xxx_reg_unlock(chip);
2019	2297	}
2020	2298
2021	2299	static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
..	..	@@ -2032,10 +2310,22 @@
2032	2310
2033	2311	/* If there is a GPIO connected to the reset pin, toggle it */
2034	2312	if (gpiod) {
	2313	+ /* If the switch has just been reset and not yet completed
	2314	+ * loading EEPROM, the reset may interrupt the I2C transaction
	2315	+ * mid-byte, causing the first EEPROM read after the reset
	2316	+ * from the wrong location resulting in the switch booting
	2317	+ * to wrong mode and inoperable.
	2318	+ */
	2319	+ if (chip->info->ops->get_eeprom)
	2320	+ mv88e6xxx_g2_eeprom_wait(chip);
	2321	+
2035	2322	gpiod_set_value_cansleep(gpiod, 1);
2036	2323	usleep_range(10000, 20000);
2037	2324	gpiod_set_value_cansleep(gpiod, 0);
2038	2325	usleep_range(10000, 20000);
	2326	+
	2327	+ if (chip->info->ops->get_eeprom)
	2328	+ mv88e6xxx_g2_eeprom_wait(chip);
2039	2329	}
2040	2330	}
2041	2331
..	..	@@ -2155,13 +2445,100 @@
2155	2445	return 0;
2156	2446	}
2157	2447
	2448	+static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
	2449	+{
	2450	+ struct mv88e6xxx_port *mvp = dev_id;
	2451	+ struct mv88e6xxx_chip *chip = mvp->chip;
	2452	+ irqreturn_t ret = IRQ_NONE;
	2453	+ int port = mvp->port;
	2454	+ u8 lane;
	2455	+
	2456	+ mv88e6xxx_reg_lock(chip);
	2457	+ lane = mv88e6xxx_serdes_get_lane(chip, port);
	2458	+ if (lane)
	2459	+ ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
	2460	+ mv88e6xxx_reg_unlock(chip);
	2461	+
	2462	+ return ret;
	2463	+}
	2464	+
	2465	+static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
	2466	+ u8 lane)
	2467	+{
	2468	+ struct mv88e6xxx_port *dev_id = &chip->ports[port];
	2469	+ unsigned int irq;
	2470	+ int err;
	2471	+
	2472	+ /* Nothing to request if this SERDES port has no IRQ */
	2473	+ irq = mv88e6xxx_serdes_irq_mapping(chip, port);
	2474	+ if (!irq)
	2475	+ return 0;
	2476	+
	2477	+ snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
	2478	+ "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
	2479	+
	2480	+ /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
	2481	+ mv88e6xxx_reg_unlock(chip);
	2482	+ err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
	2483	+ IRQF_ONESHOT, dev_id->serdes_irq_name,
	2484	+ dev_id);
	2485	+ mv88e6xxx_reg_lock(chip);
	2486	+ if (err)
	2487	+ return err;
	2488	+
	2489	+ dev_id->serdes_irq = irq;
	2490	+
	2491	+ return mv88e6xxx_serdes_irq_enable(chip, port, lane);
	2492	+}
	2493	+
	2494	+static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
	2495	+ u8 lane)
	2496	+{
	2497	+ struct mv88e6xxx_port *dev_id = &chip->ports[port];
	2498	+ unsigned int irq = dev_id->serdes_irq;
	2499	+ int err;
	2500	+
	2501	+ /* Nothing to free if no IRQ has been requested */
	2502	+ if (!irq)
	2503	+ return 0;
	2504	+
	2505	+ err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
	2506	+
	2507	+ /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
	2508	+ mv88e6xxx_reg_unlock(chip);
	2509	+ free_irq(irq, dev_id);
	2510	+ mv88e6xxx_reg_lock(chip);
	2511	+
	2512	+ dev_id->serdes_irq = 0;
	2513	+
	2514	+ return err;
	2515	+}
	2516	+
2158	2517	static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2159	2518	bool on)
2160	2519	{
2161		- if (chip->info->ops->serdes_power)
2162		- return chip->info->ops->serdes_power(chip, port, on);
	2520	+ u8 lane;
	2521	+ int err;
2163	2522
2164		- return 0;
	2523	+ lane = mv88e6xxx_serdes_get_lane(chip, port);
	2524	+ if (!lane)
	2525	+ return 0;
	2526	+
	2527	+ if (on) {
	2528	+ err = mv88e6xxx_serdes_power_up(chip, port, lane);
	2529	+ if (err)
	2530	+ return err;
	2531	+
	2532	+ err = mv88e6xxx_serdes_irq_request(chip, port, lane);
	2533	+ } else {
	2534	+ err = mv88e6xxx_serdes_irq_free(chip, port, lane);
	2535	+ if (err)
	2536	+ return err;
	2537	+
	2538	+ err = mv88e6xxx_serdes_power_down(chip, port, lane);
	2539	+ }
	2540	+
	2541	+ return err;
2165	2542	}
2166	2543
2167	2544	static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
..	..	@@ -2188,7 +2565,14 @@
2188	2565
2189	2566	if (chip->info->ops->set_egress_port) {
2190	2567	err = chip->info->ops->set_egress_port(chip,
2191		- upstream_port);
	2568	+ MV88E6XXX_EGRESS_DIR_INGRESS,
	2569	+ upstream_port);
	2570	+ if (err)
	2571	+ return err;
	2572	+
	2573	+ err = chip->info->ops->set_egress_port(chip,
	2574	+ MV88E6XXX_EGRESS_DIR_EGRESS,
	2575	+ upstream_port);
2192	2576	if (err)
2193	2577	return err;
2194	2578	}
..	..	@@ -2237,9 +2621,14 @@
2237	2621	* If this is the upstream port for this switch, enable
2238	2622	* forwarding of unknown unicasts and multicasts.
2239	2623	*/
2240		- reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP \|
2241		- MV88E6185_PORT_CTL0_USE_TAG \| MV88E6185_PORT_CTL0_USE_IP \|
	2624	+ reg = MV88E6185_PORT_CTL0_USE_TAG \| MV88E6185_PORT_CTL0_USE_IP \|
2242	2625	MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
	2626	+ /* Forward any IPv4 IGMP or IPv6 MLD frames received
	2627	+ * by a USER port to the CPU port to allow snooping.
	2628	+ */
	2629	+ if (dsa_is_user_port(ds, port))
	2630	+ reg \|= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP;
	2631	+
2243	2632	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2244	2633	if (err)
2245	2634	return err;
..	..	@@ -2252,18 +2641,8 @@
2252	2641	if (err)
2253	2642	return err;
2254	2643
2255		- /* Enable the SERDES interface for DSA and CPU ports. Normal
2256		- * ports SERDES are enabled when the port is enabled, thus
2257		- * saving a bit of power.
2258		- */
2259		- if ((dsa_is_cpu_port(ds, port) \|\| dsa_is_dsa_port(ds, port))) {
2260		- err = mv88e6xxx_serdes_power(chip, port, true);
2261		- if (err)
2262		- return err;
2263		- }
2264		-
2265		- /* Port Control 2: don't force a good FCS, set the maximum frame size to
2266		- * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
	2644	+ /* Port Control 2: don't force a good FCS, set the MTU size to
	2645	+ * 10222 bytes, disable 802.1q tags checking, don't discard tagged or
2267	2646	* untagged frames on this port, do a destination address lookup on all
2268	2647	* received packets as usual, disable ARP mirroring and don't send a
2269	2648	* copy of all transmitted/received frames on this port to the CPU.
..	..	@@ -2282,7 +2661,7 @@
2282	2661	return err;
2283	2662
2284	2663	if (chip->info->ops->port_set_jumbo_size) {
2285		- err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
	2664	+ err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
2286	2665	if (err)
2287	2666	return err;
2288	2667	}
..	..	@@ -2338,9 +2717,11 @@
2338	2717	return err;
2339	2718	}
2340	2719
2341		- err = mv88e6xxx_setup_message_port(chip, port);
2342		- if (err)
2343		- return err;
	2720	+ if (chip->info->ops->port_setup_message_port) {
	2721	+ err = chip->info->ops->port_setup_message_port(chip, port);
	2722	+ if (err)
	2723	+ return err;
	2724	+ }
2344	2725
2345	2726	/* Port based VLAN map: give each port the same default address
2346	2727	* database, and allow bidirectional communication between the
..	..	@@ -2360,38 +2741,67 @@
2360	2741	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2361	2742	}
2362	2743
	2744	+static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
	2745	+{
	2746	+ struct mv88e6xxx_chip *chip = ds->priv;
	2747	+
	2748	+ if (chip->info->ops->port_set_jumbo_size)
	2749	+ return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
	2750	+ else if (chip->info->ops->set_max_frame_size)
	2751	+ return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
	2752	+ return ETH_DATA_LEN;
	2753	+}
	2754	+
	2755	+static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
	2756	+{
	2757	+ struct mv88e6xxx_chip *chip = ds->priv;
	2758	+ int ret = 0;
	2759	+
	2760	+ /* For families where we don't know how to alter the MTU,
	2761	+ * just accept any value up to ETH_DATA_LEN
	2762	+ */
	2763	+ if (!chip->info->ops->port_set_jumbo_size &&
	2764	+ !chip->info->ops->set_max_frame_size) {
	2765	+ if (new_mtu > ETH_DATA_LEN)
	2766	+ return -EINVAL;
	2767	+
	2768	+ return 0;
	2769	+ }
	2770	+
	2771	+ if (dsa_is_dsa_port(ds, port) \|\| dsa_is_cpu_port(ds, port))
	2772	+ new_mtu += EDSA_HLEN;
	2773	+
	2774	+ mv88e6xxx_reg_lock(chip);
	2775	+ if (chip->info->ops->port_set_jumbo_size)
	2776	+ ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
	2777	+ else if (chip->info->ops->set_max_frame_size)
	2778	+ ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
	2779	+ mv88e6xxx_reg_unlock(chip);
	2780	+
	2781	+ return ret;
	2782	+}
	2783	+
2363	2784	static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2364	2785	struct phy_device *phydev)
2365	2786	{
2366	2787	struct mv88e6xxx_chip *chip = ds->priv;
2367	2788	int err;
2368	2789
2369		- mutex_lock(&chip->reg_lock);
2370		-
	2790	+ mv88e6xxx_reg_lock(chip);
2371	2791	err = mv88e6xxx_serdes_power(chip, port, true);
2372		-
2373		- if (!err && chip->info->ops->serdes_irq_setup)
2374		- err = chip->info->ops->serdes_irq_setup(chip, port);
2375		-
2376		- mutex_unlock(&chip->reg_lock);
	2792	+ mv88e6xxx_reg_unlock(chip);
2377	2793
2378	2794	return err;
2379	2795	}
2380	2796
2381		-static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
2382		- struct phy_device *phydev)
	2797	+static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
2383	2798	{
2384	2799	struct mv88e6xxx_chip *chip = ds->priv;
2385	2800
2386		- mutex_lock(&chip->reg_lock);
2387		-
2388		- if (chip->info->ops->serdes_irq_free)
2389		- chip->info->ops->serdes_irq_free(chip, port);
2390		-
	2801	+ mv88e6xxx_reg_lock(chip);
2391	2802	if (mv88e6xxx_serdes_power(chip, port, false))
2392	2803	dev_err(chip->dev, "failed to power off SERDES\n");
2393		-
2394		- mutex_unlock(&chip->reg_lock);
	2804	+ mv88e6xxx_reg_unlock(chip);
2395	2805	}
2396	2806
2397	2807	static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
..	..	@@ -2400,9 +2810,9 @@
2400	2810	struct mv88e6xxx_chip *chip = ds->priv;
2401	2811	int err;
2402	2812
2403		- mutex_lock(&chip->reg_lock);
	2813	+ mv88e6xxx_reg_lock(chip);
2404	2814	err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2405		- mutex_unlock(&chip->reg_lock);
	2815	+ mv88e6xxx_reg_unlock(chip);
2406	2816
2407	2817	return err;
2408	2818	}
..	..	@@ -2421,58 +2831,6 @@
2421	2831	return mv88e6xxx_g1_stats_clear(chip);
2422	2832	}
2423	2833
2424		-/* The mv88e6390 has some hidden registers used for debug and
2425		- * development. The errata also makes use of them.
2426		- */
2427		-static int mv88e6390_hidden_write(struct mv88e6xxx_chip *chip, int port,
2428		- int reg, u16 val)
2429		-{
2430		- u16 ctrl;
2431		- int err;
2432		-
2433		- err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_DATA_PORT,
2434		- PORT_RESERVED_1A, val);
2435		- if (err)
2436		- return err;
2437		-
2438		- ctrl = PORT_RESERVED_1A_BUSY \| PORT_RESERVED_1A_WRITE \|
2439		- PORT_RESERVED_1A_BLOCK \| port << PORT_RESERVED_1A_PORT_SHIFT \|
2440		- reg;
2441		-
2442		- return mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2443		- PORT_RESERVED_1A, ctrl);
2444		-}
2445		-
2446		-static int mv88e6390_hidden_wait(struct mv88e6xxx_chip *chip)
2447		-{
2448		- return mv88e6xxx_wait(chip, PORT_RESERVED_1A_CTRL_PORT,
2449		- PORT_RESERVED_1A, PORT_RESERVED_1A_BUSY);
2450		-}
2451		-
2452		-
2453		-static int mv88e6390_hidden_read(struct mv88e6xxx_chip *chip, int port,
2454		- int reg, u16 *val)
2455		-{
2456		- u16 ctrl;
2457		- int err;
2458		-
2459		- ctrl = PORT_RESERVED_1A_BUSY \| PORT_RESERVED_1A_READ \|
2460		- PORT_RESERVED_1A_BLOCK \| port << PORT_RESERVED_1A_PORT_SHIFT \|
2461		- reg;
2462		-
2463		- err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2464		- PORT_RESERVED_1A, ctrl);
2465		- if (err)
2466		- return err;
2467		-
2468		- err = mv88e6390_hidden_wait(chip);
2469		- if (err)
2470		- return err;
2471		-
2472		- return mv88e6xxx_port_read(chip, PORT_RESERVED_1A_DATA_PORT,
2473		- PORT_RESERVED_1A, val);
2474		-}
2475		-
2476	2834	/* Check if the errata has already been applied. */
2477	2835	static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2478	2836	{
..	..	@@ -2481,7 +2839,7 @@
2481	2839	u16 val;
2482	2840
2483	2841	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2484		- err = mv88e6390_hidden_read(chip, port, 0, &val);
	2842	+ err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
2485	2843	if (err) {
2486	2844	dev_err(chip->dev,
2487	2845	"Error reading hidden register: %d\n", err);
..	..	@@ -2514,12 +2872,19 @@
2514	2872	}
2515	2873
2516	2874	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2517		- err = mv88e6390_hidden_write(chip, port, 0, 0x01c0);
	2875	+ err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
2518	2876	if (err)
2519	2877	return err;
2520	2878	}
2521	2879
2522	2880	return mv88e6xxx_software_reset(chip);
	2881	+}
	2882	+
	2883	+static void mv88e6xxx_teardown(struct dsa_switch *ds)
	2884	+{
	2885	+ mv88e6xxx_teardown_devlink_params(ds);
	2886	+ dsa_devlink_resources_unregister(ds);
	2887	+ mv88e6xxx_teardown_devlink_regions(ds);
2523	2888	}
2524	2889
2525	2890	static int mv88e6xxx_setup(struct dsa_switch *ds)
..	..	@@ -2532,7 +2897,7 @@
2532	2897	chip->ds = ds;
2533	2898	ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2534	2899
2535		- mutex_lock(&chip->reg_lock);
	2900	+ mv88e6xxx_reg_lock(chip);
2536	2901
2537	2902	if (chip->info->ops->setup_errata) {
2538	2903	err = chip->info->ops->setup_errata(chip);
..	..	@@ -2555,6 +2920,13 @@
2555	2920	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2556	2921	if (dsa_is_unused_port(ds, i))
2557	2922	continue;
	2923	+
	2924	+ /* Prevent the use of an invalid port. */
	2925	+ if (mv88e6xxx_is_invalid_port(chip, i)) {
	2926	+ dev_err(chip->dev, "port %d is invalid\n", i);
	2927	+ err = -EINVAL;
	2928	+ goto unlock;
	2929	+ }
2558	2930
2559	2931	err = mv88e6xxx_setup_port(chip, i);
2560	2932	if (err)
..	..	@@ -2629,7 +3001,34 @@
2629	3001	goto unlock;
2630	3002
2631	3003	unlock:
2632		- mutex_unlock(&chip->reg_lock);
	3004	+ mv88e6xxx_reg_unlock(chip);
	3005	+
	3006	+ if (err)
	3007	+ return err;
	3008	+
	3009	+ /* Have to be called without holding the register lock, since
	3010	+ * they take the devlink lock, and we later take the locks in
	3011	+ * the reverse order when getting/setting parameters or
	3012	+ * resource occupancy.
	3013	+ */
	3014	+ err = mv88e6xxx_setup_devlink_resources(ds);
	3015	+ if (err)
	3016	+ return err;
	3017	+
	3018	+ err = mv88e6xxx_setup_devlink_params(ds);
	3019	+ if (err)
	3020	+ goto out_resources;
	3021	+
	3022	+ err = mv88e6xxx_setup_devlink_regions(ds);
	3023	+ if (err)
	3024	+ goto out_params;
	3025	+
	3026	+ return 0;
	3027	+
	3028	+out_params:
	3029	+ mv88e6xxx_teardown_devlink_params(ds);
	3030	+out_resources:
	3031	+ dsa_devlink_resources_unregister(ds);
2633	3032
2634	3033	return err;
2635	3034	}
..	..	@@ -2651,9 +3050,9 @@
2651	3050	if (!chip->info->ops->phy_read)
2652	3051	return -EOPNOTSUPP;
2653	3052
2654		- mutex_lock(&chip->reg_lock);
	3053	+ mv88e6xxx_reg_lock(chip);
2655	3054	err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2656		- mutex_unlock(&chip->reg_lock);
	3055	+ mv88e6xxx_reg_unlock(chip);
2657	3056
2658	3057	/* Some internal PHYs don't have a model number. */
2659	3058	if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
..	..	@@ -2675,9 +3074,9 @@
2675	3074	if (!chip->info->ops->phy_write)
2676	3075	return -EOPNOTSUPP;
2677	3076
2678		- mutex_lock(&chip->reg_lock);
	3077	+ mv88e6xxx_reg_lock(chip);
2679	3078	err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2680		- mutex_unlock(&chip->reg_lock);
	3079	+ mv88e6xxx_reg_unlock(chip);
2681	3080
2682	3081	return err;
2683	3082	}
..	..	@@ -2692,15 +3091,15 @@
2692	3091	int err;
2693	3092
2694	3093	if (external) {
2695		- mutex_lock(&chip->reg_lock);
	3094	+ mv88e6xxx_reg_lock(chip);
2696	3095	err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
2697		- mutex_unlock(&chip->reg_lock);
	3096	+ mv88e6xxx_reg_unlock(chip);
2698	3097
2699	3098	if (err)
2700	3099	return err;
2701	3100	}
2702	3101
2703		- bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
	3102	+ bus = mdiobus_alloc_size(sizeof(*mdio_bus));
2704	3103	if (!bus)
2705	3104	return -ENOMEM;
2706	3105
..	..	@@ -2725,14 +3124,14 @@
2725	3124	if (!external) {
2726	3125	err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
2727	3126	if (err)
2728		- return err;
	3127	+ goto out;
2729	3128	}
2730	3129
2731	3130	err = of_mdiobus_register(bus, np);
2732	3131	if (err) {
2733	3132	dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2734	3133	mv88e6xxx_g2_irq_mdio_free(chip, bus);
2735		- return err;
	3134	+ goto out;
2736	3135	}
2737	3136
2738	3137	if (external)
..	..	@@ -2741,34 +3140,32 @@
2741	3140	list_add(&mdio_bus->list, &chip->mdios);
2742	3141
2743	3142	return 0;
2744		-}
2745	3143
2746		-static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2747		- { .compatible = "marvell,mv88e6xxx-mdio-external",
2748		- .data = (void *)true },
2749		- { },
2750		-};
	3144	+out:
	3145	+ mdiobus_free(bus);
	3146	+ return err;
	3147	+}
2751	3148
2752	3149	static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2753	3150
2754	3151	{
2755		- struct mv88e6xxx_mdio_bus *mdio_bus;
	3152	+ struct mv88e6xxx_mdio_bus mdio_bus, p;
2756	3153	struct mii_bus *bus;
2757	3154
2758		- list_for_each_entry(mdio_bus, &chip->mdios, list) {
	3155	+ list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
2759	3156	bus = mdio_bus->bus;
2760	3157
2761	3158	if (!mdio_bus->external)
2762	3159	mv88e6xxx_g2_irq_mdio_free(chip, bus);
2763	3160
2764	3161	mdiobus_unregister(bus);
	3162	+ mdiobus_free(bus);
2765	3163	}
2766	3164	}
2767	3165
2768	3166	static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2769	3167	struct device_node *np)
2770	3168	{
2771		- const struct of_device_id *match;
2772	3169	struct device_node *child;
2773	3170	int err;
2774	3171
..	..	@@ -2778,6 +3175,7 @@
2778	3175	*/
2779	3176	child = of_get_child_by_name(np, "mdio");
2780	3177	err = mv88e6xxx_mdio_register(chip, child, false);
	3178	+ of_node_put(child);
2781	3179	if (err)
2782	3180	return err;
2783	3181
..	..	@@ -2786,11 +3184,12 @@
2786	3184	* bus.
2787	3185	*/
2788	3186	for_each_available_child_of_node(np, child) {
2789		- match = of_match_node(mv88e6xxx_mdio_external_match, child);
2790		- if (match) {
	3187	+ if (of_device_is_compatible(
	3188	+ child, "marvell,mv88e6xxx-mdio-external")) {
2791	3189	err = mv88e6xxx_mdio_register(chip, child, true);
2792	3190	if (err) {
2793	3191	mv88e6xxx_mdios_unregister(chip);
	3192	+ of_node_put(child);
2794	3193	return err;
2795	3194	}
2796	3195	}
..	..	@@ -2815,9 +3214,9 @@
2815	3214	if (!chip->info->ops->get_eeprom)
2816	3215	return -EOPNOTSUPP;
2817	3216
2818		- mutex_lock(&chip->reg_lock);
	3217	+ mv88e6xxx_reg_lock(chip);
2819	3218	err = chip->info->ops->get_eeprom(chip, eeprom, data);
2820		- mutex_unlock(&chip->reg_lock);
	3219	+ mv88e6xxx_reg_unlock(chip);
2821	3220
2822	3221	if (err)
2823	3222	return err;
..	..	@@ -2839,9 +3238,9 @@
2839	3238	if (eeprom->magic != 0xc3ec4951)
2840	3239	return -EINVAL;
2841	3240
2842		- mutex_lock(&chip->reg_lock);
	3241	+ mv88e6xxx_reg_lock(chip);
2843	3242	err = chip->info->ops->set_eeprom(chip, eeprom, data);
2844		- mutex_unlock(&chip->reg_lock);
	3243	+ mv88e6xxx_reg_unlock(chip);
2845	3244
2846	3245	return err;
2847	3246	}
..	..	@@ -2855,8 +3254,7 @@
2855	3254	.phy_read = mv88e6185_phy_ppu_read,
2856	3255	.phy_write = mv88e6185_phy_ppu_write,
2857	3256	.port_set_link = mv88e6xxx_port_set_link,
2858		- .port_set_duplex = mv88e6xxx_port_set_duplex,
2859		- .port_set_speed = mv88e6185_port_set_speed,
	3257	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
2860	3258	.port_tag_remap = mv88e6095_port_tag_remap,
2861	3259	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2862	3260	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
..	..	@@ -2865,8 +3263,8 @@
2865	3263	.port_pause_limit = mv88e6097_port_pause_limit,
2866	3264	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2867	3265	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2868		- .port_link_state = mv88e6352_port_link_state,
2869	3266	.port_get_cmode = mv88e6185_port_get_cmode,
	3267	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
2870	3268	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2871	3269	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2872	3270	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -2884,6 +3282,7 @@
2884	3282	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2885	3283	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2886	3284	.phylink_validate = mv88e6185_phylink_validate,
	3285	+ .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
2887	3286	};
2888	3287
2889	3288	static const struct mv88e6xxx_ops mv88e6095_ops = {
..	..	@@ -2894,13 +3293,12 @@
2894	3293	.phy_read = mv88e6185_phy_ppu_read,
2895	3294	.phy_write = mv88e6185_phy_ppu_write,
2896	3295	.port_set_link = mv88e6xxx_port_set_link,
2897		- .port_set_duplex = mv88e6xxx_port_set_duplex,
2898		- .port_set_speed = mv88e6185_port_set_speed,
	3296	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
2899	3297	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2900	3298	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2901	3299	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2902		- .port_link_state = mv88e6185_port_link_state,
2903	3300	.port_get_cmode = mv88e6185_port_get_cmode,
	3301	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
2904	3302	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2905	3303	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2906	3304	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -2913,6 +3311,7 @@
2913	3311	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2914	3312	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2915	3313	.phylink_validate = mv88e6185_phylink_validate,
	3314	+ .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
2916	3315	};
2917	3316
2918	3317	static const struct mv88e6xxx_ops mv88e6097_ops = {
..	..	@@ -2924,9 +3323,9 @@
2924	3323	.phy_read = mv88e6xxx_g2_smi_phy_read,
2925	3324	.phy_write = mv88e6xxx_g2_smi_phy_write,
2926	3325	.port_set_link = mv88e6xxx_port_set_link,
2927		- .port_set_duplex = mv88e6xxx_port_set_duplex,
2928		- .port_set_speed = mv88e6185_port_set_speed,
	3326	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
2929	3327	.port_tag_remap = mv88e6095_port_tag_remap,
	3328	+ .port_set_policy = mv88e6352_port_set_policy,
2930	3329	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2931	3330	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2932	3331	.port_set_ether_type = mv88e6351_port_set_ether_type,
..	..	@@ -2934,8 +3333,8 @@
2934	3333	.port_pause_limit = mv88e6097_port_pause_limit,
2935	3334	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2936	3335	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2937		- .port_link_state = mv88e6352_port_link_state,
2938	3336	.port_get_cmode = mv88e6185_port_get_cmode,
	3337	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
2939	3338	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2940	3339	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2941	3340	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -2951,6 +3350,7 @@
2951	3350	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2952	3351	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2953	3352	.phylink_validate = mv88e6185_phylink_validate,
	3353	+ .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
2954	3354	};
2955	3355
2956	3356	static const struct mv88e6xxx_ops mv88e6123_ops = {
..	..	@@ -2962,14 +3362,13 @@
2962	3362	.phy_read = mv88e6xxx_g2_smi_phy_read,
2963	3363	.phy_write = mv88e6xxx_g2_smi_phy_write,
2964	3364	.port_set_link = mv88e6xxx_port_set_link,
2965		- .port_set_duplex = mv88e6xxx_port_set_duplex,
2966		- .port_set_speed = mv88e6185_port_set_speed,
	3365	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
2967	3366	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2968	3367	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2969	3368	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2970	3369	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2971		- .port_link_state = mv88e6352_port_link_state,
2972	3370	.port_get_cmode = mv88e6185_port_get_cmode,
	3371	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
2973	3372	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2974	3373	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2975	3374	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -2981,9 +3380,12 @@
2981	3380	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2982	3381	.pot_clear = mv88e6xxx_g2_pot_clear,
2983	3382	.reset = mv88e6352_g1_reset,
	3383	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3384	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
2984	3385	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2985	3386	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2986	3387	.phylink_validate = mv88e6185_phylink_validate,
	3388	+ .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
2987	3389	};
2988	3390
2989	3391	static const struct mv88e6xxx_ops mv88e6131_ops = {
..	..	@@ -2994,8 +3396,7 @@
2994	3396	.phy_read = mv88e6185_phy_ppu_read,
2995	3397	.phy_write = mv88e6185_phy_ppu_write,
2996	3398	.port_set_link = mv88e6xxx_port_set_link,
2997		- .port_set_duplex = mv88e6xxx_port_set_duplex,
2998		- .port_set_speed = mv88e6185_port_set_speed,
	3399	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
2999	3400	.port_tag_remap = mv88e6095_port_tag_remap,
3000	3401	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3001	3402	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
..	..	@@ -3005,8 +3406,8 @@
3005	3406	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3006	3407	.port_pause_limit = mv88e6097_port_pause_limit,
3007	3408	.port_set_pause = mv88e6185_port_set_pause,
3008		- .port_link_state = mv88e6352_port_link_state,
3009	3409	.port_get_cmode = mv88e6185_port_get_cmode,
	3410	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3010	3411	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3011	3412	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3012	3413	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3036,9 +3437,9 @@
3036	3437	.phy_read = mv88e6xxx_g2_smi_phy_read,
3037	3438	.phy_write = mv88e6xxx_g2_smi_phy_write,
3038	3439	.port_set_link = mv88e6xxx_port_set_link,
3039		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3040	3440	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3041		- .port_set_speed = mv88e6341_port_set_speed,
	3441	+ .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
	3442	+ .port_max_speed_mode = mv88e6341_port_max_speed_mode,
3042	3443	.port_tag_remap = mv88e6095_port_tag_remap,
3043	3444	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3044	3445	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
..	..	@@ -3048,8 +3449,9 @@
3048	3449	.port_pause_limit = mv88e6097_port_pause_limit,
3049	3450	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3050	3451	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3051		- .port_link_state = mv88e6352_port_link_state,
3052	3452	.port_get_cmode = mv88e6352_port_get_cmode,
	3453	+ .port_set_cmode = mv88e6341_port_set_cmode,
	3454	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3053	3455	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3054	3456	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3055	3457	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
..	..	@@ -3061,11 +3463,28 @@
3061	3463	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3062	3464	.pot_clear = mv88e6xxx_g2_pot_clear,
3063	3465	.reset = mv88e6352_g1_reset,
	3466	+ .rmu_disable = mv88e6390_g1_rmu_disable,
	3467	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3468	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3064	3469	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3065	3470	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3066		- .serdes_power = mv88e6341_serdes_power,
	3471	+ .serdes_power = mv88e6390_serdes_power,
	3472	+ .serdes_get_lane = mv88e6341_serdes_get_lane,
	3473	+ /* Check status register pause & lpa register */
	3474	+ .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
	3475	+ .serdes_pcs_config = mv88e6390_serdes_pcs_config,
	3476	+ .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
	3477	+ .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
	3478	+ .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
	3479	+ .serdes_irq_enable = mv88e6390_serdes_irq_enable,
	3480	+ .serdes_irq_status = mv88e6390_serdes_irq_status,
3067	3481	.gpio_ops = &mv88e6352_gpio_ops,
3068		- .phylink_validate = mv88e6390_phylink_validate,
	3482	+ .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
	3483	+ .serdes_get_strings = mv88e6390_serdes_get_strings,
	3484	+ .serdes_get_stats = mv88e6390_serdes_get_stats,
	3485	+ .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
	3486	+ .serdes_get_regs = mv88e6390_serdes_get_regs,
	3487	+ .phylink_validate = mv88e6341_phylink_validate,
3069	3488	};
3070	3489
3071	3490	static const struct mv88e6xxx_ops mv88e6161_ops = {
..	..	@@ -3077,19 +3496,17 @@
3077	3496	.phy_read = mv88e6xxx_g2_smi_phy_read,
3078	3497	.phy_write = mv88e6xxx_g2_smi_phy_write,
3079	3498	.port_set_link = mv88e6xxx_port_set_link,
3080		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3081		- .port_set_speed = mv88e6185_port_set_speed,
	3499	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3082	3500	.port_tag_remap = mv88e6095_port_tag_remap,
3083	3501	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3084	3502	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3085	3503	.port_set_ether_type = mv88e6351_port_set_ether_type,
3086		- .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3087	3504	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3088	3505	.port_pause_limit = mv88e6097_port_pause_limit,
3089	3506	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3090	3507	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3091		- .port_link_state = mv88e6352_port_link_state,
3092	3508	.port_get_cmode = mv88e6185_port_get_cmode,
	3509	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3093	3510	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3094	3511	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3095	3512	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3101,11 +3518,14 @@
3101	3518	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3102	3519	.pot_clear = mv88e6xxx_g2_pot_clear,
3103	3520	.reset = mv88e6352_g1_reset,
	3521	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3522	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3104	3523	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3105	3524	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3106	3525	.avb_ops = &mv88e6165_avb_ops,
3107	3526	.ptp_ops = &mv88e6165_ptp_ops,
3108	3527	.phylink_validate = mv88e6185_phylink_validate,
	3528	+ .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3109	3529	};
3110	3530
3111	3531	static const struct mv88e6xxx_ops mv88e6165_ops = {
..	..	@@ -3117,12 +3537,11 @@
3117	3537	.phy_read = mv88e6165_phy_read,
3118	3538	.phy_write = mv88e6165_phy_write,
3119	3539	.port_set_link = mv88e6xxx_port_set_link,
3120		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3121		- .port_set_speed = mv88e6185_port_set_speed,
	3540	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3122	3541	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3123	3542	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3124		- .port_link_state = mv88e6352_port_link_state,
3125	3543	.port_get_cmode = mv88e6185_port_get_cmode,
	3544	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3126	3545	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3127	3546	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3128	3547	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3134,6 +3553,8 @@
3134	3553	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3135	3554	.pot_clear = mv88e6xxx_g2_pot_clear,
3136	3555	.reset = mv88e6352_g1_reset,
	3556	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3557	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3137	3558	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3138	3559	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3139	3560	.avb_ops = &mv88e6165_avb_ops,
..	..	@@ -3150,9 +3571,8 @@
3150	3571	.phy_read = mv88e6xxx_g2_smi_phy_read,
3151	3572	.phy_write = mv88e6xxx_g2_smi_phy_write,
3152	3573	.port_set_link = mv88e6xxx_port_set_link,
3153		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3154	3574	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3155		- .port_set_speed = mv88e6185_port_set_speed,
	3575	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3156	3576	.port_tag_remap = mv88e6095_port_tag_remap,
3157	3577	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3158	3578	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
..	..	@@ -3162,8 +3582,8 @@
3162	3582	.port_pause_limit = mv88e6097_port_pause_limit,
3163	3583	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3164	3584	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3165		- .port_link_state = mv88e6352_port_link_state,
3166	3585	.port_get_cmode = mv88e6352_port_get_cmode,
	3586	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3167	3587	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3168	3588	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3169	3589	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3175,6 +3595,8 @@
3175	3595	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3176	3596	.pot_clear = mv88e6xxx_g2_pot_clear,
3177	3597	.reset = mv88e6352_g1_reset,
	3598	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3599	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3178	3600	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3179	3601	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3180	3602	.phylink_validate = mv88e6185_phylink_validate,
..	..	@@ -3191,10 +3613,10 @@
3191	3613	.phy_read = mv88e6xxx_g2_smi_phy_read,
3192	3614	.phy_write = mv88e6xxx_g2_smi_phy_write,
3193	3615	.port_set_link = mv88e6xxx_port_set_link,
3194		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3195	3616	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3196		- .port_set_speed = mv88e6352_port_set_speed,
	3617	+ .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3197	3618	.port_tag_remap = mv88e6095_port_tag_remap,
	3619	+ .port_set_policy = mv88e6352_port_set_policy,
3198	3620	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3199	3621	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3200	3622	.port_set_ether_type = mv88e6351_port_set_ether_type,
..	..	@@ -3203,8 +3625,8 @@
3203	3625	.port_pause_limit = mv88e6097_port_pause_limit,
3204	3626	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3205	3627	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3206		- .port_link_state = mv88e6352_port_link_state,
3207	3628	.port_get_cmode = mv88e6352_port_get_cmode,
	3629	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3208	3630	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3209	3631	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3210	3632	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3217,9 +3639,18 @@
3217	3639	.pot_clear = mv88e6xxx_g2_pot_clear,
3218	3640	.reset = mv88e6352_g1_reset,
3219	3641	.rmu_disable = mv88e6352_g1_rmu_disable,
	3642	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3643	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3220	3644	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3221	3645	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
	3646	+ .serdes_get_lane = mv88e6352_serdes_get_lane,
	3647	+ .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
	3648	+ .serdes_pcs_config = mv88e6352_serdes_pcs_config,
	3649	+ .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
	3650	+ .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3222	3651	.serdes_power = mv88e6352_serdes_power,
	3652	+ .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
	3653	+ .serdes_get_regs = mv88e6352_serdes_get_regs,
3223	3654	.gpio_ops = &mv88e6352_gpio_ops,
3224	3655	.phylink_validate = mv88e6352_phylink_validate,
3225	3656	};
..	..	@@ -3233,10 +3664,10 @@
3233	3664	.phy_read = mv88e6xxx_g2_smi_phy_read,
3234	3665	.phy_write = mv88e6xxx_g2_smi_phy_write,
3235	3666	.port_set_link = mv88e6xxx_port_set_link,
3236		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3237	3667	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3238		- .port_set_speed = mv88e6185_port_set_speed,
	3668	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3239	3669	.port_tag_remap = mv88e6095_port_tag_remap,
	3670	+ .port_set_policy = mv88e6352_port_set_policy,
3240	3671	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3241	3672	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3242	3673	.port_set_ether_type = mv88e6351_port_set_ether_type,
..	..	@@ -3245,8 +3676,8 @@
3245	3676	.port_pause_limit = mv88e6097_port_pause_limit,
3246	3677	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3247	3678	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3248		- .port_link_state = mv88e6352_port_link_state,
3249	3679	.port_get_cmode = mv88e6352_port_get_cmode,
	3680	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3250	3681	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3251	3682	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3252	3683	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3258,6 +3689,8 @@
3258	3689	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3259	3690	.pot_clear = mv88e6xxx_g2_pot_clear,
3260	3691	.reset = mv88e6352_g1_reset,
	3692	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3693	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3261	3694	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3262	3695	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3263	3696	.phylink_validate = mv88e6185_phylink_validate,
..	..	@@ -3274,10 +3707,10 @@
3274	3707	.phy_read = mv88e6xxx_g2_smi_phy_read,
3275	3708	.phy_write = mv88e6xxx_g2_smi_phy_write,
3276	3709	.port_set_link = mv88e6xxx_port_set_link,
3277		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3278	3710	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3279		- .port_set_speed = mv88e6352_port_set_speed,
	3711	+ .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3280	3712	.port_tag_remap = mv88e6095_port_tag_remap,
	3713	+ .port_set_policy = mv88e6352_port_set_policy,
3281	3714	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3282	3715	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3283	3716	.port_set_ether_type = mv88e6351_port_set_ether_type,
..	..	@@ -3286,8 +3719,8 @@
3286	3719	.port_pause_limit = mv88e6097_port_pause_limit,
3287	3720	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3288	3721	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3289		- .port_link_state = mv88e6352_port_link_state,
3290	3722	.port_get_cmode = mv88e6352_port_get_cmode,
	3723	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3291	3724	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3292	3725	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3293	3726	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3300,9 +3733,21 @@
3300	3733	.pot_clear = mv88e6xxx_g2_pot_clear,
3301	3734	.reset = mv88e6352_g1_reset,
3302	3735	.rmu_disable = mv88e6352_g1_rmu_disable,
	3736	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3737	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3303	3738	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3304	3739	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
	3740	+ .serdes_get_lane = mv88e6352_serdes_get_lane,
	3741	+ .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
	3742	+ .serdes_pcs_config = mv88e6352_serdes_pcs_config,
	3743	+ .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
	3744	+ .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3305	3745	.serdes_power = mv88e6352_serdes_power,
	3746	+ .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
	3747	+ .serdes_irq_enable = mv88e6352_serdes_irq_enable,
	3748	+ .serdes_irq_status = mv88e6352_serdes_irq_status,
	3749	+ .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
	3750	+ .serdes_get_regs = mv88e6352_serdes_get_regs,
3306	3751	.gpio_ops = &mv88e6352_gpio_ops,
3307	3752	.phylink_validate = mv88e6352_phylink_validate,
3308	3753	};
..	..	@@ -3315,15 +3760,14 @@
3315	3760	.phy_read = mv88e6185_phy_ppu_read,
3316	3761	.phy_write = mv88e6185_phy_ppu_write,
3317	3762	.port_set_link = mv88e6xxx_port_set_link,
3318		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3319		- .port_set_speed = mv88e6185_port_set_speed,
	3763	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3320	3764	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
3321	3765	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
3322	3766	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3323	3767	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
3324	3768	.port_set_pause = mv88e6185_port_set_pause,
3325		- .port_link_state = mv88e6185_port_link_state,
3326	3769	.port_get_cmode = mv88e6185_port_get_cmode,
	3770	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3327	3771	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3328	3772	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3329	3773	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3340,6 +3784,7 @@
3340	3784	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3341	3785	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3342	3786	.phylink_validate = mv88e6185_phylink_validate,
	3787	+ .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3343	3788	};
3344	3789
3345	3790	static const struct mv88e6xxx_ops mv88e6190_ops = {
..	..	@@ -3352,18 +3797,21 @@
3352	3797	.phy_read = mv88e6xxx_g2_smi_phy_read,
3353	3798	.phy_write = mv88e6xxx_g2_smi_phy_write,
3354	3799	.port_set_link = mv88e6xxx_port_set_link,
3355		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3356	3800	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3357		- .port_set_speed = mv88e6390_port_set_speed,
	3801	+ .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
	3802	+ .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3358	3803	.port_tag_remap = mv88e6390_port_tag_remap,
	3804	+ .port_set_policy = mv88e6352_port_set_policy,
3359	3805	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3360	3806	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3361	3807	.port_set_ether_type = mv88e6351_port_set_ether_type,
	3808	+ .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3362	3809	.port_pause_limit = mv88e6390_port_pause_limit,
3363	3810	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3364	3811	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3365		- .port_link_state = mv88e6352_port_link_state,
3366	3812	.port_get_cmode = mv88e6352_port_get_cmode,
	3813	+ .port_set_cmode = mv88e6390_port_set_cmode,
	3814	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3367	3815	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3368	3816	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3369	3817	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
..	..	@@ -3376,11 +3824,24 @@
3376	3824	.pot_clear = mv88e6xxx_g2_pot_clear,
3377	3825	.reset = mv88e6352_g1_reset,
3378	3826	.rmu_disable = mv88e6390_g1_rmu_disable,
	3827	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3828	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3379	3829	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3380	3830	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3381	3831	.serdes_power = mv88e6390_serdes_power,
3382		- .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3383		- .serdes_irq_free = mv88e6390_serdes_irq_free,
	3832	+ .serdes_get_lane = mv88e6390_serdes_get_lane,
	3833	+ /* Check status register pause & lpa register */
	3834	+ .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
	3835	+ .serdes_pcs_config = mv88e6390_serdes_pcs_config,
	3836	+ .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
	3837	+ .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
	3838	+ .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
	3839	+ .serdes_irq_enable = mv88e6390_serdes_irq_enable,
	3840	+ .serdes_irq_status = mv88e6390_serdes_irq_status,
	3841	+ .serdes_get_strings = mv88e6390_serdes_get_strings,
	3842	+ .serdes_get_stats = mv88e6390_serdes_get_stats,
	3843	+ .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
	3844	+ .serdes_get_regs = mv88e6390_serdes_get_regs,
3384	3845	.gpio_ops = &mv88e6352_gpio_ops,
3385	3846	.phylink_validate = mv88e6390_phylink_validate,
3386	3847	};
..	..	@@ -3395,18 +3856,21 @@
3395	3856	.phy_read = mv88e6xxx_g2_smi_phy_read,
3396	3857	.phy_write = mv88e6xxx_g2_smi_phy_write,
3397	3858	.port_set_link = mv88e6xxx_port_set_link,
3398		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3399	3859	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3400		- .port_set_speed = mv88e6390x_port_set_speed,
	3860	+ .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
	3861	+ .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
3401	3862	.port_tag_remap = mv88e6390_port_tag_remap,
	3863	+ .port_set_policy = mv88e6352_port_set_policy,
3402	3864	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3403	3865	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3404	3866	.port_set_ether_type = mv88e6351_port_set_ether_type,
	3867	+ .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3405	3868	.port_pause_limit = mv88e6390_port_pause_limit,
3406	3869	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3407	3870	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3408		- .port_link_state = mv88e6352_port_link_state,
3409	3871	.port_get_cmode = mv88e6352_port_get_cmode,
	3872	+ .port_set_cmode = mv88e6390x_port_set_cmode,
	3873	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3410	3874	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3411	3875	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3412	3876	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
..	..	@@ -3419,11 +3883,24 @@
3419	3883	.pot_clear = mv88e6xxx_g2_pot_clear,
3420	3884	.reset = mv88e6352_g1_reset,
3421	3885	.rmu_disable = mv88e6390_g1_rmu_disable,
	3886	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3887	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3422	3888	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3423	3889	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3424		- .serdes_power = mv88e6390x_serdes_power,
3425		- .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3426		- .serdes_irq_free = mv88e6390_serdes_irq_free,
	3890	+ .serdes_power = mv88e6390_serdes_power,
	3891	+ .serdes_get_lane = mv88e6390x_serdes_get_lane,
	3892	+ /* Check status register pause & lpa register */
	3893	+ .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
	3894	+ .serdes_pcs_config = mv88e6390_serdes_pcs_config,
	3895	+ .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
	3896	+ .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
	3897	+ .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
	3898	+ .serdes_irq_enable = mv88e6390_serdes_irq_enable,
	3899	+ .serdes_irq_status = mv88e6390_serdes_irq_status,
	3900	+ .serdes_get_strings = mv88e6390_serdes_get_strings,
	3901	+ .serdes_get_stats = mv88e6390_serdes_get_stats,
	3902	+ .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
	3903	+ .serdes_get_regs = mv88e6390_serdes_get_regs,
3427	3904	.gpio_ops = &mv88e6352_gpio_ops,
3428	3905	.phylink_validate = mv88e6390x_phylink_validate,
3429	3906	};
..	..	@@ -3438,9 +3915,9 @@
3438	3915	.phy_read = mv88e6xxx_g2_smi_phy_read,
3439	3916	.phy_write = mv88e6xxx_g2_smi_phy_write,
3440	3917	.port_set_link = mv88e6xxx_port_set_link,
3441		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3442	3918	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3443		- .port_set_speed = mv88e6390_port_set_speed,
	3919	+ .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
	3920	+ .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3444	3921	.port_tag_remap = mv88e6390_port_tag_remap,
3445	3922	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3446	3923	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
..	..	@@ -3448,8 +3925,9 @@
3448	3925	.port_pause_limit = mv88e6390_port_pause_limit,
3449	3926	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3450	3927	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3451		- .port_link_state = mv88e6352_port_link_state,
3452	3928	.port_get_cmode = mv88e6352_port_get_cmode,
	3929	+ .port_set_cmode = mv88e6390_port_set_cmode,
	3930	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3453	3931	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3454	3932	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3455	3933	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
..	..	@@ -3462,11 +3940,24 @@
3462	3940	.pot_clear = mv88e6xxx_g2_pot_clear,
3463	3941	.reset = mv88e6352_g1_reset,
3464	3942	.rmu_disable = mv88e6390_g1_rmu_disable,
	3943	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3944	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3465	3945	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3466	3946	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3467	3947	.serdes_power = mv88e6390_serdes_power,
3468		- .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3469		- .serdes_irq_free = mv88e6390_serdes_irq_free,
	3948	+ .serdes_get_lane = mv88e6390_serdes_get_lane,
	3949	+ /* Check status register pause & lpa register */
	3950	+ .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
	3951	+ .serdes_pcs_config = mv88e6390_serdes_pcs_config,
	3952	+ .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
	3953	+ .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
	3954	+ .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
	3955	+ .serdes_irq_enable = mv88e6390_serdes_irq_enable,
	3956	+ .serdes_irq_status = mv88e6390_serdes_irq_status,
	3957	+ .serdes_get_strings = mv88e6390_serdes_get_strings,
	3958	+ .serdes_get_stats = mv88e6390_serdes_get_stats,
	3959	+ .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
	3960	+ .serdes_get_regs = mv88e6390_serdes_get_regs,
3470	3961	.avb_ops = &mv88e6390_avb_ops,
3471	3962	.ptp_ops = &mv88e6352_ptp_ops,
3472	3963	.phylink_validate = mv88e6390_phylink_validate,
..	..	@@ -3483,10 +3974,10 @@
3483	3974	.phy_read = mv88e6xxx_g2_smi_phy_read,
3484	3975	.phy_write = mv88e6xxx_g2_smi_phy_write,
3485	3976	.port_set_link = mv88e6xxx_port_set_link,
3486		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3487	3977	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3488		- .port_set_speed = mv88e6352_port_set_speed,
	3978	+ .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3489	3979	.port_tag_remap = mv88e6095_port_tag_remap,
	3980	+ .port_set_policy = mv88e6352_port_set_policy,
3490	3981	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3491	3982	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3492	3983	.port_set_ether_type = mv88e6351_port_set_ether_type,
..	..	@@ -3495,8 +3986,8 @@
3495	3986	.port_pause_limit = mv88e6097_port_pause_limit,
3496	3987	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3497	3988	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3498		- .port_link_state = mv88e6352_port_link_state,
3499	3989	.port_get_cmode = mv88e6352_port_get_cmode,
	3990	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3500	3991	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3501	3992	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3502	3993	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3509,13 +4000,63 @@
3509	4000	.pot_clear = mv88e6xxx_g2_pot_clear,
3510	4001	.reset = mv88e6352_g1_reset,
3511	4002	.rmu_disable = mv88e6352_g1_rmu_disable,
	4003	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	4004	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3512	4005	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3513	4006	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
	4007	+ .serdes_get_lane = mv88e6352_serdes_get_lane,
	4008	+ .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
	4009	+ .serdes_pcs_config = mv88e6352_serdes_pcs_config,
	4010	+ .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
	4011	+ .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3514	4012	.serdes_power = mv88e6352_serdes_power,
	4013	+ .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
	4014	+ .serdes_irq_enable = mv88e6352_serdes_irq_enable,
	4015	+ .serdes_irq_status = mv88e6352_serdes_irq_status,
	4016	+ .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
	4017	+ .serdes_get_regs = mv88e6352_serdes_get_regs,
3515	4018	.gpio_ops = &mv88e6352_gpio_ops,
3516	4019	.avb_ops = &mv88e6352_avb_ops,
3517	4020	.ptp_ops = &mv88e6352_ptp_ops,
3518	4021	.phylink_validate = mv88e6352_phylink_validate,
	4022	+};
	4023	+
	4024	+static const struct mv88e6xxx_ops mv88e6250_ops = {
	4025	+ /* MV88E6XXX_FAMILY_6250 */
	4026	+ .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
	4027	+ .ip_pri_map = mv88e6085_g1_ip_pri_map,
	4028	+ .irl_init_all = mv88e6352_g2_irl_init_all,
	4029	+ .get_eeprom = mv88e6xxx_g2_get_eeprom16,
	4030	+ .set_eeprom = mv88e6xxx_g2_set_eeprom16,
	4031	+ .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	4032	+ .phy_read = mv88e6xxx_g2_smi_phy_read,
	4033	+ .phy_write = mv88e6xxx_g2_smi_phy_write,
	4034	+ .port_set_link = mv88e6xxx_port_set_link,
	4035	+ .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
	4036	+ .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
	4037	+ .port_tag_remap = mv88e6095_port_tag_remap,
	4038	+ .port_set_frame_mode = mv88e6351_port_set_frame_mode,
	4039	+ .port_set_egress_floods = mv88e6352_port_set_egress_floods,
	4040	+ .port_set_ether_type = mv88e6351_port_set_ether_type,
	4041	+ .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
	4042	+ .port_pause_limit = mv88e6097_port_pause_limit,
	4043	+ .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	4044	+ .stats_snapshot = mv88e6320_g1_stats_snapshot,
	4045	+ .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
	4046	+ .stats_get_sset_count = mv88e6250_stats_get_sset_count,
	4047	+ .stats_get_strings = mv88e6250_stats_get_strings,
	4048	+ .stats_get_stats = mv88e6250_stats_get_stats,
	4049	+ .set_cpu_port = mv88e6095_g1_set_cpu_port,
	4050	+ .set_egress_port = mv88e6095_g1_set_egress_port,
	4051	+ .watchdog_ops = &mv88e6250_watchdog_ops,
	4052	+ .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
	4053	+ .pot_clear = mv88e6xxx_g2_pot_clear,
	4054	+ .reset = mv88e6250_g1_reset,
	4055	+ .vtu_getnext = mv88e6250_g1_vtu_getnext,
	4056	+ .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge,
	4057	+ .avb_ops = &mv88e6352_avb_ops,
	4058	+ .ptp_ops = &mv88e6250_ptp_ops,
	4059	+ .phylink_validate = mv88e6065_phylink_validate,
3519	4060	};
3520	4061
3521	4062	static const struct mv88e6xxx_ops mv88e6290_ops = {
..	..	@@ -3528,19 +4069,20 @@
3528	4069	.phy_read = mv88e6xxx_g2_smi_phy_read,
3529	4070	.phy_write = mv88e6xxx_g2_smi_phy_write,
3530	4071	.port_set_link = mv88e6xxx_port_set_link,
3531		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3532	4072	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3533		- .port_set_speed = mv88e6390_port_set_speed,
	4073	+ .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
	4074	+ .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3534	4075	.port_tag_remap = mv88e6390_port_tag_remap,
	4076	+ .port_set_policy = mv88e6352_port_set_policy,
3535	4077	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3536	4078	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3537	4079	.port_set_ether_type = mv88e6351_port_set_ether_type,
3538	4080	.port_pause_limit = mv88e6390_port_pause_limit,
3539		- .port_set_cmode = mv88e6390x_port_set_cmode,
3540	4081	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3541	4082	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3542		- .port_link_state = mv88e6352_port_link_state,
3543	4083	.port_get_cmode = mv88e6352_port_get_cmode,
	4084	+ .port_set_cmode = mv88e6390_port_set_cmode,
	4085	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3544	4086	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3545	4087	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3546	4088	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
..	..	@@ -3553,11 +4095,24 @@
3553	4095	.pot_clear = mv88e6xxx_g2_pot_clear,
3554	4096	.reset = mv88e6352_g1_reset,
3555	4097	.rmu_disable = mv88e6390_g1_rmu_disable,
	4098	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	4099	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3556	4100	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3557	4101	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3558	4102	.serdes_power = mv88e6390_serdes_power,
3559		- .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3560		- .serdes_irq_free = mv88e6390_serdes_irq_free,
	4103	+ .serdes_get_lane = mv88e6390_serdes_get_lane,
	4104	+ /* Check status register pause & lpa register */
	4105	+ .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
	4106	+ .serdes_pcs_config = mv88e6390_serdes_pcs_config,
	4107	+ .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
	4108	+ .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
	4109	+ .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
	4110	+ .serdes_irq_enable = mv88e6390_serdes_irq_enable,
	4111	+ .serdes_irq_status = mv88e6390_serdes_irq_status,
	4112	+ .serdes_get_strings = mv88e6390_serdes_get_strings,
	4113	+ .serdes_get_stats = mv88e6390_serdes_get_stats,
	4114	+ .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
	4115	+ .serdes_get_regs = mv88e6390_serdes_get_regs,
3561	4116	.gpio_ops = &mv88e6352_gpio_ops,
3562	4117	.avb_ops = &mv88e6390_avb_ops,
3563	4118	.ptp_ops = &mv88e6352_ptp_ops,
..	..	@@ -3575,8 +4130,7 @@
3575	4130	.phy_read = mv88e6xxx_g2_smi_phy_read,
3576	4131	.phy_write = mv88e6xxx_g2_smi_phy_write,
3577	4132	.port_set_link = mv88e6xxx_port_set_link,
3578		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3579		- .port_set_speed = mv88e6185_port_set_speed,
	4133	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3580	4134	.port_tag_remap = mv88e6095_port_tag_remap,
3581	4135	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3582	4136	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
..	..	@@ -3586,8 +4140,8 @@
3586	4140	.port_pause_limit = mv88e6097_port_pause_limit,
3587	4141	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3588	4142	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3589		- .port_link_state = mv88e6352_port_link_state,
3590	4143	.port_get_cmode = mv88e6352_port_get_cmode,
	4144	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3591	4145	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3592	4146	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3593	4147	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
..	..	@@ -3595,6 +4149,7 @@
3595	4149	.stats_get_stats = mv88e6320_stats_get_stats,
3596	4150	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3597	4151	.set_egress_port = mv88e6095_g1_set_egress_port,
	4152	+ .watchdog_ops = &mv88e6390_watchdog_ops,
3598	4153	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3599	4154	.pot_clear = mv88e6xxx_g2_pot_clear,
3600	4155	.reset = mv88e6352_g1_reset,
..	..	@@ -3617,8 +4172,7 @@
3617	4172	.phy_read = mv88e6xxx_g2_smi_phy_read,
3618	4173	.phy_write = mv88e6xxx_g2_smi_phy_write,
3619	4174	.port_set_link = mv88e6xxx_port_set_link,
3620		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3621		- .port_set_speed = mv88e6185_port_set_speed,
	4175	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3622	4176	.port_tag_remap = mv88e6095_port_tag_remap,
3623	4177	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3624	4178	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
..	..	@@ -3628,8 +4182,8 @@
3628	4182	.port_pause_limit = mv88e6097_port_pause_limit,
3629	4183	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3630	4184	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3631		- .port_link_state = mv88e6352_port_link_state,
3632	4185	.port_get_cmode = mv88e6352_port_get_cmode,
	4186	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3633	4187	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3634	4188	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3635	4189	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
..	..	@@ -3637,6 +4191,8 @@
3637	4191	.stats_get_stats = mv88e6320_stats_get_stats,
3638	4192	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3639	4193	.set_egress_port = mv88e6095_g1_set_egress_port,
	4194	+ .watchdog_ops = &mv88e6390_watchdog_ops,
	4195	+ .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3640	4196	.reset = mv88e6352_g1_reset,
3641	4197	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3642	4198	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
..	..	@@ -3657,9 +4213,9 @@
3657	4213	.phy_read = mv88e6xxx_g2_smi_phy_read,
3658	4214	.phy_write = mv88e6xxx_g2_smi_phy_write,
3659	4215	.port_set_link = mv88e6xxx_port_set_link,
3660		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3661	4216	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3662		- .port_set_speed = mv88e6341_port_set_speed,
	4217	+ .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
	4218	+ .port_max_speed_mode = mv88e6341_port_max_speed_mode,
3663	4219	.port_tag_remap = mv88e6095_port_tag_remap,
3664	4220	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3665	4221	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
..	..	@@ -3669,8 +4225,9 @@
3669	4225	.port_pause_limit = mv88e6097_port_pause_limit,
3670	4226	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3671	4227	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3672		- .port_link_state = mv88e6352_port_link_state,
3673	4228	.port_get_cmode = mv88e6352_port_get_cmode,
	4229	+ .port_set_cmode = mv88e6341_port_set_cmode,
	4230	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3674	4231	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3675	4232	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3676	4233	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
..	..	@@ -3683,13 +4240,29 @@
3683	4240	.pot_clear = mv88e6xxx_g2_pot_clear,
3684	4241	.reset = mv88e6352_g1_reset,
3685	4242	.rmu_disable = mv88e6390_g1_rmu_disable,
	4243	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	4244	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3686	4245	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3687	4246	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3688		- .serdes_power = mv88e6341_serdes_power,
	4247	+ .serdes_power = mv88e6390_serdes_power,
	4248	+ .serdes_get_lane = mv88e6341_serdes_get_lane,
	4249	+ /* Check status register pause & lpa register */
	4250	+ .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
	4251	+ .serdes_pcs_config = mv88e6390_serdes_pcs_config,
	4252	+ .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
	4253	+ .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
	4254	+ .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
	4255	+ .serdes_irq_enable = mv88e6390_serdes_irq_enable,
	4256	+ .serdes_irq_status = mv88e6390_serdes_irq_status,
3689	4257	.gpio_ops = &mv88e6352_gpio_ops,
3690	4258	.avb_ops = &mv88e6390_avb_ops,
3691	4259	.ptp_ops = &mv88e6352_ptp_ops,
3692		- .phylink_validate = mv88e6390_phylink_validate,
	4260	+ .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
	4261	+ .serdes_get_strings = mv88e6390_serdes_get_strings,
	4262	+ .serdes_get_stats = mv88e6390_serdes_get_stats,
	4263	+ .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
	4264	+ .serdes_get_regs = mv88e6390_serdes_get_regs,
	4265	+ .phylink_validate = mv88e6341_phylink_validate,
3693	4266	};
3694	4267
3695	4268	static const struct mv88e6xxx_ops mv88e6350_ops = {
..	..	@@ -3701,9 +4274,8 @@
3701	4274	.phy_read = mv88e6xxx_g2_smi_phy_read,
3702	4275	.phy_write = mv88e6xxx_g2_smi_phy_write,
3703	4276	.port_set_link = mv88e6xxx_port_set_link,
3704		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3705	4277	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3706		- .port_set_speed = mv88e6185_port_set_speed,
	4278	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3707	4279	.port_tag_remap = mv88e6095_port_tag_remap,
3708	4280	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3709	4281	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
..	..	@@ -3713,8 +4285,8 @@
3713	4285	.port_pause_limit = mv88e6097_port_pause_limit,
3714	4286	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3715	4287	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3716		- .port_link_state = mv88e6352_port_link_state,
3717	4288	.port_get_cmode = mv88e6352_port_get_cmode,
	4289	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3718	4290	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3719	4291	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3720	4292	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3726,6 +4298,8 @@
3726	4298	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3727	4299	.pot_clear = mv88e6xxx_g2_pot_clear,
3728	4300	.reset = mv88e6352_g1_reset,
	4301	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	4302	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3729	4303	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3730	4304	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3731	4305	.phylink_validate = mv88e6185_phylink_validate,
..	..	@@ -3740,10 +4314,10 @@
3740	4314	.phy_read = mv88e6xxx_g2_smi_phy_read,
3741	4315	.phy_write = mv88e6xxx_g2_smi_phy_write,
3742	4316	.port_set_link = mv88e6xxx_port_set_link,
3743		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3744	4317	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3745		- .port_set_speed = mv88e6185_port_set_speed,
	4318	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3746	4319	.port_tag_remap = mv88e6095_port_tag_remap,
	4320	+ .port_set_policy = mv88e6352_port_set_policy,
3747	4321	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3748	4322	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3749	4323	.port_set_ether_type = mv88e6351_port_set_ether_type,
..	..	@@ -3752,8 +4326,8 @@
3752	4326	.port_pause_limit = mv88e6097_port_pause_limit,
3753	4327	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3754	4328	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3755		- .port_link_state = mv88e6352_port_link_state,
3756	4329	.port_get_cmode = mv88e6352_port_get_cmode,
	4330	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3757	4331	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3758	4332	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3759	4333	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3765,7 +4339,8 @@
3765	4339	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3766	4340	.pot_clear = mv88e6xxx_g2_pot_clear,
3767	4341	.reset = mv88e6352_g1_reset,
3768		- .rmu_disable = mv88e6390_g1_rmu_disable,
	4342	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	4343	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3769	4344	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3770	4345	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3771	4346	.avb_ops = &mv88e6352_avb_ops,
..	..	@@ -3784,10 +4359,10 @@
3784	4359	.phy_read = mv88e6xxx_g2_smi_phy_read,
3785	4360	.phy_write = mv88e6xxx_g2_smi_phy_write,
3786	4361	.port_set_link = mv88e6xxx_port_set_link,
3787		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3788	4362	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3789		- .port_set_speed = mv88e6352_port_set_speed,
	4363	+ .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3790	4364	.port_tag_remap = mv88e6095_port_tag_remap,
	4365	+ .port_set_policy = mv88e6352_port_set_policy,
3791	4366	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3792	4367	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3793	4368	.port_set_ether_type = mv88e6351_port_set_ether_type,
..	..	@@ -3796,8 +4371,8 @@
3796	4371	.port_pause_limit = mv88e6097_port_pause_limit,
3797	4372	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3798	4373	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3799		- .port_link_state = mv88e6352_port_link_state,
3800	4374	.port_get_cmode = mv88e6352_port_get_cmode,
	4375	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3801	4376	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3802	4377	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3803	4378	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3810,15 +4385,27 @@
3810	4385	.pot_clear = mv88e6xxx_g2_pot_clear,
3811	4386	.reset = mv88e6352_g1_reset,
3812	4387	.rmu_disable = mv88e6352_g1_rmu_disable,
	4388	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	4389	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3813	4390	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3814	4391	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
	4392	+ .serdes_get_lane = mv88e6352_serdes_get_lane,
	4393	+ .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
	4394	+ .serdes_pcs_config = mv88e6352_serdes_pcs_config,
	4395	+ .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
	4396	+ .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3815	4397	.serdes_power = mv88e6352_serdes_power,
	4398	+ .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
	4399	+ .serdes_irq_enable = mv88e6352_serdes_irq_enable,
	4400	+ .serdes_irq_status = mv88e6352_serdes_irq_status,
3816	4401	.gpio_ops = &mv88e6352_gpio_ops,
3817	4402	.avb_ops = &mv88e6352_avb_ops,
3818	4403	.ptp_ops = &mv88e6352_ptp_ops,
3819	4404	.serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
3820	4405	.serdes_get_strings = mv88e6352_serdes_get_strings,
3821	4406	.serdes_get_stats = mv88e6352_serdes_get_stats,
	4407	+ .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
	4408	+ .serdes_get_regs = mv88e6352_serdes_get_regs,
3822	4409	.phylink_validate = mv88e6352_phylink_validate,
3823	4410	};
3824	4411
..	..	@@ -3832,21 +4419,22 @@
3832	4419	.phy_read = mv88e6xxx_g2_smi_phy_read,
3833	4420	.phy_write = mv88e6xxx_g2_smi_phy_write,
3834	4421	.port_set_link = mv88e6xxx_port_set_link,
3835		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3836	4422	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3837		- .port_set_speed = mv88e6390_port_set_speed,
	4423	+ .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
	4424	+ .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3838	4425	.port_tag_remap = mv88e6390_port_tag_remap,
	4426	+ .port_set_policy = mv88e6352_port_set_policy,
3839	4427	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3840	4428	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3841	4429	.port_set_ether_type = mv88e6351_port_set_ether_type,
3842	4430	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3843	4431	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3844	4432	.port_pause_limit = mv88e6390_port_pause_limit,
3845		- .port_set_cmode = mv88e6390x_port_set_cmode,
3846	4433	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3847	4434	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3848		- .port_link_state = mv88e6352_port_link_state,
3849	4435	.port_get_cmode = mv88e6352_port_get_cmode,
	4436	+ .port_set_cmode = mv88e6390_port_set_cmode,
	4437	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3850	4438	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3851	4439	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3852	4440	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
..	..	@@ -3859,14 +4447,28 @@
3859	4447	.pot_clear = mv88e6xxx_g2_pot_clear,
3860	4448	.reset = mv88e6352_g1_reset,
3861	4449	.rmu_disable = mv88e6390_g1_rmu_disable,
	4450	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	4451	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3862	4452	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3863	4453	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3864	4454	.serdes_power = mv88e6390_serdes_power,
3865		- .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3866		- .serdes_irq_free = mv88e6390_serdes_irq_free,
	4455	+ .serdes_get_lane = mv88e6390_serdes_get_lane,
	4456	+ /* Check status register pause & lpa register */
	4457	+ .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
	4458	+ .serdes_pcs_config = mv88e6390_serdes_pcs_config,
	4459	+ .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
	4460	+ .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
	4461	+ .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
	4462	+ .serdes_irq_enable = mv88e6390_serdes_irq_enable,
	4463	+ .serdes_irq_status = mv88e6390_serdes_irq_status,
3867	4464	.gpio_ops = &mv88e6352_gpio_ops,
3868	4465	.avb_ops = &mv88e6390_avb_ops,
3869	4466	.ptp_ops = &mv88e6352_ptp_ops,
	4467	+ .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
	4468	+ .serdes_get_strings = mv88e6390_serdes_get_strings,
	4469	+ .serdes_get_stats = mv88e6390_serdes_get_stats,
	4470	+ .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
	4471	+ .serdes_get_regs = mv88e6390_serdes_get_regs,
3870	4472	.phylink_validate = mv88e6390_phylink_validate,
3871	4473	};
3872	4474
..	..	@@ -3880,21 +4482,22 @@
3880	4482	.phy_read = mv88e6xxx_g2_smi_phy_read,
3881	4483	.phy_write = mv88e6xxx_g2_smi_phy_write,
3882	4484	.port_set_link = mv88e6xxx_port_set_link,
3883		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3884	4485	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3885		- .port_set_speed = mv88e6390x_port_set_speed,
	4486	+ .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
	4487	+ .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
3886	4488	.port_tag_remap = mv88e6390_port_tag_remap,
	4489	+ .port_set_policy = mv88e6352_port_set_policy,
3887	4490	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3888	4491	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3889	4492	.port_set_ether_type = mv88e6351_port_set_ether_type,
3890	4493	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3891	4494	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3892	4495	.port_pause_limit = mv88e6390_port_pause_limit,
3893		- .port_set_cmode = mv88e6390x_port_set_cmode,
3894	4496	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3895	4497	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3896		- .port_link_state = mv88e6352_port_link_state,
3897	4498	.port_get_cmode = mv88e6352_port_get_cmode,
	4499	+ .port_set_cmode = mv88e6390x_port_set_cmode,
	4500	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3898	4501	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3899	4502	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3900	4503	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
..	..	@@ -3907,11 +4510,24 @@
3907	4510	.pot_clear = mv88e6xxx_g2_pot_clear,
3908	4511	.reset = mv88e6352_g1_reset,
3909	4512	.rmu_disable = mv88e6390_g1_rmu_disable,
	4513	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	4514	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3910	4515	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3911	4516	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3912		- .serdes_power = mv88e6390x_serdes_power,
3913		- .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3914		- .serdes_irq_free = mv88e6390_serdes_irq_free,
	4517	+ .serdes_power = mv88e6390_serdes_power,
	4518	+ .serdes_get_lane = mv88e6390x_serdes_get_lane,
	4519	+ .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
	4520	+ .serdes_pcs_config = mv88e6390_serdes_pcs_config,
	4521	+ .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
	4522	+ .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
	4523	+ .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
	4524	+ .serdes_irq_enable = mv88e6390_serdes_irq_enable,
	4525	+ .serdes_irq_status = mv88e6390_serdes_irq_status,
	4526	+ .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
	4527	+ .serdes_get_strings = mv88e6390_serdes_get_strings,
	4528	+ .serdes_get_stats = mv88e6390_serdes_get_stats,
	4529	+ .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
	4530	+ .serdes_get_regs = mv88e6390_serdes_get_regs,
3915	4531	.gpio_ops = &mv88e6352_gpio_ops,
3916	4532	.avb_ops = &mv88e6390_avb_ops,
3917	4533	.ptp_ops = &mv88e6352_ptp_ops,
..	..	@@ -3924,6 +4540,7 @@
3924	4540	.family = MV88E6XXX_FAMILY_6097,
3925	4541	.name = "Marvell 88E6085",
3926	4542	.num_databases = 4096,
	4543	+ .num_macs = 8192,
3927	4544	.num_ports = 10,
3928	4545	.num_internal_phys = 5,
3929	4546	.max_vid = 4095,
..	..	@@ -3946,6 +4563,7 @@
3946	4563	.family = MV88E6XXX_FAMILY_6095,
3947	4564	.name = "Marvell 88E6095/88E6095F",
3948	4565	.num_databases = 256,
	4566	+ .num_macs = 8192,
3949	4567	.num_ports = 11,
3950	4568	.num_internal_phys = 0,
3951	4569	.max_vid = 4095,
..	..	@@ -3966,6 +4584,7 @@
3966	4584	.family = MV88E6XXX_FAMILY_6097,
3967	4585	.name = "Marvell 88E6097/88E6097F",
3968	4586	.num_databases = 4096,
	4587	+ .num_macs = 8192,
3969	4588	.num_ports = 11,
3970	4589	.num_internal_phys = 8,
3971	4590	.max_vid = 4095,
..	..	@@ -3988,6 +4607,7 @@
3988	4607	.family = MV88E6XXX_FAMILY_6165,
3989	4608	.name = "Marvell 88E6123",
3990	4609	.num_databases = 4096,
	4610	+ .num_macs = 1024,
3991	4611	.num_ports = 3,
3992	4612	.num_internal_phys = 5,
3993	4613	.max_vid = 4095,
..	..	@@ -4010,6 +4630,7 @@
4010	4630	.family = MV88E6XXX_FAMILY_6185,
4011	4631	.name = "Marvell 88E6131",
4012	4632	.num_databases = 256,
	4633	+ .num_macs = 8192,
4013	4634	.num_ports = 8,
4014	4635	.num_internal_phys = 0,
4015	4636	.max_vid = 4095,
..	..	@@ -4030,6 +4651,7 @@
4030	4651	.family = MV88E6XXX_FAMILY_6341,
4031	4652	.name = "Marvell 88E6141",
4032	4653	.num_databases = 4096,
	4654	+ .num_macs = 2048,
4033	4655	.num_ports = 6,
4034	4656	.num_internal_phys = 5,
4035	4657	.num_gpio = 11,
..	..	@@ -4053,6 +4675,7 @@
4053	4675	.family = MV88E6XXX_FAMILY_6165,
4054	4676	.name = "Marvell 88E6161",
4055	4677	.num_databases = 4096,
	4678	+ .num_macs = 1024,
4056	4679	.num_ports = 6,
4057	4680	.num_internal_phys = 5,
4058	4681	.max_vid = 4095,
..	..	@@ -4076,6 +4699,7 @@
4076	4699	.family = MV88E6XXX_FAMILY_6165,
4077	4700	.name = "Marvell 88E6165",
4078	4701	.num_databases = 4096,
	4702	+ .num_macs = 8192,
4079	4703	.num_ports = 6,
4080	4704	.num_internal_phys = 0,
4081	4705	.max_vid = 4095,
..	..	@@ -4099,6 +4723,7 @@
4099	4723	.family = MV88E6XXX_FAMILY_6351,
4100	4724	.name = "Marvell 88E6171",
4101	4725	.num_databases = 4096,
	4726	+ .num_macs = 8192,
4102	4727	.num_ports = 7,
4103	4728	.num_internal_phys = 5,
4104	4729	.max_vid = 4095,
..	..	@@ -4121,6 +4746,7 @@
4121	4746	.family = MV88E6XXX_FAMILY_6352,
4122	4747	.name = "Marvell 88E6172",
4123	4748	.num_databases = 4096,
	4749	+ .num_macs = 8192,
4124	4750	.num_ports = 7,
4125	4751	.num_internal_phys = 5,
4126	4752	.num_gpio = 15,
..	..	@@ -4144,6 +4770,7 @@
4144	4770	.family = MV88E6XXX_FAMILY_6351,
4145	4771	.name = "Marvell 88E6175",
4146	4772	.num_databases = 4096,
	4773	+ .num_macs = 8192,
4147	4774	.num_ports = 7,
4148	4775	.num_internal_phys = 5,
4149	4776	.max_vid = 4095,
..	..	@@ -4166,6 +4793,7 @@
4166	4793	.family = MV88E6XXX_FAMILY_6352,
4167	4794	.name = "Marvell 88E6176",
4168	4795	.num_databases = 4096,
	4796	+ .num_macs = 8192,
4169	4797	.num_ports = 7,
4170	4798	.num_internal_phys = 5,
4171	4799	.num_gpio = 15,
..	..	@@ -4189,6 +4817,7 @@
4189	4817	.family = MV88E6XXX_FAMILY_6185,
4190	4818	.name = "Marvell 88E6185",
4191	4819	.num_databases = 256,
	4820	+ .num_macs = 8192,
4192	4821	.num_ports = 10,
4193	4822	.num_internal_phys = 0,
4194	4823	.max_vid = 4095,
..	..	@@ -4209,6 +4838,7 @@
4209	4838	.family = MV88E6XXX_FAMILY_6390,
4210	4839	.name = "Marvell 88E6190",
4211	4840	.num_databases = 4096,
	4841	+ .num_macs = 16384,
4212	4842	.num_ports = 11, /* 10 + Z80 */
4213	4843	.num_internal_phys = 9,
4214	4844	.num_gpio = 16,
..	..	@@ -4232,6 +4862,7 @@
4232	4862	.family = MV88E6XXX_FAMILY_6390,
4233	4863	.name = "Marvell 88E6190X",
4234	4864	.num_databases = 4096,
	4865	+ .num_macs = 16384,
4235	4866	.num_ports = 11, /* 10 + Z80 */
4236	4867	.num_internal_phys = 9,
4237	4868	.num_gpio = 16,
..	..	@@ -4255,6 +4886,7 @@
4255	4886	.family = MV88E6XXX_FAMILY_6390,
4256	4887	.name = "Marvell 88E6191",
4257	4888	.num_databases = 4096,
	4889	+ .num_macs = 16384,
4258	4890	.num_ports = 11, /* 10 + Z80 */
4259	4891	.num_internal_phys = 9,
4260	4892	.max_vid = 8191,
..	..	@@ -4273,11 +4905,39 @@
4273	4905	.ops = &mv88e6191_ops,
4274	4906	},
4275	4907
	4908	+ [MV88E6220] = {
	4909	+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
	4910	+ .family = MV88E6XXX_FAMILY_6250,
	4911	+ .name = "Marvell 88E6220",
	4912	+ .num_databases = 64,
	4913	+
	4914	+ /* Ports 2-4 are not routed to pins
	4915	+ * => usable ports 0, 1, 5, 6
	4916	+ */
	4917	+ .num_ports = 7,
	4918	+ .num_internal_phys = 2,
	4919	+ .invalid_port_mask = BIT(2) \| BIT(3) \| BIT(4),
	4920	+ .max_vid = 4095,
	4921	+ .port_base_addr = 0x08,
	4922	+ .phy_base_addr = 0x00,
	4923	+ .global1_addr = 0x0f,
	4924	+ .global2_addr = 0x07,
	4925	+ .age_time_coeff = 15000,
	4926	+ .g1_irqs = 9,
	4927	+ .g2_irqs = 10,
	4928	+ .atu_move_port_mask = 0xf,
	4929	+ .dual_chip = true,
	4930	+ .tag_protocol = DSA_TAG_PROTO_DSA,
	4931	+ .ptp_support = true,
	4932	+ .ops = &mv88e6250_ops,
	4933	+ },
	4934	+
4276	4935	[MV88E6240] = {
4277	4936	.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
4278	4937	.family = MV88E6XXX_FAMILY_6352,
4279	4938	.name = "Marvell 88E6240",
4280	4939	.num_databases = 4096,
	4940	+ .num_macs = 8192,
4281	4941	.num_ports = 7,
4282	4942	.num_internal_phys = 5,
4283	4943	.num_gpio = 15,
..	..	@@ -4295,6 +4955,28 @@
4295	4955	.tag_protocol = DSA_TAG_PROTO_EDSA,
4296	4956	.ptp_support = true,
4297	4957	.ops = &mv88e6240_ops,
	4958	+ },
	4959	+
	4960	+ [MV88E6250] = {
	4961	+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
	4962	+ .family = MV88E6XXX_FAMILY_6250,
	4963	+ .name = "Marvell 88E6250",
	4964	+ .num_databases = 64,
	4965	+ .num_ports = 7,
	4966	+ .num_internal_phys = 5,
	4967	+ .max_vid = 4095,
	4968	+ .port_base_addr = 0x08,
	4969	+ .phy_base_addr = 0x00,
	4970	+ .global1_addr = 0x0f,
	4971	+ .global2_addr = 0x07,
	4972	+ .age_time_coeff = 15000,
	4973	+ .g1_irqs = 9,
	4974	+ .g2_irqs = 10,
	4975	+ .atu_move_port_mask = 0xf,
	4976	+ .dual_chip = true,
	4977	+ .tag_protocol = DSA_TAG_PROTO_DSA,
	4978	+ .ptp_support = true,
	4979	+ .ops = &mv88e6250_ops,
4298	4980	},
4299	4981
4300	4982	[MV88E6290] = {
..	..	@@ -4326,6 +5008,7 @@
4326	5008	.family = MV88E6XXX_FAMILY_6320,
4327	5009	.name = "Marvell 88E6320",
4328	5010	.num_databases = 4096,
	5011	+ .num_macs = 8192,
4329	5012	.num_ports = 7,
4330	5013	.num_internal_phys = 5,
4331	5014	.num_gpio = 15,
..	..	@@ -4350,6 +5033,7 @@
4350	5033	.family = MV88E6XXX_FAMILY_6320,
4351	5034	.name = "Marvell 88E6321",
4352	5035	.num_databases = 4096,
	5036	+ .num_macs = 8192,
4353	5037	.num_ports = 7,
4354	5038	.num_internal_phys = 5,
4355	5039	.num_gpio = 15,
..	..	@@ -4373,6 +5057,7 @@
4373	5057	.family = MV88E6XXX_FAMILY_6341,
4374	5058	.name = "Marvell 88E6341",
4375	5059	.num_databases = 4096,
	5060	+ .num_macs = 2048,
4376	5061	.num_internal_phys = 5,
4377	5062	.num_ports = 6,
4378	5063	.num_gpio = 11,
..	..	@@ -4397,6 +5082,7 @@
4397	5082	.family = MV88E6XXX_FAMILY_6351,
4398	5083	.name = "Marvell 88E6350",
4399	5084	.num_databases = 4096,
	5085	+ .num_macs = 8192,
4400	5086	.num_ports = 7,
4401	5087	.num_internal_phys = 5,
4402	5088	.max_vid = 4095,
..	..	@@ -4419,6 +5105,7 @@
4419	5105	.family = MV88E6XXX_FAMILY_6351,
4420	5106	.name = "Marvell 88E6351",
4421	5107	.num_databases = 4096,
	5108	+ .num_macs = 8192,
4422	5109	.num_ports = 7,
4423	5110	.num_internal_phys = 5,
4424	5111	.max_vid = 4095,
..	..	@@ -4441,6 +5128,7 @@
4441	5128	.family = MV88E6XXX_FAMILY_6352,
4442	5129	.name = "Marvell 88E6352",
4443	5130	.num_databases = 4096,
	5131	+ .num_macs = 8192,
4444	5132	.num_ports = 7,
4445	5133	.num_internal_phys = 5,
4446	5134	.num_gpio = 15,
..	..	@@ -4464,6 +5152,7 @@
4464	5152	.family = MV88E6XXX_FAMILY_6390,
4465	5153	.name = "Marvell 88E6390",
4466	5154	.num_databases = 4096,
	5155	+ .num_macs = 16384,
4467	5156	.num_ports = 11, /* 10 + Z80 */
4468	5157	.num_internal_phys = 9,
4469	5158	.num_gpio = 16,
..	..	@@ -4487,6 +5176,7 @@
4487	5176	.family = MV88E6XXX_FAMILY_6390,
4488	5177	.name = "Marvell 88E6390X",
4489	5178	.num_databases = 4096,
	5179	+ .num_macs = 16384,
4490	5180	.num_ports = 11, /* 10 + Z80 */
4491	5181	.num_internal_phys = 9,
4492	5182	.num_gpio = 16,
..	..	@@ -4525,9 +5215,9 @@
4525	5215	u16 id;
4526	5216	int err;
4527	5217
4528		- mutex_lock(&chip->reg_lock);
	5218	+ mv88e6xxx_reg_lock(chip);
4529	5219	err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
4530		- mutex_unlock(&chip->reg_lock);
	5220	+ mv88e6xxx_reg_unlock(chip);
4531	5221	if (err)
4532	5222	return err;
4533	5223
..	..	@@ -4563,93 +5253,19 @@
4563	5253
4564	5254	mutex_init(&chip->reg_lock);
4565	5255	INIT_LIST_HEAD(&chip->mdios);
	5256	+ idr_init(&chip->policies);
4566	5257
4567	5258	return chip;
4568	5259	}
4569	5260
4570		-static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4571		- struct mii_bus *bus, int sw_addr)
4572		-{
4573		- if (sw_addr == 0)
4574		- chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
4575		- else if (chip->info->multi_chip)
4576		- chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
4577		- else
4578		- return -EINVAL;
4579		-
4580		- chip->bus = bus;
4581		- chip->sw_addr = sw_addr;
4582		-
4583		- return 0;
4584		-}
4585		-
4586		-static void mv88e6xxx_ports_cmode_init(struct mv88e6xxx_chip *chip)
4587		-{
4588		- int i;
4589		-
4590		- for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
4591		- chip->ports[i].cmode = MV88E6XXX_PORT_STS_CMODE_INVALID;
4592		-}
4593		-
4594	5261	static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
4595		- int port)
	5262	+ int port,
	5263	+ enum dsa_tag_protocol m)
4596	5264	{
4597	5265	struct mv88e6xxx_chip *chip = ds->priv;
4598	5266
4599	5267	return chip->info->tag_protocol;
4600	5268	}
4601		-
4602		-#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4603		-static const char mv88e6xxx_drv_probe(struct device dsa_dev,
4604		- struct device *host_dev, int sw_addr,
4605		- void **priv)
4606		-{
4607		- struct mv88e6xxx_chip *chip;
4608		- struct mii_bus *bus;
4609		- int err;
4610		-
4611		- bus = dsa_host_dev_to_mii_bus(host_dev);
4612		- if (!bus)
4613		- return NULL;
4614		-
4615		- chip = mv88e6xxx_alloc_chip(dsa_dev);
4616		- if (!chip)
4617		- return NULL;
4618		-
4619		- /* Legacy SMI probing will only support chips similar to 88E6085 */
4620		- chip->info = &mv88e6xxx_table[MV88E6085];
4621		-
4622		- err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4623		- if (err)
4624		- goto free;
4625		-
4626		- err = mv88e6xxx_detect(chip);
4627		- if (err)
4628		- goto free;
4629		-
4630		- mv88e6xxx_ports_cmode_init(chip);
4631		-
4632		- mutex_lock(&chip->reg_lock);
4633		- err = mv88e6xxx_switch_reset(chip);
4634		- mutex_unlock(&chip->reg_lock);
4635		- if (err)
4636		- goto free;
4637		-
4638		- mv88e6xxx_phy_init(chip);
4639		-
4640		- err = mv88e6xxx_mdios_register(chip, NULL);
4641		- if (err)
4642		- goto free;
4643		-
4644		- *priv = chip;
4645		-
4646		- return chip->info->name;
4647		-free:
4648		- devm_kfree(dsa_dev, chip);
4649		-
4650		- return NULL;
4651		-}
4652		-#endif
4653	5269
4654	5270	static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4655	5271	const struct switchdev_obj_port_mdb *mdb)
..	..	@@ -4666,12 +5282,12 @@
4666	5282	{
4667	5283	struct mv88e6xxx_chip *chip = ds->priv;
4668	5284
4669		- mutex_lock(&chip->reg_lock);
	5285	+ mv88e6xxx_reg_lock(chip);
4670	5286	if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4671	5287	MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
4672	5288	dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
4673	5289	port);
4674		- mutex_unlock(&chip->reg_lock);
	5290	+ mv88e6xxx_reg_unlock(chip);
4675	5291	}
4676	5292
4677	5293	static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
..	..	@@ -4680,24 +5296,111 @@
4680	5296	struct mv88e6xxx_chip *chip = ds->priv;
4681	5297	int err;
4682	5298
	5299	+ mv88e6xxx_reg_lock(chip);
	5300	+ err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
	5301	+ mv88e6xxx_reg_unlock(chip);
	5302	+
	5303	+ return err;
	5304	+}
	5305	+
	5306	+static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
	5307	+ struct dsa_mall_mirror_tc_entry *mirror,
	5308	+ bool ingress)
	5309	+{
	5310	+ enum mv88e6xxx_egress_direction direction = ingress ?
	5311	+ MV88E6XXX_EGRESS_DIR_INGRESS :
	5312	+ MV88E6XXX_EGRESS_DIR_EGRESS;
	5313	+ struct mv88e6xxx_chip *chip = ds->priv;
	5314	+ bool other_mirrors = false;
	5315	+ int i;
	5316	+ int err;
	5317	+
	5318	+ if (!chip->info->ops->set_egress_port)
	5319	+ return -EOPNOTSUPP;
	5320	+
4683	5321	mutex_lock(&chip->reg_lock);
4684		- err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4685		- MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
	5322	+ if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
	5323	+ mirror->to_local_port) {
	5324	+ for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
	5325	+ other_mirrors \|= ingress ?
	5326	+ chip->ports[i].mirror_ingress :
	5327	+ chip->ports[i].mirror_egress;
	5328	+
	5329	+ /* Can't change egress port when other mirror is active */
	5330	+ if (other_mirrors) {
	5331	+ err = -EBUSY;
	5332	+ goto out;
	5333	+ }
	5334	+
	5335	+ err = chip->info->ops->set_egress_port(chip,
	5336	+ direction,
	5337	+ mirror->to_local_port);
	5338	+ if (err)
	5339	+ goto out;
	5340	+ }
	5341	+
	5342	+ err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
	5343	+out:
4686	5344	mutex_unlock(&chip->reg_lock);
4687	5345
4688	5346	return err;
4689	5347	}
4690	5348
	5349	+static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
	5350	+ struct dsa_mall_mirror_tc_entry *mirror)
	5351	+{
	5352	+ enum mv88e6xxx_egress_direction direction = mirror->ingress ?
	5353	+ MV88E6XXX_EGRESS_DIR_INGRESS :
	5354	+ MV88E6XXX_EGRESS_DIR_EGRESS;
	5355	+ struct mv88e6xxx_chip *chip = ds->priv;
	5356	+ bool other_mirrors = false;
	5357	+ int i;
	5358	+
	5359	+ mutex_lock(&chip->reg_lock);
	5360	+ if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
	5361	+ dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
	5362	+
	5363	+ for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
	5364	+ other_mirrors \|= mirror->ingress ?
	5365	+ chip->ports[i].mirror_ingress :
	5366	+ chip->ports[i].mirror_egress;
	5367	+
	5368	+ /* Reset egress port when no other mirror is active */
	5369	+ if (!other_mirrors) {
	5370	+ if (chip->info->ops->set_egress_port(chip,
	5371	+ direction,
	5372	+ dsa_upstream_port(ds,
	5373	+ port)))
	5374	+ dev_err(ds->dev, "failed to set egress port\n");
	5375	+ }
	5376	+
	5377	+ mutex_unlock(&chip->reg_lock);
	5378	+}
	5379	+
	5380	+static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port,
	5381	+ bool unicast, bool multicast)
	5382	+{
	5383	+ struct mv88e6xxx_chip *chip = ds->priv;
	5384	+ int err = -EOPNOTSUPP;
	5385	+
	5386	+ mv88e6xxx_reg_lock(chip);
	5387	+ if (chip->info->ops->port_set_egress_floods)
	5388	+ err = chip->info->ops->port_set_egress_floods(chip, port,
	5389	+ unicast,
	5390	+ multicast);
	5391	+ mv88e6xxx_reg_unlock(chip);
	5392	+
	5393	+ return err;
	5394	+}
	5395	+
4691	5396	static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4692		-#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4693		- .probe = mv88e6xxx_drv_probe,
4694		-#endif
4695	5397	.get_tag_protocol = mv88e6xxx_get_tag_protocol,
4696	5398	.setup = mv88e6xxx_setup,
4697		- .adjust_link = mv88e6xxx_adjust_link,
	5399	+ .teardown = mv88e6xxx_teardown,
4698	5400	.phylink_validate = mv88e6xxx_validate,
4699		- .phylink_mac_link_state = mv88e6xxx_link_state,
	5401	+ .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
4700	5402	.phylink_mac_config = mv88e6xxx_mac_config,
	5403	+ .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
4701	5404	.phylink_mac_link_down = mv88e6xxx_mac_link_down,
4702	5405	.phylink_mac_link_up = mv88e6xxx_mac_link_up,
4703	5406	.get_strings = mv88e6xxx_get_strings,
..	..	@@ -4705,6 +5408,8 @@
4705	5408	.get_sset_count = mv88e6xxx_get_sset_count,
4706	5409	.port_enable = mv88e6xxx_port_enable,
4707	5410	.port_disable = mv88e6xxx_port_disable,
	5411	+ .port_max_mtu = mv88e6xxx_get_max_mtu,
	5412	+ .port_change_mtu = mv88e6xxx_change_mtu,
4708	5413	.get_mac_eee = mv88e6xxx_get_mac_eee,
4709	5414	.set_mac_eee = mv88e6xxx_set_mac_eee,
4710	5415	.get_eeprom_len = mv88e6xxx_get_eeprom_len,
..	..	@@ -4712,9 +5417,12 @@
4712	5417	.set_eeprom = mv88e6xxx_set_eeprom,
4713	5418	.get_regs_len = mv88e6xxx_get_regs_len,
4714	5419	.get_regs = mv88e6xxx_get_regs,
	5420	+ .get_rxnfc = mv88e6xxx_get_rxnfc,
	5421	+ .set_rxnfc = mv88e6xxx_set_rxnfc,
4715	5422	.set_ageing_time = mv88e6xxx_set_ageing_time,
4716	5423	.port_bridge_join = mv88e6xxx_port_bridge_join,
4717	5424	.port_bridge_leave = mv88e6xxx_port_bridge_leave,
	5425	+ .port_egress_floods = mv88e6xxx_port_egress_floods,
4718	5426	.port_stp_state_set = mv88e6xxx_port_stp_state_set,
4719	5427	.port_fast_age = mv88e6xxx_port_fast_age,
4720	5428	.port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
..	..	@@ -4727,6 +5435,8 @@
4727	5435	.port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4728	5436	.port_mdb_add = mv88e6xxx_port_mdb_add,
4729	5437	.port_mdb_del = mv88e6xxx_port_mdb_del,
	5438	+ .port_mirror_add = mv88e6xxx_port_mirror_add,
	5439	+ .port_mirror_del = mv88e6xxx_port_mirror_del,
4730	5440	.crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
4731	5441	.crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
4732	5442	.port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
..	..	@@ -4734,10 +5444,9 @@
4734	5444	.port_txtstamp = mv88e6xxx_port_txtstamp,
4735	5445	.port_rxtstamp = mv88e6xxx_port_rxtstamp,
4736	5446	.get_ts_info = mv88e6xxx_get_ts_info,
4737		-};
4738		-
4739		-static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4740		- .ops = &mv88e6xxx_switch_ops,
	5447	+ .devlink_param_get = mv88e6xxx_devlink_param_get,
	5448	+ .devlink_param_set = mv88e6xxx_devlink_param_set,
	5449	+ .devlink_info_get = mv88e6xxx_devlink_info_get,
4741	5450	};
4742	5451
4743	5452	static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
..	..	@@ -4745,10 +5454,12 @@
4745	5454	struct device *dev = chip->dev;
4746	5455	struct dsa_switch *ds;
4747	5456
4748		- ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
	5457	+ ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
4749	5458	if (!ds)
4750	5459	return -ENOMEM;
4751	5460
	5461	+ ds->dev = dev;
	5462	+ ds->num_ports = mv88e6xxx_num_ports(chip);
4752	5463	ds->priv = chip;
4753	5464	ds->dev = dev;
4754	5465	ds->ops = &mv88e6xxx_switch_ops;
..	..	@@ -4777,6 +5488,21 @@
4777	5488	}
4778	5489	return NULL;
4779	5490	}
	5491	+
	5492	+/* There is no suspend to RAM support at DSA level yet, the switch configuration
	5493	+ * would be lost after a power cycle so prevent it to be suspended.
	5494	+ */
	5495	+static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
	5496	+{
	5497	+ return -EOPNOTSUPP;
	5498	+}
	5499	+
	5500	+static int __maybe_unused mv88e6xxx_resume(struct device *dev)
	5501	+{
	5502	+ return 0;
	5503	+}
	5504	+
	5505	+static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
4780	5506
4781	5507	static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4782	5508	{
..	..	@@ -4831,13 +5557,12 @@
4831	5557	goto out;
4832	5558	}
4833	5559	if (chip->reset)
4834		- usleep_range(1000, 2000);
	5560	+ usleep_range(10000, 20000);
4835	5561
4836	5562	err = mv88e6xxx_detect(chip);
4837	5563	if (err)
4838	5564	goto out;
4839	5565
4840		- mv88e6xxx_ports_cmode_init(chip);
4841	5566	mv88e6xxx_phy_init(chip);
4842	5567
4843	5568	if (chip->info->ops->get_eeprom) {
..	..	@@ -4848,28 +5573,33 @@
4848	5573	chip->eeprom_len = pdata->eeprom_len;
4849	5574	}
4850	5575
4851		- mutex_lock(&chip->reg_lock);
	5576	+ mv88e6xxx_reg_lock(chip);
4852	5577	err = mv88e6xxx_switch_reset(chip);
4853		- mutex_unlock(&chip->reg_lock);
	5578	+ mv88e6xxx_reg_unlock(chip);
4854	5579	if (err)
4855	5580	goto out;
4856	5581
4857		- chip->irq = of_irq_get(np, 0);
4858		- if (chip->irq == -EPROBE_DEFER) {
4859		- err = chip->irq;
4860		- goto out;
	5582	+ if (np) {
	5583	+ chip->irq = of_irq_get(np, 0);
	5584	+ if (chip->irq == -EPROBE_DEFER) {
	5585	+ err = chip->irq;
	5586	+ goto out;
	5587	+ }
4861	5588	}
	5589	+
	5590	+ if (pdata)
	5591	+ chip->irq = pdata->irq;
4862	5592
4863	5593	/* Has to be performed before the MDIO bus is created, because
4864	5594	* the PHYs will link their interrupts to these interrupt
4865	5595	* controllers
4866	5596	*/
4867		- mutex_lock(&chip->reg_lock);
	5597	+ mv88e6xxx_reg_lock(chip);
4868	5598	if (chip->irq > 0)
4869	5599	err = mv88e6xxx_g1_irq_setup(chip);
4870	5600	else
4871	5601	err = mv88e6xxx_irq_poll_setup(chip);
4872		- mutex_unlock(&chip->reg_lock);
	5602	+ mv88e6xxx_reg_unlock(chip);
4873	5603
4874	5604	if (err)
4875	5605	goto out;
..	..	@@ -4954,6 +5684,10 @@
4954	5684	.compatible = "marvell,mv88e6190",
4955	5685	.data = &mv88e6xxx_table[MV88E6190],
4956	5686	},
	5687	+ {
	5688	+ .compatible = "marvell,mv88e6250",
	5689	+ .data = &mv88e6xxx_table[MV88E6250],
	5690	+ },
4957	5691	{ /* sentinel */ },
4958	5692	};
4959	5693
..	..	@@ -4965,22 +5699,11 @@
4965	5699	.mdiodrv.driver = {
4966	5700	.name = "mv88e6085",
4967	5701	.of_match_table = mv88e6xxx_of_match,
	5702	+ .pm = &mv88e6xxx_pm_ops,
4968	5703	},
4969	5704	};
4970	5705
4971		-static int __init mv88e6xxx_init(void)
4972		-{
4973		- register_switch_driver(&mv88e6xxx_switch_drv);
4974		- return mdio_driver_register(&mv88e6xxx_driver);
4975		-}
4976		-module_init(mv88e6xxx_init);
4977		-
4978		-static void __exit mv88e6xxx_cleanup(void)
4979		-{
4980		- mdio_driver_unregister(&mv88e6xxx_driver);
4981		- unregister_switch_driver(&mv88e6xxx_switch_drv);
4982		-}
4983		-module_exit(mv88e6xxx_cleanup);
	5706	+mdio_module_driver(mv88e6xxx_driver);
4984	5707
4985	5708	MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4986	5709	MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");