forked from ~ljy/RK356X_SDK_RELEASE

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2024-09-20 cf4ce59b3b70238352c7f1729f0f7223214828ad 
 kernel/drivers/net/dsa/mv88e6xxx/chip.c
....@@ -2310,12 +2310,22 @@
23102310 
23112311 	/* If there is a GPIO connected to the reset pin, toggle it */
23122312 	if (gpiod) {
2313
+		/* If the switch has just been reset and not yet completed
2314
+		 * loading EEPROM, the reset may interrupt the I2C transaction
2315
+		 * mid-byte, causing the first EEPROM read after the reset
2316
+		 * from the wrong location resulting in the switch booting
2317
+		 * to wrong mode and inoperable.
2318
+		 */
2319
+		if (chip->info->ops->get_eeprom)
2320
+			mv88e6xxx_g2_eeprom_wait(chip);
2321
+
23132322 		gpiod_set_value_cansleep(gpiod, 1);
23142323 		usleep_range(10000, 20000);
23152324 		gpiod_set_value_cansleep(gpiod, 0);
23162325 		usleep_range(10000, 20000);
23172326 
2318
-		mv88e6xxx_g1_wait_eeprom_done(chip);
2327
+		if (chip->info->ops->get_eeprom)
2328
+			mv88e6xxx_g2_eeprom_wait(chip);
23192329 	}
23202330 }
23212331 
....@@ -2611,9 +2621,14 @@
26112621 	 * If this is the upstream port for this switch, enable
26122622 	 * forwarding of unknown unicasts and multicasts.
26132623 	 */
2614
-	reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2615
-		MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2624
+	reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
26162625 		MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2626
+	/* Forward any IPv4 IGMP or IPv6 MLD frames received
2627
+	 * by a USER port to the CPU port to allow snooping.
2628
+	 */
2629
+	if (dsa_is_user_port(ds, port))
2630
+		reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP;
2631
+
26172632 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
26182633 	if (err)
26192634 		return err;
....@@ -2734,13 +2749,24 @@
27342749 		return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
27352750 	else if (chip->info->ops->set_max_frame_size)
27362751 		return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
2737
-	return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
2752
+	return ETH_DATA_LEN;
27382753 }
27392754 
27402755 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
27412756 {
27422757 	struct mv88e6xxx_chip *chip = ds->priv;
27432758 	int ret = 0;
2759
+
2760
+	/* For families where we don't know how to alter the MTU,
2761
+	 * just accept any value up to ETH_DATA_LEN
2762
+	 */
2763
+	if (!chip->info->ops->port_set_jumbo_size &&
2764
+	    !chip->info->ops->set_max_frame_size) {
2765
+		if (new_mtu > ETH_DATA_LEN)
2766
+			return -EINVAL;
2767
+
2768
+		return 0;
2769
+	}
27442770 
27452771 	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
27462772 		new_mtu += EDSA_HLEN;
....@@ -2750,9 +2776,6 @@
27502776 		ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
27512777 	else if (chip->info->ops->set_max_frame_size)
27522778 		ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
2753
-	else
2754
-		if (new_mtu > 1522)
2755
-			ret = -EINVAL;
27562779 	mv88e6xxx_reg_unlock(chip);
27572780 
27582781 	return ret;
....@@ -4169,6 +4192,7 @@
41694192 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
41704193 	.set_egress_port = mv88e6095_g1_set_egress_port,
41714194 	.watchdog_ops = &mv88e6390_watchdog_ops,
4195
+	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
41724196 	.reset = mv88e6352_g1_reset,
41734197 	.vtu_getnext = mv88e6185_g1_vtu_getnext,
41744198 	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
....@@ -5533,7 +5557,7 @@
55335557 		goto out;
55345558 	}
55355559 	if (chip->reset)
5536
-		usleep_range(1000, 2000);
5560
+		usleep_range(10000, 20000);
55375561 
55385562 	err = mv88e6xxx_detect(chip);
55395563 	if (err)