rtl88x2CE_WiFi_linux add concurrent mode

hc

2024-09-20 cf4ce59b3b70238352c7f1729f0f7223214828ad

 kernel/drivers/memory/jz4780-nemc.c
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@@ -1,16 +1,14 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * JZ4780 NAND/external memory controller (NEMC)
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  *
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  * Copyright (c) 2015 Imagination Technologies
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  * Author: Alex Smith <alex@alex-smith.me.uk>
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of the GNU General Public License version 2 as published
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- * by the Free Software Foundation.
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  */
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8
 
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 #include <linux/clk.h>
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 #include <linux/init.h>
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+#include <linux/io.h>
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 #include <linux/math64.h>
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 #include <linux/of.h>
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 #include <linux/of_address.h>
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@@ -24,6 +22,8 @@
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22
 
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 #define NEMC_SMCRn(n)		(0x14 + (((n) - 1) * 4))
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 #define NEMC_NFCSR		0x50
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+
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+#define NEMC_REG_LEN		0x54
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 #define NEMC_SMCR_SMT		BIT(0)
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 #define NEMC_SMCR_BW_SHIFT	6
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@@ -44,9 +44,14 @@
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 #define NEMC_NFCSR_NFCEn(n)	BIT((((n) - 1) << 1) + 1)
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 #define NEMC_NFCSR_TNFEn(n)	BIT(16 + (n) - 1)
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46
 
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+struct jz_soc_info {
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+	u8 tas_tah_cycles_max;
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+};
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+
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 struct jz4780_nemc {
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 	spinlock_t lock;
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 	struct device *dev;
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+	const struct jz_soc_info *soc_info;
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 	void __iomem *base;
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 	struct clk *clk;
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 	uint32_t clk_period;
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@@ -59,7 +64,7 @@
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  *
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  * Return: The number of unique NEMC banks referred to by the specified NEMC
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  * child device. Unique here means that a device that references the same bank
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- * multiple times in the its "reg" property will only count once.
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+ * multiple times in its "reg" property will only count once.
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  */
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 unsigned int jz4780_nemc_num_banks(struct device *dev)
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 {
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@@ -161,7 +166,7 @@
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 	 * Conversion of tBP and tAW cycle counts to values supported by the
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 	 * hardware (round up to the next supported value).
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 	 */
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-	static const uint32_t convert_tBP_tAW[] = {
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+	static const u8 convert_tBP_tAW[] = {
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 		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
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 		/* 11 - 12 -> 12 cycles */
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@@ -202,7 +207,7 @@
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 	if (of_property_read_u32(node, "ingenic,nemc-tAS", &val) == 0) {
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 		smcr &= ~NEMC_SMCR_TAS_MASK;
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 		cycles = jz4780_nemc_ns_to_cycles(nemc, val);
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-		if (cycles > 15) {
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+		if (cycles > nemc->soc_info->tas_tah_cycles_max) {
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 			dev_err(nemc->dev, "tAS %u is too high (%u cycles)\n",
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 				val, cycles);
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 			return false;
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@@ -214,7 +219,7 @@
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 	if (of_property_read_u32(node, "ingenic,nemc-tAH", &val) == 0) {
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 		smcr &= ~NEMC_SMCR_TAH_MASK;
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 		cycles = jz4780_nemc_ns_to_cycles(nemc, val);
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-		if (cycles > 15) {
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+		if (cycles > nemc->soc_info->tas_tah_cycles_max) {
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 			dev_err(nemc->dev, "tAH %u is too high (%u cycles)\n",
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 				val, cycles);
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 			return false;
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@@ -278,14 +283,32 @@
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 	if (!nemc)
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 		return -ENOMEM;
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+	nemc->soc_info = device_get_match_data(dev);
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+	if (!nemc->soc_info)
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+		return -EINVAL;
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+
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 	spin_lock_init(&nemc->lock);
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 	nemc->dev = dev;
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 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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-	nemc->base = devm_ioremap_resource(dev, res);
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-	if (IS_ERR(nemc->base)) {
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+	if (!res)
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+		return -EINVAL;
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+
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+	/*
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+	 * The driver currently only uses the registers up to offset
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+	 * NEMC_REG_LEN. Since the EFUSE registers are in the middle of the
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+	 * NEMC registers, we only request the registers we will use for now;
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+	 * that way the EFUSE driver can probe too.
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+	 */
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+	if (!devm_request_mem_region(dev, res->start, NEMC_REG_LEN, dev_name(dev))) {
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+		dev_err(dev, "unable to request I/O memory region\n");
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+		return -EBUSY;
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+	}
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+
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+	nemc->base = devm_ioremap(dev, res->start, NEMC_REG_LEN);
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+	if (!nemc->base) {
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 		dev_err(dev, "failed to get I/O memory\n");
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-		return PTR_ERR(nemc->base);
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+		return -ENOMEM;
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 	}
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 	writel(0, nemc->base + NEMC_NFCSR);
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@@ -370,8 +393,17 @@
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 	return 0;
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 }
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395
 
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+static const struct jz_soc_info jz4740_soc_info = {
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+	.tas_tah_cycles_max = 7,
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+};
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+
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+static const struct jz_soc_info jz4780_soc_info = {
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+	.tas_tah_cycles_max = 15,
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+};
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+
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 static const struct of_device_id jz4780_nemc_dt_match[] = {
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-	{ .compatible = "ingenic,jz4780-nemc" },
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+	{ .compatible = "ingenic,jz4740-nemc", .data = &jz4740_soc_info, },
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+	{ .compatible = "ingenic,jz4780-nemc", .data = &jz4780_soc_info, },
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 	{},
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 };
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