rtl88x2CE_WiFi_linux add concurrent mode

hc

2024-09-20 cf4ce59b3b70238352c7f1729f0f7223214828ad

 kernel/arch/x86/include/asm/uv/uv_hub.h
..
..
@@ -5,6 +5,7 @@
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  *
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  * SGI UV architectural definitions
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  *
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+ * (C) Copyright 2020 Hewlett Packard Enterprise Development LP
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  * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
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  */
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11
 
..
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@@ -19,6 +20,7 @@
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 #include <linux/topology.h>
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 #include <asm/types.h>
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 #include <asm/percpu.h>
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+#include <asm/uv/uv.h>
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 #include <asm/uv/uv_mmrs.h>
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 #include <asm/uv/bios.h>
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 #include <asm/irq_vectors.h>
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@@ -128,17 +130,6 @@
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  */
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 #define UV_MAX_NASID_VALUE	(UV_MAX_NUMALINK_BLADES * 2)
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132
 
131
-/* System Controller Interface Reg info */
132
-struct uv_scir_s {
133
-	struct timer_list timer;
134
-	unsigned long	offset;
135
-	unsigned long	last;
136
-	unsigned long	idle_on;
137
-	unsigned long	idle_off;
138
-	unsigned char	state;
139
-	unsigned char	enabled;
140
-};
141
-
142
133
 /* GAM (globally addressed memory) range table */
143
134
 struct uv_gam_range_s {
144
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 	u32	limit;		/* PA bits 56:26 (GAM_RANGE_SHFT) */
..
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@@ -154,6 +145,8 @@
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  * available in the L3 cache on the cpu socket for the node.
155
146
  */
156
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 struct uv_hub_info_s {
148
+	unsigned int		hub_type;
149
+	unsigned char		hub_revision;
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150
 	unsigned long		global_mmr_base;
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151
 	unsigned long		global_mmr_shift;
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152
 	unsigned long		gpa_mask;
..
..
@@ -166,9 +159,9 @@
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 	unsigned char		m_val;
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160
 	unsigned char		n_val;
168
161
 	unsigned char		gr_table_len;
169
-	unsigned char		hub_revision;
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162
 	unsigned char		apic_pnode_shift;
171
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 	unsigned char		gpa_shift;
164
+	unsigned char		nasid_shift;
172
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 	unsigned char		m_shift;
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 	unsigned char		n_lshift;
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167
 	unsigned int		gnode_extra;
..
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@@ -190,15 +183,12 @@
190
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 struct uv_cpu_info_s {
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 	void			*p_uv_hub_info;
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 	unsigned char		blade_cpu_id;
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-	struct uv_scir_s	scir;
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+	void			*reserved;
194
187
 };
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 DECLARE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
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189
 
197
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 #define uv_cpu_info		this_cpu_ptr(&__uv_cpu_info)
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 #define uv_cpu_info_per(cpu)	(&per_cpu(__uv_cpu_info, cpu))
199
-
200
-#define	uv_scir_info		(&uv_cpu_info->scir)
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-#define	uv_cpu_scir_info(cpu)	(&uv_cpu_info_per(cpu)->scir)
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192
 
203
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 /* Node specific hub common info struct */
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 extern void **__uv_hub_info_list;
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@@ -218,109 +208,51 @@
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 	return (struct uv_hub_info_s *)uv_cpu_info_per(cpu)->p_uv_hub_info;
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209
 }
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210
 
221
-#define	UV_HUB_INFO_VERSION	0x7150
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-extern int uv_hub_info_version(void);
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-static inline int uv_hub_info_check(int version)
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+static inline int uv_hub_type(void)
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212
 {
225
-	if (uv_hub_info_version() == version)
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-		return 0;
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-
228
-	pr_crit("UV: uv_hub_info version(%x) mismatch, expecting(%x)\n",
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-		uv_hub_info_version(), version);
230
-
231
-	BUG();	/* Catastrophic - cannot continue on unknown UV system */
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+	return uv_hub_info->hub_type;
232
214
 }
233
-#define	_uv_hub_info_check()	uv_hub_info_check(UV_HUB_INFO_VERSION)
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+
216
+static inline __init void uv_hub_type_set(int uvmask)
217
+{
218
+	uv_hub_info->hub_type = uvmask;
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+}
220
+
234
221
 
235
222
 /*
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  * HUB revision ranges for each UV HUB architecture.
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  * This is a software convention - NOT the hardware revision numbers in
238
225
  * the hub chip.
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  */
240
-#define UV1_HUB_REVISION_BASE		1
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227
 #define UV2_HUB_REVISION_BASE		3
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 #define UV3_HUB_REVISION_BASE		5
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 #define UV4_HUB_REVISION_BASE		7
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 #define UV4A_HUB_REVISION_BASE		8	/* UV4 (fixed) rev 2 */
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+#define UV5_HUB_REVISION_BASE		9
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232
 
246
-#ifdef	UV1_HUB_IS_SUPPORTED
247
-static inline int is_uv1_hub(void)
248
-{
249
-	return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE;
250
-}
251
-#else
252
-static inline int is_uv1_hub(void)
253
-{
254
-	return 0;
255
-}
256
-#endif
233
+static inline int is_uv(int uvmask) { return uv_hub_type() & uvmask; }
234
+static inline int is_uv1_hub(void) { return 0; }
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+static inline int is_uv2_hub(void) { return is_uv(UV2); }
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+static inline int is_uv3_hub(void) { return is_uv(UV3); }
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+static inline int is_uv4a_hub(void) { return is_uv(UV4A); }
238
+static inline int is_uv4_hub(void) { return is_uv(UV4); }
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+static inline int is_uv5_hub(void) { return is_uv(UV5); }
257
240
 
258
-#ifdef	UV2_HUB_IS_SUPPORTED
259
-static inline int is_uv2_hub(void)
260
-{
261
-	return ((uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) &&
262
-		(uv_hub_info->hub_revision < UV3_HUB_REVISION_BASE));
263
-}
264
-#else
265
-static inline int is_uv2_hub(void)
266
-{
267
-	return 0;
268
-}
269
-#endif
241
+/*
242
+ * UV4A is a revision of UV4.  So on UV4A, both is_uv4_hub() and
243
+ * is_uv4a_hub() return true, While on UV4, only is_uv4_hub()
244
+ * returns true.  So to get true results, first test if is UV4A,
245
+ * then test if is UV4.
246
+ */
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247
 
271
-#ifdef	UV3_HUB_IS_SUPPORTED
272
-static inline int is_uv3_hub(void)
273
-{
274
-	return ((uv_hub_info->hub_revision >= UV3_HUB_REVISION_BASE) &&
275
-		(uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE));
276
-}
277
-#else
278
-static inline int is_uv3_hub(void)
279
-{
280
-	return 0;
281
-}
282
-#endif
248
+/* UVX class: UV2,3,4 */
249
+static inline int is_uvx_hub(void) { return is_uv(UVX); }
283
250
 
284
-/* First test "is UV4A", then "is UV4" */
285
-#ifdef	UV4A_HUB_IS_SUPPORTED
286
-static inline int is_uv4a_hub(void)
287
-{
288
-	return (uv_hub_info->hub_revision >= UV4A_HUB_REVISION_BASE);
289
-}
290
-#else
291
-static inline int is_uv4a_hub(void)
292
-{
293
-	return 0;
294
-}
295
-#endif
251
+/* UVY class: UV5,..? */
252
+static inline int is_uvy_hub(void) { return is_uv(UVY); }
296
253
 
297
-#ifdef	UV4_HUB_IS_SUPPORTED
298
-static inline int is_uv4_hub(void)
299
-{
300
-	return uv_hub_info->hub_revision >= UV4_HUB_REVISION_BASE;
301
-}
302
-#else
303
-static inline int is_uv4_hub(void)
304
-{
305
-	return 0;
306
-}
307
-#endif
308
-
309
-static inline int is_uvx_hub(void)
310
-{
311
-	if (uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE)
312
-		return uv_hub_info->hub_revision;
313
-
314
-	return 0;
315
-}
316
-
317
-static inline int is_uv_hub(void)
318
-{
319
-#ifdef	UV1_HUB_IS_SUPPORTED
320
-	return uv_hub_info->hub_revision;
321
-#endif
322
-	return is_uvx_hub();
323
-}
254
+/* Any UV Hubbed System */
255
+static inline int is_uv_hub(void) { return is_uv(UV_ANY); }
324
256
 
325
257
 union uvh_apicid {
326
258
     unsigned long       v;
..
..
@@ -342,14 +274,11 @@
342
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  *		g -  GNODE (full 15-bit global nasid, right shifted 1)
343
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  *		p -  PNODE (local part of nsids, right shifted 1)
344
276
  */
345
-#define UV_NASID_TO_PNODE(n)		(((n) >> 1) & uv_hub_info->pnode_mask)
277
+#define UV_NASID_TO_PNODE(n)		\
278
+		(((n) >> uv_hub_info->nasid_shift) & uv_hub_info->pnode_mask)
346
279
 #define UV_PNODE_TO_GNODE(p)		((p) |uv_hub_info->gnode_extra)
347
-#define UV_PNODE_TO_NASID(p)		(UV_PNODE_TO_GNODE(p) << 1)
348
-
349
-#define UV1_LOCAL_MMR_BASE		0xf4000000UL
350
-#define UV1_GLOBAL_MMR32_BASE		0xf8000000UL
351
-#define UV1_LOCAL_MMR_SIZE		(64UL * 1024 * 1024)
352
-#define UV1_GLOBAL_MMR32_SIZE		(64UL * 1024 * 1024)
280
+#define UV_PNODE_TO_NASID(p)		\
281
+		(UV_PNODE_TO_GNODE(p) << uv_hub_info->nasid_shift)
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282
 
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 #define UV2_LOCAL_MMR_BASE		0xfa000000UL
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 #define UV2_GLOBAL_MMR32_BASE		0xfc000000UL
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..
@@ -362,33 +291,42 @@
362
291
 #define UV3_GLOBAL_MMR32_SIZE		(32UL * 1024 * 1024)
363
292
 
364
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 #define UV4_LOCAL_MMR_BASE		0xfa000000UL
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-#define UV4_GLOBAL_MMR32_BASE		0xfc000000UL
294
+#define UV4_GLOBAL_MMR32_BASE		0
366
295
 #define UV4_LOCAL_MMR_SIZE		(32UL * 1024 * 1024)
367
-#define UV4_GLOBAL_MMR32_SIZE		(16UL * 1024 * 1024)
296
+#define UV4_GLOBAL_MMR32_SIZE		0
297
+
298
+#define UV5_LOCAL_MMR_BASE		0xfa000000UL
299
+#define UV5_GLOBAL_MMR32_BASE		0
300
+#define UV5_LOCAL_MMR_SIZE		(32UL * 1024 * 1024)
301
+#define UV5_GLOBAL_MMR32_SIZE		0
368
302
 
369
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 #define UV_LOCAL_MMR_BASE		(				\
370
-					is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \
371
-					is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \
372
-					is_uv3_hub() ? UV3_LOCAL_MMR_BASE : \
373
-					/*is_uv4_hub*/ UV4_LOCAL_MMR_BASE)
304
+					is_uv(UV2) ? UV2_LOCAL_MMR_BASE : \
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+					is_uv(UV3) ? UV3_LOCAL_MMR_BASE : \
306
+					is_uv(UV4) ? UV4_LOCAL_MMR_BASE : \
307
+					is_uv(UV5) ? UV5_LOCAL_MMR_BASE : \
308
+					0)
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309
 
375
310
 #define UV_GLOBAL_MMR32_BASE		(				\
376
-					is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE : \
377
-					is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE : \
378
-					is_uv3_hub() ? UV3_GLOBAL_MMR32_BASE : \
379
-					/*is_uv4_hub*/ UV4_GLOBAL_MMR32_BASE)
311
+					is_uv(UV2) ? UV2_GLOBAL_MMR32_BASE : \
312
+					is_uv(UV3) ? UV3_GLOBAL_MMR32_BASE : \
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+					is_uv(UV4) ? UV4_GLOBAL_MMR32_BASE : \
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+					is_uv(UV5) ? UV5_GLOBAL_MMR32_BASE : \
315
+					0)
380
316
 
381
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 #define UV_LOCAL_MMR_SIZE		(				\
382
-					is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \
383
-					is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \
384
-					is_uv3_hub() ? UV3_LOCAL_MMR_SIZE : \
385
-					/*is_uv4_hub*/ UV4_LOCAL_MMR_SIZE)
318
+					is_uv(UV2) ? UV2_LOCAL_MMR_SIZE : \
319
+					is_uv(UV3) ? UV3_LOCAL_MMR_SIZE : \
320
+					is_uv(UV4) ? UV4_LOCAL_MMR_SIZE : \
321
+					is_uv(UV5) ? UV5_LOCAL_MMR_SIZE : \
322
+					0)
386
323
 
387
324
 #define UV_GLOBAL_MMR32_SIZE		(				\
388
-					is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE : \
389
-					is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE : \
390
-					is_uv3_hub() ? UV3_GLOBAL_MMR32_SIZE : \
391
-					/*is_uv4_hub*/ UV4_GLOBAL_MMR32_SIZE)
325
+					is_uv(UV2) ? UV2_GLOBAL_MMR32_SIZE : \
326
+					is_uv(UV3) ? UV3_GLOBAL_MMR32_SIZE : \
327
+					is_uv(UV4) ? UV4_GLOBAL_MMR32_SIZE : \
328
+					is_uv(UV5) ? UV5_GLOBAL_MMR32_SIZE : \
329
+					0)
392
330
 
393
331
 #define UV_GLOBAL_MMR64_BASE		(uv_hub_info->global_mmr_base)
394
332
 
..
..
@@ -405,8 +343,6 @@
405
343
 
406
344
 #define UVH_APICID		0x002D0E00L
407
345
 #define UV_APIC_PNODE_SHIFT	6
408
-
409
-#define UV_APICID_HIBIT_MASK	0xffff0000
410
346
 
411
347
 /* Local Bus from cpu's perspective */
412
348
 #define LOCAL_BUS_BASE		0x1c00000
..
..
@@ -614,15 +550,6 @@
614
550
 	return s2pn ? s2pn[pnode - uv_hub_info->min_socket] : pnode;
615
551
 }
616
552
 
617
-/* Convert an apicid to the socket number on the blade */
618
-static inline int uv_apicid_to_socket(int apicid)
619
-{
620
-	if (is_uv1_hub())
621
-		return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1;
622
-	else
623
-		return 0;
624
-}
625
-
626
553
 /*
627
554
  * Access global MMRs using the low memory MMR32 space. This region supports
628
555
  * faster MMR access but not all MMRs are accessible in this space.
..
..
@@ -713,9 +640,8 @@
713
640
 {
714
641
 	return uv_cpu_info_per(cpu)->blade_cpu_id;
715
642
 }
716
-#define _uv_cpu_blade_processor_id 1	/* indicate function available */
717
643
 
718
-/* Blade number to Node number (UV1..UV4 is 1:1) */
644
+/* Blade number to Node number (UV2..UV4 is 1:1) */
719
645
 static inline int uv_blade_to_node(int blade)
720
646
 {
721
647
 	return blade;
..
..
@@ -729,7 +655,7 @@
729
655
 
730
656
 /*
731
657
  * Convert linux node number to the UV blade number.
732
- * .. Currently for UV1 thru UV4 the node and the blade are identical.
658
+ * .. Currently for UV2 thru UV4 the node and the blade are identical.
733
659
  * .. If this changes then you MUST check references to this function!
734
660
  */
735
661
 static inline int uv_node_to_blade_id(int nid)
..
..
@@ -737,7 +663,7 @@
737
663
 	return nid;
738
664
 }
739
665
 
740
-/* Convert a cpu number to the the UV blade number */
666
+/* Convert a CPU number to the UV blade number */
741
667
 static inline int uv_cpu_to_blade_id(int cpu)
742
668
 {
743
669
 	return uv_node_to_blade_id(cpu_to_node(cpu));
..
..
@@ -801,26 +727,13 @@
801
727
 #define UVH_TSC_SYNC_SHIFT_UV2K	16	/* UV2/3k have different bits */
802
728
 #define UVH_TSC_SYNC_MASK	3	/* 0011 */
803
729
 #define UVH_TSC_SYNC_VALID	3	/* 0011 */
804
-#define UVH_TSC_SYNC_INVALID	2	/* 0010 */
730
+#define UVH_TSC_SYNC_UNKNOWN	0	/* 0000 */
805
731
 
806
732
 /* BMC sets a bit this MMR non-zero before sending an NMI */
807
733
 #define UVH_NMI_MMR		UVH_BIOS_KERNEL_MMR
808
734
 #define UVH_NMI_MMR_CLEAR	UVH_BIOS_KERNEL_MMR_ALIAS
809
735
 #define UVH_NMI_MMR_SHIFT	63
810
736
 #define UVH_NMI_MMR_TYPE	"SCRATCH5"
811
-
812
-/* Newer SMM NMI handler, not present in all systems */
813
-#define UVH_NMI_MMRX		UVH_EVENT_OCCURRED0
814
-#define UVH_NMI_MMRX_CLEAR	UVH_EVENT_OCCURRED0_ALIAS
815
-#define UVH_NMI_MMRX_SHIFT	UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT
816
-#define UVH_NMI_MMRX_TYPE	"EXTIO_INT0"
817
-
818
-/* Non-zero indicates newer SMM NMI handler present */
819
-#define UVH_NMI_MMRX_SUPPORTED	UVH_EXTIO_INT0_BROADCAST
820
-
821
-/* Indicates to BIOS that we want to use the newer SMM NMI handler */
822
-#define UVH_NMI_MMRX_REQ	UVH_BIOS_KERNEL_MMR_ALIAS_2
823
-#define UVH_NMI_MMRX_REQ_SHIFT	62
824
737
 
825
738
 struct uv_hub_nmi_s {
826
739
 	raw_spinlock_t	nmi_lock;
..
..
@@ -852,51 +765,6 @@
852
765
 #define	UV_NMI_STATE_IN			1
853
766
 #define	UV_NMI_STATE_DUMP		2
854
767
 #define	UV_NMI_STATE_DUMP_DONE		3
855
-
856
-/* Update SCIR state */
857
-static inline void uv_set_scir_bits(unsigned char value)
858
-{
859
-	if (uv_scir_info->state != value) {
860
-		uv_scir_info->state = value;
861
-		uv_write_local_mmr8(uv_scir_info->offset, value);
862
-	}
863
-}
864
-
865
-static inline unsigned long uv_scir_offset(int apicid)
866
-{
867
-	return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f);
868
-}
869
-
870
-static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
871
-{
872
-	if (uv_cpu_scir_info(cpu)->state != value) {
873
-		uv_write_global_mmr8(uv_cpu_to_pnode(cpu),
874
-				uv_cpu_scir_info(cpu)->offset, value);
875
-		uv_cpu_scir_info(cpu)->state = value;
876
-	}
877
-}
878
-
879
-extern unsigned int uv_apicid_hibits;
880
-static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode)
881
-{
882
-	apicid |= uv_apicid_hibits;
883
-	return (1UL << UVH_IPI_INT_SEND_SHFT) |
884
-			((apicid) << UVH_IPI_INT_APIC_ID_SHFT) |
885
-			(mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
886
-			(vector << UVH_IPI_INT_VECTOR_SHFT);
887
-}
888
-
889
-static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
890
-{
891
-	unsigned long val;
892
-	unsigned long dmode = dest_Fixed;
893
-
894
-	if (vector == NMI_VECTOR)
895
-		dmode = dest_NMI;
896
-
897
-	val = uv_hub_ipi_value(apicid, vector, dmode);
898
-	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
899
-}
900
768
 
901
769
 /*
902
770
  * Get the minimum revision number of the hub chips within the partition.