rtl88x2CE_WiFi_linux add concurrent mode

hc

2024-09-20 cf4ce59b3b70238352c7f1729f0f7223214828ad

 kernel/arch/mips/mm/c-r4k.c
..
..
@@ -29,7 +29,6 @@
29
29
 #include <asm/cpu-type.h>
30
30
 #include <asm/io.h>
31
31
 #include <asm/page.h>
32
-#include <asm/pgtable.h>
33
32
 #include <asm/r4kcache.h>
34
33
 #include <asm/sections.h>
35
34
 #include <asm/mmu_context.h>
..
..
@@ -131,9 +130,10 @@
131
130
 
132
131
 #define R4600_HIT_CACHEOP_WAR_IMPL					\
133
132
 do {									\
134
-	if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())		\
133
+	if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) &&		\
134
+	    cpu_is_r4600_v2_x())					\
135
135
 		*(volatile unsigned long *)CKSEG1;			\
136
-	if (R4600_V1_HIT_CACHEOP_WAR)					\
136
+	if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP))					\
137
137
 		__asm__ __volatile__("nop;nop;nop;nop");		\
138
138
 } while (0)
139
139
 
..
..
@@ -239,7 +239,7 @@
239
239
 		r4k_blast_dcache = blast_dcache128;
240
240
 }
241
241
 
242
-/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
242
+/* force code alignment (used for CONFIG_WAR_TX49XX_ICACHE_INDEX_INV) */
243
243
 #define JUMP_TO_ALIGN(order) \
244
244
 	__asm__ __volatile__( \
245
245
 		"b\t1f\n\t" \
..
..
@@ -271,12 +271,14 @@
271
271
 	/* I'm in even chunk.  blast odd chunks */
272
272
 	for (ws = 0; ws < ws_end; ws += ws_inc)
273
273
 		for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
274
-			cache32_unroll32(addr|ws, Index_Invalidate_I);
274
+			cache_unroll(32, kernel_cache, Index_Invalidate_I,
275
+				     addr | ws, 32);
275
276
 	CACHE32_UNROLL32_ALIGN;
276
277
 	/* I'm in odd chunk.  blast even chunks */
277
278
 	for (ws = 0; ws < ws_end; ws += ws_inc)
278
279
 		for (addr = start; addr < end; addr += 0x400 * 2)
279
-			cache32_unroll32(addr|ws, Index_Invalidate_I);
280
+			cache_unroll(32, kernel_cache, Index_Invalidate_I,
281
+				     addr | ws, 32);
280
282
 }
281
283
 
282
284
 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
..
..
@@ -302,12 +304,14 @@
302
304
 	/* I'm in even chunk.  blast odd chunks */
303
305
 	for (ws = 0; ws < ws_end; ws += ws_inc)
304
306
 		for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
305
-			cache32_unroll32(addr|ws, Index_Invalidate_I);
307
+			cache_unroll(32, kernel_cache, Index_Invalidate_I,
308
+				     addr | ws, 32);
306
309
 	CACHE32_UNROLL32_ALIGN;
307
310
 	/* I'm in odd chunk.  blast even chunks */
308
311
 	for (ws = 0; ws < ws_end; ws += ws_inc)
309
312
 		for (addr = start; addr < end; addr += 0x400 * 2)
310
-			cache32_unroll32(addr|ws, Index_Invalidate_I);
313
+			cache_unroll(32, kernel_cache, Index_Invalidate_I,
314
+				     addr | ws, 32);
311
315
 }
312
316
 
313
317
 static void (* r4k_blast_icache_page)(unsigned long addr);
..
..
@@ -320,7 +324,7 @@
320
324
 		r4k_blast_icache_page = (void *)cache_noop;
321
325
 	else if (ic_lsize == 16)
322
326
 		r4k_blast_icache_page = blast_icache16_page;
323
-	else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2)
327
+	else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2EF)
324
328
 		r4k_blast_icache_page = loongson2_blast_icache32_page;
325
329
 	else if (ic_lsize == 32)
326
330
 		r4k_blast_icache_page = blast_icache32_page;
..
..
@@ -363,13 +367,14 @@
363
367
 	else if (ic_lsize == 16)
364
368
 		r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
365
369
 	else if (ic_lsize == 32) {
366
-		if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
370
+		if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
371
+		    cpu_is_r4600_v1_x())
367
372
 			r4k_blast_icache_page_indexed =
368
373
 				blast_icache32_r4600_v1_page_indexed;
369
-		else if (TX49XX_ICACHE_INDEX_INV_WAR)
374
+		else if (IS_ENABLED(CONFIG_WAR_TX49XX_ICACHE_INDEX_INV))
370
375
 			r4k_blast_icache_page_indexed =
371
376
 				tx49_blast_icache32_page_indexed;
372
-		else if (current_cpu_type() == CPU_LOONGSON2)
377
+		else if (current_cpu_type() == CPU_LOONGSON2EF)
373
378
 			r4k_blast_icache_page_indexed =
374
379
 				loongson2_blast_icache32_page_indexed;
375
380
 		else
..
..
@@ -391,11 +396,12 @@
391
396
 	else if (ic_lsize == 16)
392
397
 		r4k_blast_icache = blast_icache16;
393
398
 	else if (ic_lsize == 32) {
394
-		if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
399
+		if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
400
+		    cpu_is_r4600_v1_x())
395
401
 			r4k_blast_icache = blast_r4600_v1_icache32;
396
-		else if (TX49XX_ICACHE_INDEX_INV_WAR)
402
+		else if (IS_ENABLED(CONFIG_WAR_TX49XX_ICACHE_INDEX_INV))
397
403
 			r4k_blast_icache = tx49_blast_icache32;
398
-		else if (current_cpu_type() == CPU_LOONGSON2)
404
+		else if (current_cpu_type() == CPU_LOONGSON2EF)
399
405
 			r4k_blast_icache = loongson2_blast_icache32;
400
406
 		else
401
407
 			r4k_blast_icache = blast_icache32;
..
..
@@ -465,7 +471,7 @@
465
471
 {
466
472
 	unsigned long sc_lsize = cpu_scache_line_size();
467
473
 
468
-	if (current_cpu_type() != CPU_LOONGSON3)
474
+	if (current_cpu_type() != CPU_LOONGSON64)
469
475
 		r4k_blast_scache_node = (void *)cache_noop;
470
476
 	else if (sc_lsize == 16)
471
477
 		r4k_blast_scache_node = blast_scache16_node;
..
..
@@ -480,7 +486,7 @@
480
486
 static inline void local_r4k___flush_cache_all(void * args)
481
487
 {
482
488
 	switch (current_cpu_type()) {
483
-	case CPU_LOONGSON2:
489
+	case CPU_LOONGSON2EF:
484
490
 	case CPU_R4000SC:
485
491
 	case CPU_R4000MC:
486
492
 	case CPU_R4400SC:
..
..
@@ -497,7 +503,7 @@
497
503
 		r4k_blast_scache();
498
504
 		break;
499
505
 
500
-	case CPU_LOONGSON3:
506
+	case CPU_LOONGSON64:
501
507
 		/* Use get_ebase_cpunum() for both NUMA=y/n */
502
508
 		r4k_blast_scache_node(get_ebase_cpunum() >> 2);
503
509
 		break;
..
..
@@ -539,6 +545,9 @@
539
545
 {
540
546
 	unsigned int i;
541
547
 	const cpumask_t *mask = cpu_present_mask;
548
+
549
+	if (cpu_has_mmid)
550
+		return cpu_context(0, mm) != 0;
542
551
 
543
552
 	/* cpu_sibling_map[] undeclared when !CONFIG_SMP */
544
553
 #ifdef CONFIG_SMP
..
..
@@ -646,8 +655,6 @@
646
655
 	int exec = vma->vm_flags & VM_EXEC;
647
656
 	struct mm_struct *mm = vma->vm_mm;
648
657
 	int map_coherent = 0;
649
-	pgd_t *pgdp;
650
-	pud_t *pudp;
651
658
 	pmd_t *pmdp;
652
659
 	pte_t *ptep;
653
660
 	void *vaddr;
..
..
@@ -660,10 +667,8 @@
660
667
 		return;
661
668
 
662
669
 	addr &= PAGE_MASK;
663
-	pgdp = pgd_offset(mm, addr);
664
-	pudp = pud_offset(pgdp, addr);
665
-	pmdp = pmd_offset(pudp, addr);
666
-	ptep = pte_offset(pmdp, addr);
670
+	pmdp = pmd_off(mm, addr);
671
+	ptep = pte_offset_kernel(pmdp, addr);
667
672
 
668
673
 	/*
669
674
 	 * If the page isn't marked valid, the page cannot possibly be
..
..
@@ -697,10 +702,7 @@
697
702
 	}
698
703
 	if (exec) {
699
704
 		if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
700
-			int cpu = smp_processor_id();
701
-
702
-			if (cpu_context(cpu, mm) != 0)
703
-				drop_mmu_context(mm, cpu);
705
+			drop_mmu_context(mm);
704
706
 		} else
705
707
 			vaddr ? r4k_blast_icache_page(addr) :
706
708
 				r4k_blast_icache_user_page(addr);
..
..
@@ -770,7 +772,7 @@
770
772
 		r4k_blast_icache();
771
773
 	else {
772
774
 		switch (boot_cpu_type()) {
773
-		case CPU_LOONGSON2:
775
+		case CPU_LOONGSON2EF:
774
776
 			protected_loongson2_blast_icache_range(start, end);
775
777
 			break;
776
778
 
..
..
@@ -863,7 +865,7 @@
863
865
 	preempt_disable();
864
866
 	if (cpu_has_inclusive_pcaches) {
865
867
 		if (size >= scache_size) {
866
-			if (current_cpu_type() != CPU_LOONGSON3)
868
+			if (current_cpu_type() != CPU_LOONGSON64)
867
869
 				r4k_blast_scache();
868
870
 			else
869
871
 				r4k_blast_scache_node(pa_to_nid(addr));
..
..
@@ -895,6 +897,31 @@
895
897
 	__sync();
896
898
 }
897
899
 
900
+static void prefetch_cache_inv(unsigned long addr, unsigned long size)
901
+{
902
+	unsigned int linesz = cpu_scache_line_size();
903
+	unsigned long addr0 = addr, addr1;
904
+
905
+	addr0 &= ~(linesz - 1);
906
+	addr1 = (addr0 + size - 1) & ~(linesz - 1);
907
+
908
+	protected_writeback_scache_line(addr0);
909
+	if (likely(addr1 != addr0))
910
+		protected_writeback_scache_line(addr1);
911
+	else
912
+		return;
913
+
914
+	addr0 += linesz;
915
+	if (likely(addr1 != addr0))
916
+		protected_writeback_scache_line(addr0);
917
+	else
918
+		return;
919
+
920
+	addr1 -= linesz;
921
+	if (likely(addr1 > addr0))
922
+		protected_writeback_scache_line(addr0);
923
+}
924
+
898
925
 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
899
926
 {
900
927
 	/* Catch bad driver code */
..
..
@@ -902,9 +929,13 @@
902
929
 		return;
903
930
 
904
931
 	preempt_disable();
932
+
933
+	if (current_cpu_type() == CPU_BMIPS5000)
934
+		prefetch_cache_inv(addr, size);
935
+
905
936
 	if (cpu_has_inclusive_pcaches) {
906
937
 		if (size >= scache_size) {
907
-			if (current_cpu_type() != CPU_LOONGSON3)
938
+			if (current_cpu_type() != CPU_LOONGSON64)
908
939
 				r4k_blast_scache();
909
940
 			else
910
941
 				r4k_blast_scache_node(pa_to_nid(addr));
..
..
@@ -936,119 +967,6 @@
936
967
 	__sync();
937
968
 }
938
969
 #endif /* CONFIG_DMA_NONCOHERENT */
939
-
940
-struct flush_cache_sigtramp_args {
941
-	struct mm_struct *mm;
942
-	struct page *page;
943
-	unsigned long addr;
944
-};
945
-
946
-/*
947
- * While we're protected against bad userland addresses we don't care
948
- * very much about what happens in that case.  Usually a segmentation
949
- * fault will dump the process later on anyway ...
950
- */
951
-static void local_r4k_flush_cache_sigtramp(void *args)
952
-{
953
-	struct flush_cache_sigtramp_args *fcs_args = args;
954
-	unsigned long addr = fcs_args->addr;
955
-	struct page *page = fcs_args->page;
956
-	struct mm_struct *mm = fcs_args->mm;
957
-	int map_coherent = 0;
958
-	void *vaddr;
959
-
960
-	unsigned long ic_lsize = cpu_icache_line_size();
961
-	unsigned long dc_lsize = cpu_dcache_line_size();
962
-	unsigned long sc_lsize = cpu_scache_line_size();
963
-
964
-	/*
965
-	 * If owns no valid ASID yet, cannot possibly have gotten
966
-	 * this page into the cache.
967
-	 */
968
-	if (!has_valid_asid(mm, R4K_HIT))
969
-		return;
970
-
971
-	if (mm == current->active_mm) {
972
-		vaddr = NULL;
973
-	} else {
974
-		/*
975
-		 * Use kmap_coherent or kmap_atomic to do flushes for
976
-		 * another ASID than the current one.
977
-		 */
978
-		map_coherent = (cpu_has_dc_aliases &&
979
-				page_mapcount(page) &&
980
-				!Page_dcache_dirty(page));
981
-		if (map_coherent)
982
-			vaddr = kmap_coherent(page, addr);
983
-		else
984
-			vaddr = kmap_atomic(page);
985
-		addr = (unsigned long)vaddr + (addr & ~PAGE_MASK);
986
-	}
987
-
988
-	R4600_HIT_CACHEOP_WAR_IMPL;
989
-	if (!cpu_has_ic_fills_f_dc) {
990
-		if (dc_lsize)
991
-			vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1))
992
-			      : protected_writeback_dcache_line(
993
-							addr & ~(dc_lsize - 1));
994
-		if (!cpu_icache_snoops_remote_store && scache_size)
995
-			vaddr ? flush_scache_line(addr & ~(sc_lsize - 1))
996
-			      : protected_writeback_scache_line(
997
-							addr & ~(sc_lsize - 1));
998
-	}
999
-	if (ic_lsize)
1000
-		vaddr ? flush_icache_line(addr & ~(ic_lsize - 1))
1001
-		      : protected_flush_icache_line(addr & ~(ic_lsize - 1));
1002
-
1003
-	if (vaddr) {
1004
-		if (map_coherent)
1005
-			kunmap_coherent();
1006
-		else
1007
-			kunmap_atomic(vaddr);
1008
-	}
1009
-
1010
-	if (MIPS4K_ICACHE_REFILL_WAR) {
1011
-		__asm__ __volatile__ (
1012
-			".set push\n\t"
1013
-			".set noat\n\t"
1014
-			".set "MIPS_ISA_LEVEL"\n\t"
1015
-#ifdef CONFIG_32BIT
1016
-			"la	$at,1f\n\t"
1017
-#endif
1018
-#ifdef CONFIG_64BIT
1019
-			"dla	$at,1f\n\t"
1020
-#endif
1021
-			"cache	%0,($at)\n\t"
1022
-			"nop; nop; nop\n"
1023
-			"1:\n\t"
1024
-			".set pop"
1025
-			:
1026
-			: "i" (Hit_Invalidate_I));
1027
-	}
1028
-	if (MIPS_CACHE_SYNC_WAR)
1029
-		__asm__ __volatile__ ("sync");
1030
-}
1031
-
1032
-static void r4k_flush_cache_sigtramp(unsigned long addr)
1033
-{
1034
-	struct flush_cache_sigtramp_args args;
1035
-	int npages;
1036
-
1037
-	down_read(&current->mm->mmap_sem);
1038
-
1039
-	npages = get_user_pages_fast(addr, 1, 0, &args.page);
1040
-	if (npages < 1)
1041
-		goto out;
1042
-
1043
-	args.mm = current->mm;
1044
-	args.addr = addr;
1045
-
1046
-	r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_sigtramp, &args);
1047
-
1048
-	put_page(args.page);
1049
-out:
1050
-	up_read(&current->mm->mmap_sem);
1051
-}
1052
970
 
1053
971
 static void r4k_flush_icache_all(void)
1054
972
 {
..
..
@@ -1127,7 +1045,7 @@
1127
1045
 			"cache\t%1, 0x3000(%0)\n\t"
1128
1046
 			".set pop\n"
1129
1047
 			:
1130
-			: "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
1048
+			: "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill_I));
1131
1049
 	}
1132
1050
 }
1133
1051
 
..
..
@@ -1151,12 +1069,12 @@
1151
1069
 		if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
1152
1070
 			present = 1;
1153
1071
 		if (rev == PRID_REV_ENCODE_332(2, 4, 0))
1154
-			write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
1072
+			write_c0_config6(read_c0_config6() | MTI_CONF6_SYND);
1155
1073
 		break;
1156
1074
 	case PRID_IMP_1074K:
1157
1075
 		if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
1158
1076
 			present = 1;
1159
-			write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
1077
+			write_c0_config6(read_c0_config6() | MTI_CONF6_SYND);
1160
1078
 		}
1161
1079
 		break;
1162
1080
 	default:
..
..
@@ -1211,7 +1129,6 @@
1211
1129
 		c->options |= MIPS_CPU_CACHE_CDEX_P;
1212
1130
 		break;
1213
1131
 
1214
-	case CPU_R5432:
1215
1132
 	case CPU_R5500:
1216
1133
 		icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1217
1134
 		c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
..
..
@@ -1247,7 +1164,6 @@
1247
1164
 	case CPU_R4400PC:
1248
1165
 	case CPU_R4400SC:
1249
1166
 	case CPU_R4400MC:
1250
-	case CPU_R4300:
1251
1167
 		icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1252
1168
 		c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1253
1169
 		c->icache.ways = 1;
..
..
@@ -1280,6 +1196,7 @@
1280
1196
 
1281
1197
 	case CPU_VR4133:
1282
1198
 		write_c0_config(config & ~VR41_CONF_P4K);
1199
+		fallthrough;
1283
1200
 	case CPU_VR4131:
1284
1201
 		/* Workaround for cache instruction bug of VR4131 */
1285
1202
 		if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
..
..
@@ -1338,7 +1255,7 @@
1338
1255
 		c->options |= MIPS_CPU_PREFETCH;
1339
1256
 		break;
1340
1257
 
1341
-	case CPU_LOONGSON2:
1258
+	case CPU_LOONGSON2EF:
1342
1259
 		icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1343
1260
 		c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1344
1261
 		if (prid & 0x3)
..
..
@@ -1356,7 +1273,7 @@
1356
1273
 		c->dcache.waybit = 0;
1357
1274
 		break;
1358
1275
 
1359
-	case CPU_LOONGSON3:
1276
+	case CPU_LOONGSON64:
1360
1277
 		config1 = read_c0_config1();
1361
1278
 		lsize = (config1 >> 19) & 7;
1362
1279
 		if (lsize)
..
..
@@ -1381,7 +1298,9 @@
1381
1298
 					  c->dcache.ways *
1382
1299
 					  c->dcache.linesz;
1383
1300
 		c->dcache.waybit = 0;
1384
-		if ((prid & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2)
1301
+		if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >=
1302
+				(PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0) ||
1303
+				(c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
1385
1304
 			c->options |= MIPS_CPU_PREFETCH;
1386
1305
 		break;
1387
1306
 
..
..
@@ -1503,7 +1422,7 @@
1503
1422
 	case CPU_74K:
1504
1423
 	case CPU_1074K:
1505
1424
 		has_74k_erratum = alias_74k_erratum(c);
1506
-		/* Fall through. */
1425
+		fallthrough;
1507
1426
 	case CPU_M14KC:
1508
1427
 	case CPU_M14KEC:
1509
1428
 	case CPU_24K:
..
..
@@ -1527,6 +1446,7 @@
1527
1446
 			c->dcache.flags |= MIPS_CACHE_PINDEX;
1528
1447
 			break;
1529
1448
 		}
1449
+		fallthrough;
1530
1450
 	default:
1531
1451
 		if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
1532
1452
 			c->dcache.flags |= MIPS_CACHE_ALIASES;
..
..
@@ -1565,7 +1485,7 @@
1565
1485
 		c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1566
1486
 		break;
1567
1487
 
1568
-	case CPU_LOONGSON2:
1488
+	case CPU_LOONGSON2EF:
1569
1489
 		/*
1570
1490
 		 * LOONGSON2 has 4 way icache, but when using indexed cache op,
1571
1491
 		 * one op will act on all 4 ways
..
..
@@ -1573,17 +1493,17 @@
1573
1493
 		c->icache.ways = 1;
1574
1494
 	}
1575
1495
 
1576
-	printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1577
-	       icache_size >> 10,
1578
-	       c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1579
-	       way_string[c->icache.ways], c->icache.linesz);
1496
+	pr_info("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1497
+		icache_size >> 10,
1498
+		c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1499
+		way_string[c->icache.ways], c->icache.linesz);
1580
1500
 
1581
-	printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1582
-	       dcache_size >> 10, way_string[c->dcache.ways],
1583
-	       (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1584
-	       (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1501
+	pr_info("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1502
+		dcache_size >> 10, way_string[c->dcache.ways],
1503
+		(c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1504
+		(c->dcache.flags & MIPS_CACHE_ALIASES) ?
1585
1505
 			"cache aliases" : "no aliases",
1586
-	       c->dcache.linesz);
1506
+		c->dcache.linesz);
1587
1507
 }
1588
1508
 
1589
1509
 static void probe_vcache(void)
..
..
@@ -1591,7 +1511,7 @@
1591
1511
 	struct cpuinfo_mips *c = &current_cpu_data;
1592
1512
 	unsigned int config2, lsize;
1593
1513
 
1594
-	if (current_cpu_type() != CPU_LOONGSON3)
1514
+	if (current_cpu_type() != CPU_LOONGSON64)
1595
1515
 		return;
1596
1516
 
1597
1517
 	config2 = read_c0_config2();
..
..
@@ -1689,7 +1609,7 @@
1689
1609
 	c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1690
1610
 }
1691
1611
 
1692
-static void __init loongson3_sc_init(void)
1612
+static void loongson3_sc_init(void)
1693
1613
 {
1694
1614
 	struct cpuinfo_mips *c = &current_cpu_data;
1695
1615
 	unsigned int config2, lsize;
..
..
@@ -1706,8 +1626,13 @@
1706
1626
 	scache_size = c->scache.sets *
1707
1627
 				  c->scache.ways *
1708
1628
 				  c->scache.linesz;
1709
-	/* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */
1710
-	scache_size *= 4;
1629
+
1630
+	/* Loongson-3 has 4-Scache banks, while Loongson-2K have only 2 banks */
1631
+	if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
1632
+		scache_size *= 2;
1633
+	else
1634
+		scache_size *= 4;
1635
+
1711
1636
 	c->scache.waybit = 0;
1712
1637
 	c->scache.waysize = scache_size / c->scache.ways;
1713
1638
 	pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
..
..
@@ -1766,11 +1691,11 @@
1766
1691
 #endif
1767
1692
 		return;
1768
1693
 
1769
-	case CPU_LOONGSON2:
1694
+	case CPU_LOONGSON2EF:
1770
1695
 		loongson2_sc_init();
1771
1696
 		return;
1772
1697
 
1773
-	case CPU_LOONGSON3:
1698
+	case CPU_LOONGSON64:
1774
1699
 		loongson3_sc_init();
1775
1700
 		return;
1776
1701
 
..
..
@@ -1780,9 +1705,10 @@
1780
1705
 		return;
1781
1706
 
1782
1707
 	default:
1783
-		if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1784
-				    MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
1785
-				    MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) {
1708
+		if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
1709
+				    MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
1710
+				    MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
1711
+				    MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
1786
1712
 #ifdef CONFIG_MIPS_CPU_SCACHE
1787
1713
 			if (mips_sc_init ()) {
1788
1714
 				scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
..
..
@@ -1980,7 +1906,6 @@
1980
1906
 
1981
1907
 	__flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1982
1908
 
1983
-	flush_cache_sigtramp	= r4k_flush_cache_sigtramp;
1984
1909
 	flush_icache_all	= r4k_flush_icache_all;
1985
1910
 	local_flush_data_cache_page	= local_r4k_flush_data_cache_page;
1986
1911
 	flush_data_cache_page	= r4k_flush_data_cache_page;
..
..
@@ -1989,22 +1914,21 @@
1989
1914
 	__flush_icache_user_range	= r4k_flush_icache_user_range;
1990
1915
 	__local_flush_icache_user_range	= local_r4k_flush_icache_user_range;
1991
1916
 
1992
-#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
1993
-# if defined(CONFIG_DMA_PERDEV_COHERENT)
1994
-	if (0) {
1995
-# else
1996
-	if ((coherentio == IO_COHERENCE_ENABLED) ||
1997
-	    ((coherentio == IO_COHERENCE_DEFAULT) && hw_coherentio)) {
1998
-# endif
1917
+#ifdef CONFIG_DMA_NONCOHERENT
1918
+#ifdef CONFIG_DMA_MAYBE_COHERENT
1919
+	if (coherentio == IO_COHERENCE_ENABLED ||
1920
+	    (coherentio == IO_COHERENCE_DEFAULT && hw_coherentio)) {
1999
1921
 		_dma_cache_wback_inv	= (void *)cache_noop;
2000
1922
 		_dma_cache_wback	= (void *)cache_noop;
2001
1923
 		_dma_cache_inv		= (void *)cache_noop;
2002
-	} else {
1924
+	} else
1925
+#endif /* CONFIG_DMA_MAYBE_COHERENT */
1926
+	{
2003
1927
 		_dma_cache_wback_inv	= r4k_dma_cache_wback_inv;
2004
1928
 		_dma_cache_wback	= r4k_dma_cache_wback_inv;
2005
1929
 		_dma_cache_inv		= r4k_dma_cache_inv;
2006
1930
 	}
2007
-#endif
1931
+#endif /* CONFIG_DMA_NONCOHERENT */
2008
1932
 
2009
1933
 	build_clear_page();
2010
1934
 	build_copy_page();
..
..
@@ -2036,7 +1960,6 @@
2036
1960
 		/* I$ fills from D$ just by emptying the write buffers */
2037
1961
 		flush_cache_page = (void *)b5k_instruction_hazard;
2038
1962
 		flush_cache_range = (void *)b5k_instruction_hazard;
2039
-		flush_cache_sigtramp = (void *)b5k_instruction_hazard;
2040
1963
 		local_flush_data_cache_page = (void *)b5k_instruction_hazard;
2041
1964
 		flush_data_cache_page = (void *)b5k_instruction_hazard;
2042
1965
 		flush_icache_range = (void *)b5k_instruction_hazard;
..
..
@@ -2046,7 +1969,7 @@
2046
1969
 		/* Optimization: an L2 flush implicitly flushes the L1 */
2047
1970
 		current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
2048
1971
 		break;
2049
-	case CPU_LOONGSON3:
1972
+	case CPU_LOONGSON64:
2050
1973
 		/* Loongson-3 maintains cache coherency by hardware */
2051
1974
 		__flush_cache_all	= cache_noop;
2052
1975
 		__flush_cache_vmap	= cache_noop;
..
..
@@ -2055,7 +1978,6 @@
2055
1978
 		flush_cache_mm		= (void *)cache_noop;
2056
1979
 		flush_cache_page	= (void *)cache_noop;
2057
1980
 		flush_cache_range	= (void *)cache_noop;
2058
-		flush_cache_sigtramp	= (void *)cache_noop;
2059
1981
 		flush_icache_all	= (void *)cache_noop;
2060
1982
 		flush_data_cache_page	= (void *)cache_noop;
2061
1983
 		local_flush_data_cache_page	= (void *)cache_noop;