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2024-09-20 cf4ce59b3b70238352c7f1729f0f7223214828ad 
 kernel/arch/mips/boot/dts/ingenic/jz4740.dtsi
....@@ -1,10 +1,25 @@
11 // SPDX-License-Identifier: GPL-2.0
22 #include <dt-bindings/clock/jz4740-cgu.h>
3
+#include <dt-bindings/clock/ingenic,tcu.h>
34 
45 / {
56 	#address-cells = <1>;
67 	#size-cells = <1>;
78 	compatible = "ingenic,jz4740";
9
+
10
+	cpus {
11
+		#address-cells = <1>;
12
+		#size-cells = <0>;
13
+
14
+		cpu0: cpu@0 {
15
+			device_type = "cpu";
16
+			compatible = "ingenic,xburst-mxu1.0";
17
+			reg = <0>;
18
+
19
+			clocks = <&cgu JZ4740_CLK_CCLK>;
20
+			clock-names = "cpu";
21
+		};
22
+	};
823 
924 	cpuintc: interrupt-controller {
1025 		#address-cells = <0>;
....@@ -45,12 +60,48 @@
4560 		#clock-cells = <1>;
4661 	};
4762 
48
-	watchdog: watchdog@10002000 {
49
-		compatible = "ingenic,jz4740-watchdog";
50
-		reg = <0x10002000 0x10>;
63
+	tcu: timer@10002000 {
64
+		compatible = "ingenic,jz4740-tcu", "simple-mfd";
65
+		reg = <0x10002000 0x1000>;
66
+		#address-cells = <1>;
67
+		#size-cells = <1>;
68
+		ranges = <0x0 0x10002000 0x1000>;
5169 
52
-		clocks = <&cgu JZ4740_CLK_RTC>;
53
-		clock-names = "rtc";
70
+		#clock-cells = <1>;
71
+
72
+		clocks = <&cgu JZ4740_CLK_RTC>,
73
+			 <&cgu JZ4740_CLK_EXT>,
74
+			 <&cgu JZ4740_CLK_PCLK>,
75
+			 <&cgu JZ4740_CLK_TCU>;
76
+		clock-names = "rtc", "ext", "pclk", "tcu";
77
+
78
+		interrupt-controller;
79
+		#interrupt-cells = <1>;
80
+
81
+		interrupt-parent = <&intc>;
82
+		interrupts = <23 22 21>;
83
+
84
+		watchdog: watchdog@0 {
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+			compatible = "ingenic,jz4740-watchdog";
86
+			reg = <0x0 0xc>;
87
+
88
+			clocks = <&tcu TCU_CLK_WDT>;
89
+			clock-names = "wdt";
90
+		};
91
+
92
+		pwm: pwm@40 {
93
+			compatible = "ingenic,jz4740-pwm";
94
+			reg = <0x40 0x80>;
95
+
96
+			#pwm-cells = <3>;
97
+
98
+			clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
99
+				 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
100
+				 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
101
+				 <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
102
+			clock-names = "timer0", "timer1", "timer2", "timer3",
103
+				      "timer4", "timer5", "timer6", "timer7";
104
+		};
54105 	};
55106 
56107 	rtc_dev: rtc@10003000 {
....@@ -132,6 +183,53 @@
132183 		};
133184 	};
134185 
186
+	aic: audio-controller@10020000 {
187
+		compatible = "ingenic,jz4740-i2s";
188
+		reg = <0x10020000 0x38>;
189
+
190
+		#sound-dai-cells = <0>;
191
+
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+		interrupt-parent = <&intc>;
193
+		interrupts = <18>;
194
+
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+		clocks = <&cgu JZ4740_CLK_AIC>,
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+			 <&cgu JZ4740_CLK_I2S>,
197
+			 <&cgu JZ4740_CLK_EXT>,
198
+			 <&cgu JZ4740_CLK_PLL_HALF>;
199
+		clock-names = "aic", "i2s", "ext", "pll half";
200
+
201
+		dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
202
+		dma-names = "rx", "tx";
203
+	};
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+
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+	codec: audio-codec@100200a4 {
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+		compatible = "ingenic,jz4740-codec";
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+		reg = <0x10020080 0x8>;
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+
209
+		#sound-dai-cells = <0>;
210
+
211
+		clocks = <&cgu JZ4740_CLK_AIC>;
212
+		clock-names = "aic";
213
+	};
214
+
215
+	mmc: mmc@10021000 {
216
+		compatible = "ingenic,jz4740-mmc";
217
+		reg = <0x10021000 0x1000>;
218
+
219
+		clocks = <&cgu JZ4740_CLK_MMC>;
220
+		clock-names = "mmc";
221
+
222
+		interrupt-parent = <&intc>;
223
+		interrupts = <14>;
224
+
225
+		dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
226
+		dma-names = "rx", "tx";
227
+
228
+		cap-sd-highspeed;
229
+		cap-mmc-highspeed;
230
+		cap-sdio-irq;
231
+	};
232
+
135233 	uart0: serial@10030000 {
136234 		compatible = "ingenic,jz4740-uart";
137235 		reg = <0x10030000 0x100>;
....@@ -154,6 +252,49 @@
154252 		clock-names = "baud", "module";
155253 	};
156254 
255
+	adc: adc@10070000 {
256
+		compatible = "ingenic,jz4740-adc";
257
+		reg = <0x10070000 0x30>;
258
+		#io-channel-cells = <1>;
259
+
260
+		clocks = <&cgu JZ4740_CLK_ADC>;
261
+		clock-names = "adc";
262
+
263
+		interrupt-parent = <&intc>;
264
+		interrupts = <12>;
265
+	};
266
+
267
+	nemc: memory-controller@13010000 {
268
+		compatible = "ingenic,jz4740-nemc";
269
+		reg = <0x13010000 0x54>;
270
+		#address-cells = <2>;
271
+		#size-cells = <1>;
272
+		ranges = <1 0 0x18000000 0x4000000>,
273
+			 <2 0 0x14000000 0x4000000>,
274
+			 <3 0 0x0c000000 0x4000000>,
275
+			 <4 0 0x08000000 0x4000000>;
276
+
277
+		clocks = <&cgu JZ4740_CLK_MCLK>;
278
+	};
279
+
280
+	ecc: ecc-controller@13010100 {
281
+		compatible = "ingenic,jz4740-ecc";
282
+		reg = <0x13010100 0x2C>;
283
+
284
+		clocks = <&cgu JZ4740_CLK_MCLK>;
285
+	};
286
+
287
+	dmac: dma-controller@13020000 {
288
+		compatible = "ingenic,jz4740-dma";
289
+		reg = <0x13020000 0xbc>, <0x13020300 0x14>;
290
+		#dma-cells = <2>;
291
+
292
+		interrupt-parent = <&intc>;
293
+		interrupts = <20>;
294
+
295
+		clocks = <&cgu JZ4740_CLK_DMA>;
296
+	};
297
+
157298 	uhc: uhc@13030000 {
158299 		compatible = "ingenic,jz4740-ohci", "generic-ohci";
159300 		reg = <0x13030000 0x1000>;
....@@ -167,4 +308,27 @@
167308 
168309 		status = "disabled";
169310 	};
311
+
312
+	udc: usb@13040000 {
313
+		compatible = "ingenic,jz4740-musb";
314
+		reg = <0x13040000 0x10000>;
315
+
316
+		interrupt-parent = <&intc>;
317
+		interrupts = <24>;
318
+		interrupt-names = "mc";
319
+
320
+		clocks = <&cgu JZ4740_CLK_UDC>;
321
+		clock-names = "udc";
322
+	};
323
+
324
+	lcd: lcd-controller@13050000 {
325
+		compatible = "ingenic,jz4740-lcd";
326
+		reg = <0x13050000 0x1000>;
327
+
328
+		interrupt-parent = <&intc>;
329
+		interrupts = <30>;
330
+
331
+		clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>;
332
+		clock-names = "lcd_pclk", "lcd";
333
+	};
170334 };