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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved. |
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| 3 | 4 | */ |
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| 4 | 5 | |
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| 5 | | -/* |
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| 6 | | - * This program is free software; you can redistribute it and/or modify |
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| 7 | | - * it under the terms of the GNU General Public License version 2 as |
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| 8 | | - * published by the Free Software Foundation. |
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| 9 | | - */ |
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| 10 | 6 | |
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| 11 | 7 | #ifndef __ASM_ARCH_MXC_COMMON_H__ |
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| 12 | 8 | #define __ASM_ARCH_MXC_COMMON_H__ |
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| .. | .. |
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| 21 | 17 | enum mxc_cpu_pwr_mode; |
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| 22 | 18 | struct of_device_id; |
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| 23 | 19 | |
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| 24 | | -void mx21_map_io(void); |
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| 25 | | -void mx27_map_io(void); |
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| 26 | 20 | void mx31_map_io(void); |
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| 27 | 21 | void mx35_map_io(void); |
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| 28 | 22 | void imx21_init_early(void); |
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| 29 | | -void imx27_init_early(void); |
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| 30 | 23 | void imx31_init_early(void); |
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| 31 | 24 | void imx35_init_early(void); |
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| 32 | 25 | void mxc_init_irq(void __iomem *); |
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| 33 | | -void mx21_init_irq(void); |
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| 34 | | -void mx27_init_irq(void); |
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| 35 | 26 | void mx31_init_irq(void); |
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| 36 | 27 | void mx35_init_irq(void); |
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| 37 | | -void imx21_soc_init(void); |
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| 38 | | -void imx27_soc_init(void); |
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| 39 | | -void imx31_soc_init(void); |
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| 40 | | -void imx35_soc_init(void); |
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| 41 | | -int mx21_clocks_init(unsigned long lref, unsigned long fref); |
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| 42 | | -int mx27_clocks_init(unsigned long fref); |
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| 43 | | -int mx31_clocks_init(unsigned long fref); |
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| 44 | | -int mx35_clocks_init(void); |
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| 45 | | -struct platform_device *mxc_register_gpio(char *name, int id, |
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| 46 | | - resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); |
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| 47 | 28 | void mxc_set_cpu_type(unsigned int type); |
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| 48 | 29 | void mxc_restart(enum reboot_mode, const char *); |
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| 49 | 30 | void mxc_arch_reset_init(void __iomem *); |
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| .. | .. |
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| 53 | 34 | int mxc_device_init(void); |
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| 54 | 35 | void imx_set_soc_revision(unsigned int rev); |
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| 55 | 36 | void imx_init_revision_from_anatop(void); |
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| 56 | | -struct device *imx_soc_device_init(void); |
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| 57 | 37 | void imx6_enable_rbc(bool enable); |
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| 58 | 38 | void imx_gpc_check_dt(void); |
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| 59 | 39 | void imx_gpc_set_arm_power_in_lpm(bool power_off); |
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| .. | .. |
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| 70 | 50 | WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */ |
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| 71 | 51 | STOP_POWER_ON, /* just STOP */ |
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| 72 | 52 | STOP_POWER_OFF, /* STOP + SRPG */ |
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| 53 | +}; |
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| 54 | + |
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| 55 | +enum ulp_cpu_pwr_mode { |
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| 56 | + ULP_PM_HSRUN, /* High speed run mode */ |
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| 57 | + ULP_PM_RUN, /* Run mode */ |
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| 58 | + ULP_PM_WAIT, /* Wait mode */ |
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| 59 | + ULP_PM_STOP, /* Stop mode */ |
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| 60 | + ULP_PM_VLPS, /* Very low power stop mode */ |
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| 61 | + ULP_PM_VLLS, /* very low leakage stop mode */ |
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| 73 | 62 | }; |
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| 74 | 63 | |
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| 75 | 64 | void imx_enable_cpu(int cpu, bool enable); |
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| .. | .. |
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| 98 | 87 | void imx6_set_int_mem_clk_lpm(bool enable); |
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| 99 | 88 | void imx6sl_set_wait_clk(bool enter); |
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| 100 | 89 | int imx_mmdc_get_ddr_type(void); |
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| 90 | +int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode); |
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| 101 | 91 | |
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| 102 | 92 | void imx_cpu_die(unsigned int cpu); |
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| 103 | 93 | int imx_cpu_kill(unsigned int cpu); |
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| .. | .. |
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| 120 | 110 | void imx6sl_pm_init(void); |
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| 121 | 111 | void imx6sx_pm_init(void); |
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| 122 | 112 | void imx6ul_pm_init(void); |
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| 113 | +void imx7ulp_pm_init(void); |
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| 123 | 114 | |
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| 124 | 115 | #ifdef CONFIG_PM |
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| 125 | 116 | void imx51_pm_init(void); |
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