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1 | 1 | TI PCI Controllers |
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2 | 2 | |
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3 | 3 | PCIe DesignWare Controller |
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4 | | - - compatible: Should be "ti,dra7-pcie" for RC |
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5 | | - Should be "ti,dra7-pcie-ep" for EP |
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| 4 | + - compatible: Should be "ti,dra7-pcie" for RC (deprecated) |
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| 5 | + Should be "ti,dra7-pcie-ep" for EP (deprecated) |
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| 6 | + Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode |
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| 7 | + Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode |
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| 8 | + Should be "ti,dra726-pcie-rc" for dra72x in RC mode |
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| 9 | + Should be "ti,dra726-pcie-ep" for dra72x in EP mode |
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6 | 10 | - phys : list of PHY specifiers (used by generic PHY framework) |
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7 | 11 | - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the |
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8 | 12 | number of PHYs as specified in *phys* property. |
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9 | 13 | - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>", |
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10 | 14 | where <X> is the instance number of the pcie from the HW spec. |
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11 | 15 | - num-lanes as specified in ../designware-pcie.txt |
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| 16 | + - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control |
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| 17 | + module and the register offset to specify lane |
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| 18 | + selection. |
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12 | 19 | |
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13 | 20 | HOST MODE |
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14 | 21 | ========= |
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.. | .. |
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26 | 33 | ranges, |
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27 | 34 | interrupt-map-mask, |
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28 | 35 | interrupt-map : as specified in ../designware-pcie.txt |
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| 36 | + - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument |
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| 37 | + should contain the register offset within syscon |
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| 38 | + and the 2nd argument should contain the bit field |
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| 39 | + for setting the bit to enable unaligned |
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| 40 | + access. |
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29 | 41 | |
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30 | 42 | DEVICE MODE |
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31 | 43 | =========== |
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