forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-10 cde9070d9970eef1f7ec2360586c802a16230ad8 
 kernel/drivers/tty/serial/ucc_uart.c
....@@ -32,7 +32,11 @@
3232 #include <soc/fsl/qe/ucc_slow.h>
3333 
3434 #include <linux/firmware.h>
35
-#include <asm/reg.h>
35
+#include <soc/fsl/cpm.h>
36
+
37
+#ifdef CONFIG_PPC32
38
+#include <asm/reg.h> /* mfspr, SPRN_SVR */
39
+#endif
3640 
3741 /*
3842  * The GUMR flag for Soft UART.  This would normally be defined in qe.h,
....@@ -257,11 +261,11 @@
257261 	struct qe_bd *bdp = qe_port->tx_bd_base;
258262 
259263 	while (1) {
260
-		if (in_be16(&bdp->status) & BD_SC_READY)
264
+		if (qe_ioread16be(&bdp->status) & BD_SC_READY)
261265 			/* This BD is not done, so return "not done" */
262266 			return 0;
263267 
264
-		if (in_be16(&bdp->status) & BD_SC_WRAP)
268
+		if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
265269 			/*
266270 			 * This BD is done and it's the last one, so return
267271 			 * "done"
....@@ -279,7 +283,7 @@
279283  * don't need that support. This function must exist, however, otherwise
280284  * the kernel will panic.
281285  */
282
-void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
286
+static void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
283287 {
284288 }
285289 
....@@ -307,7 +311,7 @@
307311 	struct uart_qe_port *qe_port =
308312 		container_of(port, struct uart_qe_port, port);
309313 
310
-	clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
314
+	qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
311315 }
312316 
313317 /*
....@@ -332,20 +336,18 @@
332336 	struct uart_port *port = &qe_port->port;
333337 	struct circ_buf *xmit = &port->state->xmit;
334338 
335
-	bdp = qe_port->rx_cur;
336
-
337339 	/* Handle xon/xoff */
338340 	if (port->x_char) {
339341 		/* Pick next descriptor and fill from buffer */
340342 		bdp = qe_port->tx_cur;
341343 
342
-		p = qe2cpu_addr(bdp->buf, qe_port);
344
+		p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
343345 
344346 		*p++ = port->x_char;
345
-		out_be16(&bdp->length, 1);
346
-		setbits16(&bdp->status, BD_SC_READY);
347
+		qe_iowrite16be(1, &bdp->length);
348
+		qe_setbits_be16(&bdp->status, BD_SC_READY);
347349 		/* Get next BD. */
348
-		if (in_be16(&bdp->status) & BD_SC_WRAP)
350
+		if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
349351 			bdp = qe_port->tx_bd_base;
350352 		else
351353 			bdp++;
....@@ -364,10 +366,10 @@
364366 	/* Pick next descriptor and fill from buffer */
365367 	bdp = qe_port->tx_cur;
366368 
367
-	while (!(in_be16(&bdp->status) & BD_SC_READY) &&
369
+	while (!(qe_ioread16be(&bdp->status) & BD_SC_READY) &&
368370 	       (xmit->tail != xmit->head)) {
369371 		count = 0;
370
-		p = qe2cpu_addr(bdp->buf, qe_port);
372
+		p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
371373 		while (count < qe_port->tx_fifosize) {
372374 			*p++ = xmit->buf[xmit->tail];
373375 			xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
....@@ -377,11 +379,11 @@
377379 				break;
378380 		}
379381 
380
-		out_be16(&bdp->length, count);
381
-		setbits16(&bdp->status, BD_SC_READY);
382
+		qe_iowrite16be(count, &bdp->length);
383
+		qe_setbits_be16(&bdp->status, BD_SC_READY);
382384 
383385 		/* Get next BD. */
384
-		if (in_be16(&bdp->status) & BD_SC_WRAP)
386
+		if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
385387 			bdp = qe_port->tx_bd_base;
386388 		else
387389 			bdp++;
....@@ -414,12 +416,12 @@
414416 		container_of(port, struct uart_qe_port, port);
415417 
416418 	/* If we currently are transmitting, then just return */
417
-	if (in_be16(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
419
+	if (qe_ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
418420 		return;
419421 
420422 	/* Otherwise, pump the port and start transmission */
421423 	if (qe_uart_tx_pump(qe_port))
422
-		setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
424
+		qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
423425 }
424426 
425427 /*
....@@ -430,7 +432,7 @@
430432 	struct uart_qe_port *qe_port =
431433 		container_of(port, struct uart_qe_port, port);
432434 
433
-	clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
435
+	qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
434436 }
435437 
436438 /* Start or stop sending  break signal
....@@ -469,14 +471,14 @@
469471 	 */
470472 	bdp = qe_port->rx_cur;
471473 	while (1) {
472
-		status = in_be16(&bdp->status);
474
+		status = qe_ioread16be(&bdp->status);
473475 
474476 		/* If this one is empty, then we assume we've read them all */
475477 		if (status & BD_SC_EMPTY)
476478 			break;
477479 
478480 		/* get number of characters, and check space in RX buffer */
479
-		i = in_be16(&bdp->length);
481
+		i = qe_ioread16be(&bdp->length);
480482 
481483 		/* If we don't have enough room in RX buffer for the entire BD,
482484 		 * then we try later, which will be the next RX interrupt.
....@@ -487,7 +489,7 @@
487489 		}
488490 
489491 		/* get pointer */
490
-		cp = qe2cpu_addr(bdp->buf, qe_port);
492
+		cp = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
491493 
492494 		/* loop through the buffer */
493495 		while (i-- > 0) {
....@@ -507,9 +509,10 @@
507509 		}
508510 
509511 		/* This BD is ready to be used again. Clear status. get next */
510
-		clrsetbits_be16(&bdp->status, BD_SC_BR | BD_SC_FR | BD_SC_PR |
511
-			BD_SC_OV | BD_SC_ID, BD_SC_EMPTY);
512
-		if (in_be16(&bdp->status) & BD_SC_WRAP)
512
+		qe_clrsetbits_be16(&bdp->status,
513
+				   BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID,
514
+				   BD_SC_EMPTY);
515
+		if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
513516 			bdp = qe_port->rx_bd_base;
514517 		else
515518 			bdp++;
....@@ -551,9 +554,7 @@
551554 	/* Overrun does not affect the current character ! */
552555 	if (status & BD_SC_OV)
553556 		tty_insert_flip_char(tport, 0, TTY_OVERRUN);
554
-#ifdef SUPPORT_SYSRQ
555557 	port->sysrq = 0;
556
-#endif
557558 	goto error_return;
558559 }
559560 
....@@ -568,8 +569,8 @@
568569 	u16 events;
569570 
570571 	/* Clear the interrupts */
571
-	events = in_be16(&uccp->ucce);
572
-	out_be16(&uccp->ucce, events);
572
+	events = qe_ioread16be(&uccp->ucce);
573
+	qe_iowrite16be(events, &uccp->ucce);
573574 
574575 	if (events & UCC_UART_UCCE_BRKE)
575576 		uart_handle_break(&qe_port->port);
....@@ -600,17 +601,17 @@
600601 	bdp = qe_port->rx_bd_base;
601602 	qe_port->rx_cur = qe_port->rx_bd_base;
602603 	for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
603
-		out_be16(&bdp->status, BD_SC_EMPTY | BD_SC_INTRPT);
604
-		out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
605
-		out_be16(&bdp->length, 0);
604
+		qe_iowrite16be(BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
605
+		qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
606
+		qe_iowrite16be(0, &bdp->length);
606607 		bd_virt += qe_port->rx_fifosize;
607608 		bdp++;
608609 	}
609610 
610611 	/* */
611
-	out_be16(&bdp->status, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
612
-	out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
613
-	out_be16(&bdp->length, 0);
612
+	qe_iowrite16be(BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
613
+	qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
614
+	qe_iowrite16be(0, &bdp->length);
614615 
615616 	/* Set the physical address of the host memory
616617 	 * buffers in the buffer descriptors, and the
....@@ -621,21 +622,21 @@
621622 	qe_port->tx_cur = qe_port->tx_bd_base;
622623 	bdp = qe_port->tx_bd_base;
623624 	for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
624
-		out_be16(&bdp->status, BD_SC_INTRPT);
625
-		out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
626
-		out_be16(&bdp->length, 0);
625
+		qe_iowrite16be(BD_SC_INTRPT, &bdp->status);
626
+		qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
627
+		qe_iowrite16be(0, &bdp->length);
627628 		bd_virt += qe_port->tx_fifosize;
628629 		bdp++;
629630 	}
630631 
631632 	/* Loopback requires the preamble bit to be set on the first TX BD */
632633 #ifdef LOOPBACK
633
-	setbits16(&qe_port->tx_cur->status, BD_SC_P);
634
+	qe_setbits_be16(&qe_port->tx_cur->status, BD_SC_P);
634635 #endif
635636 
636
-	out_be16(&bdp->status, BD_SC_WRAP | BD_SC_INTRPT);
637
-	out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
638
-	out_be16(&bdp->length, 0);
637
+	qe_iowrite16be(BD_SC_WRAP | BD_SC_INTRPT, &bdp->status);
638
+	qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
639
+	qe_iowrite16be(0, &bdp->length);
639640 }
640641 
641642 /*
....@@ -657,78 +658,74 @@
657658 	ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
658659 
659660 	/* Program the UCC UART parameter RAM */
660
-	out_8(&uccup->common.rbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
661
-	out_8(&uccup->common.tbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
662
-	out_be16(&uccup->common.mrblr, qe_port->rx_fifosize);
663
-	out_be16(&uccup->maxidl, 0x10);
664
-	out_be16(&uccup->brkcr, 1);
665
-	out_be16(&uccup->parec, 0);
666
-	out_be16(&uccup->frmec, 0);
667
-	out_be16(&uccup->nosec, 0);
668
-	out_be16(&uccup->brkec, 0);
669
-	out_be16(&uccup->uaddr[0], 0);
670
-	out_be16(&uccup->uaddr[1], 0);
671
-	out_be16(&uccup->toseq, 0);
661
+	qe_iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.rbmr);
662
+	qe_iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.tbmr);
663
+	qe_iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr);
664
+	qe_iowrite16be(0x10, &uccup->maxidl);
665
+	qe_iowrite16be(1, &uccup->brkcr);
666
+	qe_iowrite16be(0, &uccup->parec);
667
+	qe_iowrite16be(0, &uccup->frmec);
668
+	qe_iowrite16be(0, &uccup->nosec);
669
+	qe_iowrite16be(0, &uccup->brkec);
670
+	qe_iowrite16be(0, &uccup->uaddr[0]);
671
+	qe_iowrite16be(0, &uccup->uaddr[1]);
672
+	qe_iowrite16be(0, &uccup->toseq);
672673 	for (i = 0; i < 8; i++)
673
-		out_be16(&uccup->cchars[i], 0xC000);
674
-	out_be16(&uccup->rccm, 0xc0ff);
674
+		qe_iowrite16be(0xC000, &uccup->cchars[i]);
675
+	qe_iowrite16be(0xc0ff, &uccup->rccm);
675676 
676677 	/* Configure the GUMR registers for UART */
677678 	if (soft_uart) {
678679 		/* Soft-UART requires a 1X multiplier for TX */
679
-		clrsetbits_be32(&uccp->gumr_l,
680
-			UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
681
-			UCC_SLOW_GUMR_L_RDCR_MASK,
682
-			UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 |
683
-			UCC_SLOW_GUMR_L_RDCR_16);
680
+		qe_clrsetbits_be32(&uccp->gumr_l,
681
+				   UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
682
+				   UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 | UCC_SLOW_GUMR_L_RDCR_16);
684683 
685
-		clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
686
-			UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
684
+		qe_clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
685
+				   UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
687686 	} else {
688
-		clrsetbits_be32(&uccp->gumr_l,
689
-			UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
690
-			UCC_SLOW_GUMR_L_RDCR_MASK,
691
-			UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 |
692
-			UCC_SLOW_GUMR_L_RDCR_16);
687
+		qe_clrsetbits_be32(&uccp->gumr_l,
688
+				   UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
689
+				   UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);
693690 
694
-		clrsetbits_be32(&uccp->gumr_h,
695
-			UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
696
-			UCC_SLOW_GUMR_H_RFW);
691
+		qe_clrsetbits_be32(&uccp->gumr_h,
692
+				   UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
693
+				   UCC_SLOW_GUMR_H_RFW);
697694 	}
698695 
699696 #ifdef LOOPBACK
700
-	clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
701
-		UCC_SLOW_GUMR_L_DIAG_LOOP);
702
-	clrsetbits_be32(&uccp->gumr_h,
703
-		UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
704
-		UCC_SLOW_GUMR_H_CDS);
697
+	qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
698
+			   UCC_SLOW_GUMR_L_DIAG_LOOP);
699
+	qe_clrsetbits_be32(&uccp->gumr_h,
700
+			   UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
701
+			   UCC_SLOW_GUMR_H_CDS);
705702 #endif
706703 
707704 	/* Disable rx interrupts  and clear all pending events.  */
708
-	out_be16(&uccp->uccm, 0);
709
-	out_be16(&uccp->ucce, 0xffff);
710
-	out_be16(&uccp->udsr, 0x7e7e);
705
+	qe_iowrite16be(0, &uccp->uccm);
706
+	qe_iowrite16be(0xffff, &uccp->ucce);
707
+	qe_iowrite16be(0x7e7e, &uccp->udsr);
711708 
712709 	/* Initialize UPSMR */
713
-	out_be16(&uccp->upsmr, 0);
710
+	qe_iowrite16be(0, &uccp->upsmr);
714711 
715712 	if (soft_uart) {
716
-		out_be16(&uccup->supsmr, 0x30);
717
-		out_be16(&uccup->res92, 0);
718
-		out_be32(&uccup->rx_state, 0);
719
-		out_be32(&uccup->rx_cnt, 0);
720
-		out_8(&uccup->rx_bitmark, 0);
721
-		out_8(&uccup->rx_length, 10);
722
-		out_be32(&uccup->dump_ptr, 0x4000);
723
-		out_8(&uccup->rx_temp_dlst_qe, 0);
724
-		out_be32(&uccup->rx_frame_rem, 0);
725
-		out_8(&uccup->rx_frame_rem_size, 0);
713
+		qe_iowrite16be(0x30, &uccup->supsmr);
714
+		qe_iowrite16be(0, &uccup->res92);
715
+		qe_iowrite32be(0, &uccup->rx_state);
716
+		qe_iowrite32be(0, &uccup->rx_cnt);
717
+		qe_iowrite8(0, &uccup->rx_bitmark);
718
+		qe_iowrite8(10, &uccup->rx_length);
719
+		qe_iowrite32be(0x4000, &uccup->dump_ptr);
720
+		qe_iowrite8(0, &uccup->rx_temp_dlst_qe);
721
+		qe_iowrite32be(0, &uccup->rx_frame_rem);
722
+		qe_iowrite8(0, &uccup->rx_frame_rem_size);
726723 		/* Soft-UART requires TX to be 1X */
727
-		out_8(&uccup->tx_mode,
728
-			UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1);
729
-		out_be16(&uccup->tx_state, 0);
730
-		out_8(&uccup->resD4, 0);
731
-		out_be16(&uccup->resD5, 0);
724
+		qe_iowrite8(UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1,
725
+			    &uccup->tx_mode);
726
+		qe_iowrite16be(0, &uccup->tx_state);
727
+		qe_iowrite8(0, &uccup->resD4);
728
+		qe_iowrite16be(0, &uccup->resD5);
732729 
733730 		/* Set UART mode.
734731 		 * Enable receive and transmit.
....@@ -742,22 +739,19 @@
742739 		 * ...
743740 		 * 6.Receiver must use 16x over sampling
744741 		 */
745
-		clrsetbits_be32(&uccp->gumr_l,
746
-			UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
747
-			UCC_SLOW_GUMR_L_RDCR_MASK,
748
-			UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 |
749
-			UCC_SLOW_GUMR_L_RDCR_16);
742
+		qe_clrsetbits_be32(&uccp->gumr_l,
743
+				   UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
744
+				   UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);
750745 
751
-		clrsetbits_be32(&uccp->gumr_h,
752
-			UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
753
-			UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX |
754
-			UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);
746
+		qe_clrsetbits_be32(&uccp->gumr_h,
747
+				   UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
748
+				   UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);
755749 
756750 #ifdef LOOPBACK
757
-		clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
758
-				UCC_SLOW_GUMR_L_DIAG_LOOP);
759
-		clrbits32(&uccp->gumr_h, UCC_SLOW_GUMR_H_CTSP |
760
-			  UCC_SLOW_GUMR_H_CDS);
751
+		qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
752
+				   UCC_SLOW_GUMR_L_DIAG_LOOP);
753
+		qe_clrbits_be32(&uccp->gumr_h,
754
+				UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_CDS);
761755 #endif
762756 
763757 		cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
....@@ -800,7 +794,7 @@
800794 	}
801795 
802796 	/* Startup rx-int */
803
-	setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
797
+	qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
804798 	ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);
805799 
806800 	return 0;
....@@ -836,7 +830,7 @@
836830 
837831 	/* Stop uarts */
838832 	ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
839
-	clrbits16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);
833
+	qe_clrbits_be16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);
840834 
841835 	/* Shut them really down and reinit buffer descriptors */
842836 	ucc_slow_graceful_stop_tx(qe_port->us_private);
....@@ -856,9 +850,9 @@
856850 	struct ucc_slow __iomem *uccp = qe_port->uccp;
857851 	unsigned int baud;
858852 	unsigned long flags;
859
-	u16 upsmr = in_be16(&uccp->upsmr);
853
+	u16 upsmr = qe_ioread16be(&uccp->upsmr);
860854 	struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
861
-	u16 supsmr = in_be16(&uccup->supsmr);
855
+	u16 supsmr = qe_ioread16be(&uccup->supsmr);
862856 	u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */
863857 
864858 	/* Character length programmed into the mode register is the
....@@ -956,10 +950,10 @@
956950 	/* Update the per-port timeout. */
957951 	uart_update_timeout(port, termios->c_cflag, baud);
958952 
959
-	out_be16(&uccp->upsmr, upsmr);
953
+	qe_iowrite16be(upsmr, &uccp->upsmr);
960954 	if (soft_uart) {
961
-		out_be16(&uccup->supsmr, supsmr);
962
-		out_8(&uccup->rx_length, char_length);
955
+		qe_iowrite16be(supsmr, &uccup->supsmr);
956
+		qe_iowrite8(char_length, &uccup->rx_length);
963957 
964958 		/* Soft-UART requires a 1X multiplier for TX */
965959 		qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
....@@ -1081,7 +1075,7 @@
10811075 }
10821076 /* UART operations
10831077  *
1084
- * Details on these functions can be found in Documentation/serial/driver
1078
+ * Details on these functions can be found in Documentation/driver-api/serial/driver.rst
10851079  */
10861080 static const struct uart_ops qe_uart_pops = {
10871081 	.tx_empty       = qe_uart_tx_empty,
....@@ -1101,6 +1095,8 @@
11011095 	.verify_port    = qe_uart_verify_port,
11021096 };
11031097 
1098
+
1099
+#ifdef CONFIG_PPC32
11041100 /*
11051101  * Obtain the SOC model number and revision level
11061102  *
....@@ -1140,6 +1136,8 @@
11401136 	if (!soc_string)
11411137 		/* No compatible property, so try the name. */
11421138 		soc_string = np->name;
1139
+
1140
+	of_node_put(np);
11431141 
11441142 	/* Extract the SOC number from the "PowerPC," string */
11451143 	if ((sscanf(soc_string, "PowerPC,%u", &soc) != 1) || !soc)
....@@ -1188,70 +1186,86 @@
11881186 	release_firmware(fw);
11891187 }
11901188 
1189
+static int soft_uart_init(struct platform_device *ofdev)
1190
+{
1191
+	struct device_node *np = ofdev->dev.of_node;
1192
+	struct qe_firmware_info *qe_fw_info;
1193
+	int ret;
1194
+
1195
+	if (of_find_property(np, "soft-uart", NULL)) {
1196
+		dev_dbg(&ofdev->dev, "using Soft-UART mode\n");
1197
+		soft_uart = 1;
1198
+	} else {
1199
+		return 0;
1200
+	}
1201
+
1202
+	qe_fw_info = qe_get_firmware_info();
1203
+
1204
+	/* Check if the firmware has been uploaded. */
1205
+	if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
1206
+		firmware_loaded = 1;
1207
+	} else {
1208
+		char filename[32];
1209
+		unsigned int soc;
1210
+		unsigned int rev_h;
1211
+		unsigned int rev_l;
1212
+
1213
+		soc = soc_info(&rev_h, &rev_l);
1214
+		if (!soc) {
1215
+			dev_err(&ofdev->dev, "unknown CPU model\n");
1216
+			return -ENXIO;
1217
+		}
1218
+		sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
1219
+			soc, rev_h, rev_l);
1220
+
1221
+		dev_info(&ofdev->dev, "waiting for firmware %s\n",
1222
+			 filename);
1223
+
1224
+		/*
1225
+		 * We call request_firmware_nowait instead of
1226
+		 * request_firmware so that the driver can load and
1227
+		 * initialize the ports without holding up the rest of
1228
+		 * the kernel.  If hotplug support is enabled in the
1229
+		 * kernel, then we use it.
1230
+		 */
1231
+		ret = request_firmware_nowait(THIS_MODULE,
1232
+					      FW_ACTION_HOTPLUG, filename, &ofdev->dev,
1233
+					      GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
1234
+		if (ret) {
1235
+			dev_err(&ofdev->dev,
1236
+				"could not load firmware %s\n",
1237
+				filename);
1238
+			return ret;
1239
+		}
1240
+	}
1241
+	return 0;
1242
+}
1243
+
1244
+#else /* !CONFIG_PPC32 */
1245
+
1246
+static int soft_uart_init(struct platform_device *ofdev)
1247
+{
1248
+	return 0;
1249
+}
1250
+
1251
+#endif
1252
+
1253
+
11911254 static int ucc_uart_probe(struct platform_device *ofdev)
11921255 {
11931256 	struct device_node *np = ofdev->dev.of_node;
1194
-	const unsigned int *iprop;      /* Integer OF properties */
11951257 	const char *sprop;      /* String OF properties */
11961258 	struct uart_qe_port *qe_port = NULL;
11971259 	struct resource res;
1260
+	u32 val;
11981261 	int ret;
11991262 
12001263 	/*
12011264 	 * Determine if we need Soft-UART mode
12021265 	 */
1203
-	if (of_find_property(np, "soft-uart", NULL)) {
1204
-		dev_dbg(&ofdev->dev, "using Soft-UART mode\n");
1205
-		soft_uart = 1;
1206
-	}
1207
-
1208
-	/*
1209
-	 * If we are using Soft-UART, determine if we need to upload the
1210
-	 * firmware, too.
1211
-	 */
1212
-	if (soft_uart) {
1213
-		struct qe_firmware_info *qe_fw_info;
1214
-
1215
-		qe_fw_info = qe_get_firmware_info();
1216
-
1217
-		/* Check if the firmware has been uploaded. */
1218
-		if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
1219
-			firmware_loaded = 1;
1220
-		} else {
1221
-			char filename[32];
1222
-			unsigned int soc;
1223
-			unsigned int rev_h;
1224
-			unsigned int rev_l;
1225
-
1226
-			soc = soc_info(&rev_h, &rev_l);
1227
-			if (!soc) {
1228
-				dev_err(&ofdev->dev, "unknown CPU model\n");
1229
-				return -ENXIO;
1230
-			}
1231
-			sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
1232
-				soc, rev_h, rev_l);
1233
-
1234
-			dev_info(&ofdev->dev, "waiting for firmware %s\n",
1235
-				filename);
1236
-
1237
-			/*
1238
-			 * We call request_firmware_nowait instead of
1239
-			 * request_firmware so that the driver can load and
1240
-			 * initialize the ports without holding up the rest of
1241
-			 * the kernel.  If hotplug support is enabled in the
1242
-			 * kernel, then we use it.
1243
-			 */
1244
-			ret = request_firmware_nowait(THIS_MODULE,
1245
-				FW_ACTION_HOTPLUG, filename, &ofdev->dev,
1246
-				GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
1247
-			if (ret) {
1248
-				dev_err(&ofdev->dev,
1249
-					"could not load firmware %s\n",
1250
-					filename);
1251
-				return ret;
1252
-			}
1253
-		}
1254
-	}
1266
+	ret = soft_uart_init(ofdev);
1267
+	if (ret)
1268
+		return ret;
12551269 
12561270 	qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL);
12571271 	if (!qe_port) {
....@@ -1274,23 +1288,20 @@
12741288 
12751289 	/* Get the UCC number (device ID) */
12761290 	/* UCCs are numbered 1-7 */
1277
-	iprop = of_get_property(np, "cell-index", NULL);
1278
-	if (!iprop) {
1279
-		iprop = of_get_property(np, "device-id", NULL);
1280
-		if (!iprop) {
1281
-			dev_err(&ofdev->dev, "UCC is unspecified in "
1282
-				"device tree\n");
1291
+	if (of_property_read_u32(np, "cell-index", &val)) {
1292
+		if (of_property_read_u32(np, "device-id", &val)) {
1293
+			dev_err(&ofdev->dev, "UCC is unspecified in device tree\n");
12831294 			ret = -EINVAL;
12841295 			goto out_free;
12851296 		}
12861297 	}
12871298 
1288
-	if ((*iprop < 1) || (*iprop > UCC_MAX_NUM)) {
1289
-		dev_err(&ofdev->dev, "no support for UCC%u\n", *iprop);
1299
+	if (val < 1 || val > UCC_MAX_NUM) {
1300
+		dev_err(&ofdev->dev, "no support for UCC%u\n", val);
12901301 		ret = -ENODEV;
12911302 		goto out_free;
12921303 	}
1293
-	qe_port->ucc_num = *iprop - 1;
1304
+	qe_port->ucc_num = val - 1;
12941305 
12951306 	/*
12961307 	 * In the future, we should not require the BRG to be specified in the
....@@ -1334,13 +1345,12 @@
13341345 	}
13351346 
13361347 	/* Get the port number, numbered 0-3 */
1337
-	iprop = of_get_property(np, "port-number", NULL);
1338
-	if (!iprop) {
1348
+	if (of_property_read_u32(np, "port-number", &val)) {
13391349 		dev_err(&ofdev->dev, "missing port-number in device tree\n");
13401350 		ret = -EINVAL;
13411351 		goto out_free;
13421352 	}
1343
-	qe_port->port.line = *iprop;
1353
+	qe_port->port.line = val;
13441354 	if (qe_port->port.line >= UCC_MAX_UART) {
13451355 		dev_err(&ofdev->dev, "port-number must be 0-%u\n",
13461356 			UCC_MAX_UART - 1);
....@@ -1370,31 +1380,36 @@
13701380 		}
13711381 	}
13721382 
1373
-	iprop = of_get_property(np, "brg-frequency", NULL);
1374
-	if (!iprop) {
1383
+	if (of_property_read_u32(np, "brg-frequency", &val)) {
13751384 		dev_err(&ofdev->dev,
13761385 		       "missing brg-frequency in device tree\n");
13771386 		ret = -EINVAL;
13781387 		goto out_np;
13791388 	}
13801389 
1381
-	if (*iprop)
1382
-		qe_port->port.uartclk = *iprop;
1390
+	if (val)
1391
+		qe_port->port.uartclk = val;
13831392 	else {
1393
+		if (!IS_ENABLED(CONFIG_PPC32)) {
1394
+			dev_err(&ofdev->dev,
1395
+				"invalid brg-frequency in device tree\n");
1396
+			ret = -EINVAL;
1397
+			goto out_np;
1398
+		}
1399
+
13841400 		/*
13851401 		 * Older versions of U-Boot do not initialize the brg-frequency
13861402 		 * property, so in this case we assume the BRG frequency is
13871403 		 * half the QE bus frequency.
13881404 		 */
1389
-		iprop = of_get_property(np, "bus-frequency", NULL);
1390
-		if (!iprop) {
1405
+		if (of_property_read_u32(np, "bus-frequency", &val)) {
13911406 			dev_err(&ofdev->dev,
13921407 				"missing QE bus-frequency in device tree\n");
13931408 			ret = -EINVAL;
13941409 			goto out_np;
13951410 		}
1396
-		if (*iprop)
1397
-			qe_port->port.uartclk = *iprop / 2;
1411
+		if (val)
1412
+			qe_port->port.uartclk = val / 2;
13981413 		else {
13991414 			dev_err(&ofdev->dev,
14001415 				"invalid QE bus-frequency in device tree\n");