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2024-05-10 cde9070d9970eef1f7ec2360586c802a16230ad8 
 kernel/drivers/pci/controller/pcie-iproc.c
....@@ -60,6 +60,10 @@
6060 #define APB_ERR_EN_SHIFT		0
6161 #define APB_ERR_EN			BIT(APB_ERR_EN_SHIFT)
6262 
63
+#define CFG_RD_SUCCESS			0
64
+#define CFG_RD_UR			1
65
+#define CFG_RD_CRS			2
66
+#define CFG_RD_CA			3
6367 #define CFG_RETRY_STATUS		0xffff0001
6468 #define CFG_RETRY_STATUS_TIMEOUT_US	500000 /* 500 milliseconds */
6569 
....@@ -159,7 +163,7 @@
159163  * @size_unit: inbound mapping region size unit, could be SZ_1K, SZ_1M, or
160164  * SZ_1G
161165  * @region_sizes: list of supported inbound mapping region sizes in KB, MB, or
162
- * GB, depedning on the size unit
166
+ * GB, depending on the size unit
163167  * @nr_sizes: number of supported inbound mapping region sizes
164168  * @nr_windows: number of supported inbound mapping windows for the region
165169  * @imap_addr_offset: register offset between the upper and lower 32-bit
....@@ -188,8 +192,15 @@
188192 		.imap_window_offset = 0x4,
189193 	},
190194 	{
191
-		/* IARR1/IMAP1 (currently unused) */
192
-		.type = IPROC_PCIE_IB_MAP_INVALID,
195
+		/* IARR1/IMAP1 */
196
+		.type = IPROC_PCIE_IB_MAP_MEM,
197
+		.size_unit = SZ_1M,
198
+		.region_sizes = { 8 },
199
+		.nr_sizes = 1,
200
+		.nr_windows = 8,
201
+		.imap_addr_offset = 0x4,
202
+		.imap_window_offset = 0x8,
203
+
193204 	},
194205 	{
195206 		/* IARR2/IMAP2 */
....@@ -289,6 +300,9 @@
289300 	IPROC_PCIE_IARR4,
290301 	IPROC_PCIE_IMAP4,
291302 
303
+	/* config read status */
304
+	IPROC_PCIE_CFG_RD_STATUS,
305
+
292306 	/* link status */
293307 	IPROC_PCIE_LINK_STATUS,
294308 
....@@ -344,12 +358,15 @@
344358 	[IPROC_PCIE_OMAP3]		= 0xdf8,
345359 	[IPROC_PCIE_IARR0]		= 0xd00,
346360 	[IPROC_PCIE_IMAP0]		= 0xc00,
361
+	[IPROC_PCIE_IARR1]		= 0xd08,
362
+	[IPROC_PCIE_IMAP1]		= 0xd70,
347363 	[IPROC_PCIE_IARR2]		= 0xd10,
348364 	[IPROC_PCIE_IMAP2]		= 0xcc0,
349365 	[IPROC_PCIE_IARR3]		= 0xe00,
350366 	[IPROC_PCIE_IMAP3]		= 0xe08,
351367 	[IPROC_PCIE_IARR4]		= 0xe68,
352368 	[IPROC_PCIE_IMAP4]		= 0xe70,
369
+	[IPROC_PCIE_CFG_RD_STATUS]	= 0xee0,
353370 	[IPROC_PCIE_LINK_STATUS]	= 0xf0c,
354371 	[IPROC_PCIE_APB_ERR_EN]		= 0xf40,
355372 };
....@@ -474,10 +491,12 @@
474491 	return (pcie->base + offset);
475492 }
476493 
477
-static unsigned int iproc_pcie_cfg_retry(void __iomem *cfg_data_p)
494
+static unsigned int iproc_pcie_cfg_retry(struct iproc_pcie *pcie,
495
+					 void __iomem *cfg_data_p)
478496 {
479497 	int timeout = CFG_RETRY_STATUS_TIMEOUT_US;
480498 	unsigned int data;
499
+	u32 status;
481500 
482501 	/*
483502 	 * As per PCIe spec r3.1, sec 2.3.2, CRS Software Visibility only
....@@ -498,6 +517,15 @@
498517 	 */
499518 	data = readl(cfg_data_p);
500519 	while (data == CFG_RETRY_STATUS && timeout--) {
520
+		/*
521
+		 * CRS state is set in CFG_RD status register
522
+		 * This will handle the case where CFG_RETRY_STATUS is
523
+		 * valid config data.
524
+		 */
525
+		status = iproc_pcie_read_reg(pcie, IPROC_PCIE_CFG_RD_STATUS);
526
+		if (status != CFG_RD_CRS)
527
+			return data;
528
+
501529 		udelay(1);
502530 		data = readl(cfg_data_p);
503531 	}
....@@ -576,7 +604,7 @@
576604 	if (!cfg_data_p)
577605 		return PCIBIOS_DEVICE_NOT_FOUND;
578606 
579
-	data = iproc_pcie_cfg_retry(cfg_data_p);
607
+	data = iproc_pcie_cfg_retry(pcie, cfg_data_p);
580608 
581609 	*val = data;
582610 	if (size <= 2)
....@@ -936,8 +964,25 @@
936964 			resource_size_t window_size =
937965 				ob_map->window_sizes[size_idx] * SZ_1M;
938966 
939
-			if (size < window_size)
940
-				continue;
967
+			/*
968
+			 * Keep iterating until we reach the last window and
969
+			 * with the minimal window size at index zero. In this
970
+			 * case, we take a compromise by mapping it using the
971
+			 * minimum window size that can be supported
972
+			 */
973
+			if (size < window_size) {
974
+				if (size_idx > 0 || window_idx > 0)
975
+					continue;
976
+
977
+				/*
978
+				 * For the corner case of reaching the minimal
979
+				 * window size that can be supported on the
980
+				 * last window
981
+				 */
982
+				axi_addr = ALIGN_DOWN(axi_addr, window_size);
983
+				pci_addr = ALIGN_DOWN(pci_addr, window_size);
984
+				size = window_size;
985
+			}
941986 
942987 			if (!IS_ALIGNED(axi_addr, window_size) ||
943988 			    !IS_ALIGNED(pci_addr, window_size)) {
....@@ -1086,15 +1131,16 @@
10861131 }
10871132 
10881133 static int iproc_pcie_setup_ib(struct iproc_pcie *pcie,
1089
-			       struct of_pci_range *range,
1134
+			       struct resource_entry *entry,
10901135 			       enum iproc_pcie_ib_map_type type)
10911136 {
10921137 	struct device *dev = pcie->dev;
10931138 	struct iproc_pcie_ib *ib = &pcie->ib;
10941139 	int ret;
10951140 	unsigned int region_idx, size_idx;
1096
-	u64 axi_addr = range->cpu_addr, pci_addr = range->pci_addr;
1097
-	resource_size_t size = range->size;
1141
+	u64 axi_addr = entry->res->start;
1142
+	u64 pci_addr = entry->res->start - entry->offset;
1143
+	resource_size_t size = resource_size(entry->res);
10981144 
10991145 	/* iterate through all IARR mapping regions */
11001146 	for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) {
....@@ -1148,23 +1194,44 @@
11481194 
11491195 static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie)
11501196 {
1151
-	struct of_pci_range range;
1152
-	struct of_pci_range_parser parser;
1153
-	int ret;
1197
+	struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1198
+	struct resource_entry *entry;
1199
+	int ret = 0;
11541200 
1155
-	/* Get the dma-ranges from DT */
1156
-	ret = of_pci_dma_range_parser_init(&parser, pcie->dev->of_node);
1157
-	if (ret)
1158
-		return ret;
1159
-
1160
-	for_each_of_pci_range(&parser, &range) {
1201
+	resource_list_for_each_entry(entry, &host->dma_ranges) {
11611202 		/* Each range entry corresponds to an inbound mapping region */
1162
-		ret = iproc_pcie_setup_ib(pcie, &range, IPROC_PCIE_IB_MAP_MEM);
1203
+		ret = iproc_pcie_setup_ib(pcie, entry, IPROC_PCIE_IB_MAP_MEM);
11631204 		if (ret)
1164
-			return ret;
1205
+			break;
11651206 	}
11661207 
1167
-	return 0;
1208
+	return ret;
1209
+}
1210
+
1211
+static void iproc_pcie_invalidate_mapping(struct iproc_pcie *pcie)
1212
+{
1213
+	struct iproc_pcie_ib *ib = &pcie->ib;
1214
+	struct iproc_pcie_ob *ob = &pcie->ob;
1215
+	int idx;
1216
+
1217
+	if (pcie->ep_is_internal)
1218
+		return;
1219
+
1220
+	if (pcie->need_ob_cfg) {
1221
+		/* iterate through all OARR mapping regions */
1222
+		for (idx = ob->nr_windows - 1; idx >= 0; idx--) {
1223
+			iproc_pcie_write_reg(pcie,
1224
+					     MAP_REG(IPROC_PCIE_OARR0, idx), 0);
1225
+		}
1226
+	}
1227
+
1228
+	if (pcie->need_ib_cfg) {
1229
+		/* iterate through all IARR mapping regions */
1230
+		for (idx = 0; idx < ib->nr_regions; idx++) {
1231
+			iproc_pcie_write_reg(pcie,
1232
+					     MAP_REG(IPROC_PCIE_IARR0, idx), 0);
1233
+		}
1234
+	}
11681235 }
11691236 
11701237 static int iproce_pcie_get_msi(struct iproc_pcie *pcie,
....@@ -1198,13 +1265,16 @@
11981265 static int iproc_pcie_paxb_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr)
11991266 {
12001267 	int ret;
1201
-	struct of_pci_range range;
1268
+	struct resource_entry entry;
12021269 
1203
-	memset(&range, 0, sizeof(range));
1204
-	range.size = SZ_32K;
1205
-	range.pci_addr = range.cpu_addr = msi_addr & ~(range.size - 1);
1270
+	memset(&entry, 0, sizeof(entry));
1271
+	entry.res = &entry.__res;
12061272 
1207
-	ret = iproc_pcie_setup_ib(pcie, &range, IPROC_PCIE_IB_MAP_IO);
1273
+	msi_addr &= ~(SZ_32K - 1);
1274
+	entry.res->start = msi_addr;
1275
+	entry.res->end = msi_addr + SZ_32K - 1;
1276
+
1277
+	ret = iproc_pcie_setup_ib(pcie, &entry, IPROC_PCIE_IB_MAP_IO);
12081278 	return ret;
12091279 }
12101280 
....@@ -1320,14 +1390,18 @@
13201390 	if (pcie->need_msi_steer) {
13211391 		ret = iproc_pcie_msi_steer(pcie, msi_node);
13221392 		if (ret)
1323
-			return ret;
1393
+			goto out_put_node;
13241394 	}
13251395 
13261396 	/*
13271397 	 * If another MSI controller is being used, the call below should fail
13281398 	 * but that is okay
13291399 	 */
1330
-	return iproc_msi_init(pcie, msi_node);
1400
+	ret = iproc_msi_init(pcie, msi_node);
1401
+
1402
+out_put_node:
1403
+	of_node_put(msi_node);
1404
+	return ret;
13311405 }
13321406 
13331407 static void iproc_pcie_msi_disable(struct iproc_pcie *pcie)
....@@ -1405,7 +1479,6 @@
14051479 {
14061480 	struct device *dev;
14071481 	int ret;
1408
-	struct pci_bus *child;
14091482 	struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
14101483 
14111484 	dev = pcie->dev;
....@@ -1415,10 +1488,6 @@
14151488 		dev_err(dev, "unable to initialize controller parameters\n");
14161489 		return ret;
14171490 	}
1418
-
1419
-	ret = devm_request_pci_bus_resources(dev, res);
1420
-	if (ret)
1421
-		return ret;
14221491 
14231492 	ret = phy_init(pcie->phy);
14241493 	if (ret) {
....@@ -1434,6 +1503,8 @@
14341503 
14351504 	iproc_pcie_perst_ctrl(pcie, true);
14361505 	iproc_pcie_perst_ctrl(pcie, false);
1506
+
1507
+	iproc_pcie_invalidate_mapping(pcie);
14371508 
14381509 	if (pcie->need_ob_cfg) {
14391510 		ret = iproc_pcie_map_ranges(pcie, res);
....@@ -1461,28 +1532,15 @@
14611532 		if (iproc_pcie_msi_enable(pcie))
14621533 			dev_info(dev, "not using iProc MSI\n");
14631534 
1464
-	list_splice_init(res, &host->windows);
1465
-	host->busnr = 0;
1466
-	host->dev.parent = dev;
14671535 	host->ops = &iproc_pcie_ops;
14681536 	host->sysdata = pcie;
14691537 	host->map_irq = pcie->map_irq;
1470
-	host->swizzle_irq = pci_common_swizzle;
14711538 
1472
-	ret = pci_scan_root_bus_bridge(host);
1539
+	ret = pci_host_probe(host);
14731540 	if (ret < 0) {
14741541 		dev_err(dev, "failed to scan host: %d\n", ret);
14751542 		goto err_power_off_phy;
14761543 	}
1477
-
1478
-	pci_assign_unassigned_bus_resources(host->bus);
1479
-
1480
-	pcie->root_bus = host->bus;
1481
-
1482
-	list_for_each_entry(child, &host->bus->children, node)
1483
-		pcie_bus_configure_settings(child);
1484
-
1485
-	pci_bus_add_devices(host->bus);
14861544 
14871545 	return 0;
14881546 
....@@ -1496,8 +1554,10 @@
14961554 
14971555 int iproc_pcie_remove(struct iproc_pcie *pcie)
14981556 {
1499
-	pci_stop_root_bus(pcie->root_bus);
1500
-	pci_remove_root_bus(pcie->root_bus);
1557
+	struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1558
+
1559
+	pci_stop_root_bus(host->bus);
1560
+	pci_remove_root_bus(host->bus);
15011561 
15021562 	iproc_pcie_msi_disable(pcie);
15031563