.. | .. |
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62 | 62 | .write = pci_generic_config_write, |
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63 | 63 | }; |
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64 | 64 | |
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65 | | -static int versatile_pci_parse_request_of_pci_ranges(struct device *dev, |
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66 | | - struct list_head *res) |
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67 | | -{ |
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68 | | - int err, mem = 1, res_valid = 0; |
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69 | | - resource_size_t iobase; |
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70 | | - struct resource_entry *win, *tmp; |
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71 | | - |
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72 | | - err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, res, &iobase); |
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73 | | - if (err) |
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74 | | - return err; |
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75 | | - |
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76 | | - err = devm_request_pci_bus_resources(dev, res); |
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77 | | - if (err) |
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78 | | - goto out_release_res; |
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79 | | - |
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80 | | - resource_list_for_each_entry_safe(win, tmp, res) { |
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81 | | - struct resource *res = win->res; |
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82 | | - |
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83 | | - switch (resource_type(res)) { |
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84 | | - case IORESOURCE_IO: |
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85 | | - err = devm_pci_remap_iospace(dev, res, iobase); |
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86 | | - if (err) { |
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87 | | - dev_warn(dev, "error %d: failed to map resource %pR\n", |
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88 | | - err, res); |
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89 | | - resource_list_destroy_entry(win); |
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90 | | - } |
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91 | | - break; |
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92 | | - case IORESOURCE_MEM: |
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93 | | - res_valid |= !(res->flags & IORESOURCE_PREFETCH); |
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94 | | - |
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95 | | - writel(res->start >> 28, PCI_IMAP(mem)); |
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96 | | - writel(PHYS_OFFSET >> 28, PCI_SMAP(mem)); |
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97 | | - mem++; |
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98 | | - |
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99 | | - break; |
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100 | | - } |
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101 | | - } |
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102 | | - |
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103 | | - if (res_valid) |
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104 | | - return 0; |
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105 | | - |
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106 | | - dev_err(dev, "non-prefetchable memory resource required\n"); |
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107 | | - err = -EINVAL; |
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108 | | - |
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109 | | -out_release_res: |
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110 | | - pci_free_resource_list(res); |
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111 | | - return err; |
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112 | | -} |
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113 | | - |
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114 | 65 | static int versatile_pci_probe(struct platform_device *pdev) |
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115 | 66 | { |
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116 | 67 | struct device *dev = &pdev->dev; |
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117 | 68 | struct resource *res; |
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118 | | - int ret, i, myslot = -1; |
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| 69 | + struct resource_entry *entry; |
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| 70 | + int i, myslot = -1, mem = 1; |
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119 | 71 | u32 val; |
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120 | 72 | void __iomem *local_pci_cfg_base; |
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121 | | - struct pci_bus *bus, *child; |
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122 | 73 | struct pci_host_bridge *bridge; |
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123 | | - LIST_HEAD(pci_res); |
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124 | 74 | |
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125 | 75 | bridge = devm_pci_alloc_host_bridge(dev, 0); |
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126 | 76 | if (!bridge) |
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127 | 77 | return -ENOMEM; |
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128 | 78 | |
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129 | | - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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130 | | - versatile_pci_base = devm_ioremap_resource(dev, res); |
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| 79 | + versatile_pci_base = devm_platform_ioremap_resource(pdev, 0); |
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131 | 80 | if (IS_ERR(versatile_pci_base)) |
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132 | 81 | return PTR_ERR(versatile_pci_base); |
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133 | 82 | |
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134 | | - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
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135 | | - versatile_cfg_base[0] = devm_ioremap_resource(dev, res); |
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| 83 | + versatile_cfg_base[0] = devm_platform_ioremap_resource(pdev, 1); |
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136 | 84 | if (IS_ERR(versatile_cfg_base[0])) |
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137 | 85 | return PTR_ERR(versatile_cfg_base[0]); |
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138 | 86 | |
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.. | .. |
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141 | 89 | if (IS_ERR(versatile_cfg_base[1])) |
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142 | 90 | return PTR_ERR(versatile_cfg_base[1]); |
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143 | 91 | |
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144 | | - ret = versatile_pci_parse_request_of_pci_ranges(dev, &pci_res); |
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145 | | - if (ret) |
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146 | | - return ret; |
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| 92 | + resource_list_for_each_entry(entry, &bridge->windows) { |
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| 93 | + if (resource_type(entry->res) == IORESOURCE_MEM) { |
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| 94 | + writel(entry->res->start >> 28, PCI_IMAP(mem)); |
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| 95 | + writel(__pa(PAGE_OFFSET) >> 28, PCI_SMAP(mem)); |
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| 96 | + mem++; |
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| 97 | + } |
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| 98 | + } |
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147 | 99 | |
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148 | 100 | /* |
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149 | 101 | * We need to discover the PCI core first to configure itself |
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.. | .. |
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177 | 129 | /* |
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178 | 130 | * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM |
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179 | 131 | */ |
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180 | | - writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0); |
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181 | | - writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1); |
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182 | | - writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2); |
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| 132 | + writel(__pa(PAGE_OFFSET), local_pci_cfg_base + PCI_BASE_ADDRESS_0); |
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| 133 | + writel(__pa(PAGE_OFFSET), local_pci_cfg_base + PCI_BASE_ADDRESS_1); |
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| 134 | + writel(__pa(PAGE_OFFSET), local_pci_cfg_base + PCI_BASE_ADDRESS_2); |
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183 | 135 | |
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184 | 136 | /* |
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185 | 137 | * For many years the kernel and QEMU were symbiotically buggy |
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.. | .. |
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194 | 146 | */ |
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195 | 147 | writel(0, versatile_cfg_base[0] + PCI_INTERRUPT_LINE); |
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196 | 148 | |
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197 | | - pci_add_flags(PCI_ENABLE_PROC_DOMAINS); |
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198 | 149 | pci_add_flags(PCI_REASSIGN_ALL_BUS); |
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199 | 150 | |
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200 | | - list_splice_init(&pci_res, &bridge->windows); |
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201 | | - bridge->dev.parent = dev; |
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202 | | - bridge->sysdata = NULL; |
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203 | | - bridge->busnr = 0; |
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204 | 151 | bridge->ops = &pci_versatile_ops; |
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205 | | - bridge->map_irq = of_irq_parse_and_map_pci; |
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206 | | - bridge->swizzle_irq = pci_common_swizzle; |
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207 | 152 | |
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208 | | - ret = pci_scan_root_bus_bridge(bridge); |
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209 | | - if (ret < 0) |
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210 | | - return ret; |
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211 | | - |
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212 | | - bus = bridge->bus; |
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213 | | - |
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214 | | - pci_assign_unassigned_bus_resources(bus); |
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215 | | - list_for_each_entry(child, &bus->children, node) |
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216 | | - pcie_bus_configure_settings(child); |
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217 | | - pci_bus_add_devices(bus); |
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218 | | - |
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219 | | - return 0; |
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| 153 | + return pci_host_probe(bridge); |
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220 | 154 | } |
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221 | 155 | |
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222 | 156 | static const struct of_device_id versatile_pci_of_match[] = { |
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