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2024-05-10 cde9070d9970eef1f7ec2360586c802a16230ad8 
 kernel/drivers/net/wireless/ath/ath10k/hw.h
....@@ -1,19 +1,8 @@
1
+/* SPDX-License-Identifier: ISC */
12 /*
23  * Copyright (c) 2005-2011 Atheros Communications Inc.
34  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
45  * Copyright (c) 2018 The Linux Foundation. All rights reserved.
5
- *
6
- * Permission to use, copy, modify, and/or distribute this software for any
7
- * purpose with or without fee is hereby granted, provided that the above
8
- * copyright notice and this permission notice appear in all copies.
9
- *
10
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
176  */
187 
198 #ifndef _HW_H_
....@@ -21,12 +10,21 @@
2110 
2211 #include "targaddrs.h"
2312 
13
+enum ath10k_bus {
14
+	ATH10K_BUS_PCI,
15
+	ATH10K_BUS_AHB,
16
+	ATH10K_BUS_SDIO,
17
+	ATH10K_BUS_USB,
18
+	ATH10K_BUS_SNOC,
19
+};
20
+
2421 #define ATH10K_FW_DIR			"ath10k"
2522 
2623 #define QCA988X_2_0_DEVICE_ID_UBNT   (0x11ac)
2724 #define QCA988X_2_0_DEVICE_ID   (0x003c)
2825 #define QCA6164_2_1_DEVICE_ID   (0x0041)
2926 #define QCA6174_2_1_DEVICE_ID   (0x003e)
27
+#define QCA6174_3_2_DEVICE_ID   (0x0042)
3028 #define QCA99X0_2_0_DEVICE_ID   (0x0040)
3129 #define QCA9888_2_0_DEVICE_ID	(0x0056)
3230 #define QCA9984_1_0_DEVICE_ID	(0x0046)
....@@ -109,6 +107,7 @@
109107 #define QCA9984_HW_1_0_CHIP_ID_REV	0x0
110108 #define QCA9984_HW_1_0_FW_DIR		ATH10K_FW_DIR "/QCA9984/hw1.0"
111109 #define QCA9984_HW_1_0_BOARD_DATA_FILE "board.bin"
110
+#define QCA9984_HW_1_0_EBOARD_DATA_FILE "eboard.bin"
112111 #define QCA9984_HW_1_0_PATCH_LOAD_ADDR	0x1234
113112 
114113 /* QCA9888 2.0 defines */
....@@ -153,6 +152,8 @@
153152 #define ATH10K_FW_UTF_FILE		"utf.bin"
154153 #define ATH10K_FW_UTF_API2_FILE		"utf-2.bin"
155154 
155
+#define ATH10K_FW_UTF_FILE_BASE		"utf"
156
+
156157 /* includes also the null byte */
157158 #define ATH10K_FIRMWARE_MAGIC               "QCA-ATH10K"
158159 #define ATH10K_BOARD_MAGIC                  "QCA-ATH10K-BOARD"
....@@ -164,7 +165,7 @@
164165 struct ath10k_fw_ie {
165166 	__le32 id;
166167 	__le32 len;
167
-	u8 data[0];
168
+	u8 data[];
168169 };
169170 
170171 enum ath10k_fw_ie_type {
....@@ -221,6 +222,7 @@
221222 enum ath10k_bd_ie_type {
222223 	/* contains sub IEs of enum ath10k_bd_ie_board_type */
223224 	ATH10K_BD_IE_BOARD = 0,
225
+	ATH10K_BD_IE_BOARD_EXT = 1,
224226 };
225227 
226228 enum ath10k_bd_ie_board_type {
....@@ -343,9 +345,11 @@
343345 };
344346 
345347 struct ath10k_hw_ce_regs {
346
-	u32 sr_base_addr;
348
+	u32 sr_base_addr_lo;
349
+	u32 sr_base_addr_hi;
347350 	u32 sr_size_addr;
348
-	u32 dr_base_addr;
351
+	u32 dr_base_addr_lo;
352
+	u32 dr_base_addr_hi;
349353 	u32 dr_size_addr;
350354 	u32 ce_cmd_addr;
351355 	u32 misc_ie_addr;
....@@ -375,6 +379,9 @@
375379 	u8 num_target_ce_config_wlan;
376380 	u16 ce_desc_meta_data_mask;
377381 	u8 ce_desc_meta_data_lsb;
382
+	u32 rfkill_pin;
383
+	u32 rfkill_cfg;
384
+	bool rfkill_on_level;
378385 };
379386 
380387 extern const struct ath10k_hw_values qca988x_values;
....@@ -388,6 +395,11 @@
388395 
389396 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
390397 				u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev);
398
+
399
+int ath10k_hw_diag_fast_download(struct ath10k *ar,
400
+				 u32 address,
401
+				 const void *buffer,
402
+				 u32 length);
391403 
392404 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)
393405 #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887)
....@@ -501,6 +513,7 @@
501513 struct ath10k_hw_params {
502514 	u32 id;
503515 	u16 dev_id;
516
+	enum ath10k_bus bus;
504517 	const char *name;
505518 	u32 patch_load_addr;
506519 	int uart_pin;
....@@ -539,6 +552,8 @@
539552 		const char *dir;
540553 		const char *board;
541554 		size_t board_size;
555
+		const char *eboard;
556
+		size_t ext_board_size;
542557 		size_t board_ext_size;
543558 	} fw;
544559 
....@@ -578,9 +593,6 @@
578593 	/* Target rx ring fill level */
579594 	u32 rx_ring_fill_level;
580595 
581
-	/* target supporting per ce IRQ */
582
-	bool per_ce_irq;
583
-
584596 	/* target supporting shadow register for ce write */
585597 	bool shadow_reg_support;
586598 
....@@ -594,20 +606,46 @@
594606 	 * to avoid it sending spurious acks.
595607 	 */
596608 	bool hw_filter_reset_required;
609
+
610
+	/* target supporting fw download via diag ce */
611
+	bool fw_diag_ce_download;
612
+
613
+	/* target supporting fw download via large size BMI */
614
+	bool bmi_large_size_download;
615
+
616
+	/* need to set uart pin if disable uart print, workaround for a
617
+	 * firmware bug
618
+	 */
619
+	bool uart_pin_workaround;
620
+
621
+	/* Workaround for the credit size calculation */
622
+	bool credit_size_workaround;
623
+
624
+	/* tx stats support over pktlog */
625
+	bool tx_stats_over_pktlog;
626
+
627
+	/* provides bitrates for sta_statistics using WMI_TLV_PEER_STATS_INFO_EVENTID */
628
+	bool supports_peer_stats_info;
597629 };
598630 
599631 struct htt_rx_desc;
632
+struct htt_resp;
633
+struct htt_data_tx_completion_ext;
600634 
601635 /* Defines needed for Rx descriptor abstraction */
602636 struct ath10k_hw_ops {
603637 	int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd);
604638 	void (*set_coverage_class)(struct ath10k *ar, s16 value);
605639 	int (*enable_pll_clk)(struct ath10k *ar);
640
+	bool (*rx_desc_get_msdu_limit_error)(struct htt_rx_desc *rxd);
641
+	int (*tx_data_rssi_pad_bytes)(struct htt_resp *htt);
642
+	int (*is_rssi_enable)(struct htt_resp *resp);
606643 };
607644 
608645 extern const struct ath10k_hw_ops qca988x_ops;
609646 extern const struct ath10k_hw_ops qca99x0_ops;
610647 extern const struct ath10k_hw_ops qca6174_ops;
648
+extern const struct ath10k_hw_ops qca6174_sdio_ops;
611649 extern const struct ath10k_hw_ops wcn3990_ops;
612650 
613651 extern const struct ath10k_hw_clk_params qca6174_clk[];
....@@ -618,6 +656,33 @@
618656 {
619657 	if (hw->hw_ops->rx_desc_get_l3_pad_bytes)
620658 		return hw->hw_ops->rx_desc_get_l3_pad_bytes(rxd);
659
+	return 0;
660
+}
661
+
662
+static inline bool
663
+ath10k_rx_desc_msdu_limit_error(struct ath10k_hw_params *hw,
664
+				struct htt_rx_desc *rxd)
665
+{
666
+	if (hw->hw_ops->rx_desc_get_msdu_limit_error)
667
+		return hw->hw_ops->rx_desc_get_msdu_limit_error(rxd);
668
+	return false;
669
+}
670
+
671
+static inline int
672
+ath10k_tx_data_rssi_get_pad_bytes(struct ath10k_hw_params *hw,
673
+				  struct htt_resp *htt)
674
+{
675
+	if (hw->hw_ops->tx_data_rssi_pad_bytes)
676
+		return hw->hw_ops->tx_data_rssi_pad_bytes(htt);
677
+	return 0;
678
+}
679
+
680
+static inline int
681
+ath10k_is_rssi_enable(struct ath10k_hw_params *hw,
682
+		      struct htt_resp *resp)
683
+{
684
+	if (hw->hw_ops->is_rssi_enable)
685
+		return hw->hw_ops->is_rssi_enable(resp);
621686 	return 0;
622687 }
623688 
....@@ -703,13 +768,17 @@
703768 #define TARGET_TLV_NUM_TDLS_VDEVS		1
704769 #define TARGET_TLV_NUM_TIDS			((TARGET_TLV_NUM_PEERS) * 2)
705770 #define TARGET_TLV_NUM_MSDU_DESC		(1024 + 32)
771
+#define TARGET_TLV_NUM_MSDU_DESC_HL		1024
706772 #define TARGET_TLV_NUM_WOW_PATTERNS		22
707773 #define TARGET_TLV_MGMT_NUM_MSDU_DESC		(50)
708774 
709775 /* Target specific defines for WMI-HL-1.0 firmware */
710
-#define TARGET_HL_10_TLV_NUM_PEERS		14
711
-#define TARGET_HL_10_TLV_AST_SKID_LIMIT		6
712
-#define TARGET_HL_10_TLV_NUM_WDS_ENTRIES	2
776
+#define TARGET_HL_TLV_NUM_PEERS			33
777
+#define TARGET_HL_TLV_AST_SKID_LIMIT		16
778
+#define TARGET_HL_TLV_NUM_WDS_ENTRIES		2
779
+
780
+/* Target specific defines for QCA9377 high latency firmware */
781
+#define TARGET_QCA9377_HL_NUM_PEERS		15
713782 
714783 /* Diagnostic Window */
715784 #define CE_DIAG_PIPE	7
....@@ -1050,6 +1119,7 @@
10501119 #define MBOX_CPU_INT_STATUS_ENABLE_ADDRESS	0x00000819
10511120 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_LSB	0
10521121 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_MASK	0x000000ff
1122
+#define MBOX_CPU_STATUS_ENABLE_ASSERT_MASK 0x00000001
10531123 #define MBOX_ERROR_STATUS_ENABLE_ADDRESS	0x0000081a
10541124 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB  1
10551125 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
....@@ -1129,4 +1199,15 @@
11291199 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK	0x00000020
11301200 /* qca6174 PLL offset/mask end */
11311201 
1202
+/* CPU_ADDR_MSB is a register, bit[3:0] is to specify which memory
1203
+ * region is accessed. The memory region size is 1M.
1204
+ * If host wants to access 0xX12345 at target, then CPU_ADDR_MSB[3:0]
1205
+ * is 0xX.
1206
+ * The following MACROs are defined to get the 0xX and the size limit.
1207
+ */
1208
+#define CPU_ADDR_MSB_REGION_MASK	GENMASK(23, 20)
1209
+#define CPU_ADDR_MSB_REGION_VAL(X)	FIELD_GET(CPU_ADDR_MSB_REGION_MASK, X)
1210
+#define REGION_ACCESS_SIZE_LIMIT	0x100000
1211
+#define REGION_ACCESS_SIZE_MASK		(REGION_ACCESS_SIZE_LIMIT - 1)
1212
+
11321213 #endif /* _HW_H_ */