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2024-05-10 cde9070d9970eef1f7ec2360586c802a16230ad8 
 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
....@@ -1,19 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /**
2
- * dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
3
+ * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
34  *
45  * Copyright (C) 2014 Chen-Zhi (Roger Chen)
56  *
67  * Chen-Zhi (Roger Chen)  <roger.chen@rock-chips.com>
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License as published by
10
- * the Free Software Foundation; either version 2 of the License, or
11
- * (at your option) any later version.
12
- *
13
- * This program is distributed in the hope that it will be useful,
14
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
15
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
- * GNU General Public License for more details.
178  */
189 
1910 #include <linux/stmmac.h>
....@@ -48,7 +39,6 @@
4839 	void (*set_to_qsgmii)(struct rk_priv_data *bsp_priv);
4940 	void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
5041 	void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
51
-	void (*set_sgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
5242 	void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
5343 				    bool enable);
5444 	void (*integrated_phy_power)(struct rk_priv_data *bsp_priv, bool up);
....@@ -56,7 +46,7 @@
5646 
5747 struct rk_priv_data {
5848 	struct platform_device *pdev;
59
-	int phy_iface;
49
+	phy_interface_t phy_iface;
6050 	int bus_id;
6151 	struct regulator *regulator;
6252 	bool suspended;
....@@ -65,7 +55,6 @@
6555 	bool clk_enabled;
6656 	bool clock_input;
6757 	bool integrated_phy;
68
-	struct phy *comphy;
6958 
7059 	struct clk *clk_mac;
7160 	struct clk *gmac_clkin;
....@@ -86,9 +75,11 @@
8675 	int rx_delay;
8776 
8877 	struct regmap *grf;
78
+	struct regmap *php_grf;
8979 	struct regmap *xpcs;
9080 
9181 	unsigned char otp_data;
82
+	unsigned int bgs_increment;
9283 };
9384 
9485 /* XPCS */
....@@ -173,10 +164,10 @@
173164 	int ret, i, id = bsp_priv->bus_id;
174165 	u32 val;
175166 
176
-	if (mode == PHY_INTERFACE_MODE_QSGMII && !id)
167
+	if (mode == PHY_INTERFACE_MODE_QSGMII && id > 0)
177168 		return 0;
178169 
179
-	ret = xpcs_soft_reset(bsp_priv, 0);
170
+	ret = xpcs_soft_reset(bsp_priv, id);
180171 	if (ret) {
181172 		dev_err(&bsp_priv->pdev->dev, "xpcs_soft_reset fail %d\n", ret);
182173 		return ret;
....@@ -203,10 +194,10 @@
203194 				   SR_MII_CTRL_AN_ENABLE);
204195 		}
205196 	} else {
206
-		val = xpcs_read(bsp_priv, SR_MII_OFFSET(0) + VR_MII_DIG_CTRL1);
207
-		xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_DIG_CTRL1,
197
+		val = xpcs_read(bsp_priv, SR_MII_OFFSET(id) + VR_MII_DIG_CTRL1);
198
+		xpcs_write(bsp_priv, SR_MII_OFFSET(id) + VR_MII_DIG_CTRL1,
208199 			   val | MII_MAC_AUTO_SW);
209
-		xpcs_write(bsp_priv, SR_MII_OFFSET(0) + MII_BMCR,
200
+		xpcs_write(bsp_priv, SR_MII_OFFSET(id) + MII_BMCR,
210201 			   SR_MII_CTRL_AN_ENABLE);
211202 	}
212203 
....@@ -223,9 +214,19 @@
223214 	((((tx) >= 0) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
224215 	 (((rx) >= 0) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
225216 
217
+#define DELAY_ENABLE_BY_ID(soc, tx, rx, id) \
218
+	((((tx) >= 0) ? soc##_GMAC_TXCLK_DLY_ENABLE(id) : soc##_GMAC_TXCLK_DLY_DISABLE(id)) | \
219
+	 (((rx) >= 0) ? soc##_GMAC_RXCLK_DLY_ENABLE(id) : soc##_GMAC_RXCLK_DLY_DISABLE(id)))
220
+
226221 #define DELAY_VALUE(soc, tx, rx) \
227222 	((((tx) >= 0) ? soc##_GMAC_CLK_TX_DL_CFG(tx) : 0) | \
228223 	 (((rx) >= 0) ? soc##_GMAC_CLK_RX_DL_CFG(rx) : 0))
224
+
225
+#define GMAC_RGMII_CLK_DIV_BY_ID(soc, id, div) \
226
+		(soc##_GMAC##id##_CLK_RGMII_DIV##div)
227
+
228
+#define GMAC_RMII_CLK_DIV_BY_ID(soc, id, div) \
229
+		(soc##_GMAC##id##_CLK_RMII_DIV##div)
229230 
230231 /* Integrated EPHY */
231232 
....@@ -268,6 +269,60 @@
268269 	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
269270 	if (priv->phy_reset)
270271 		reset_control_assert(priv->phy_reset);
272
+}
273
+
274
+/* Integrated FEPHY */
275
+#define RK_FEPHY_SHUTDOWN		GRF_BIT(1)
276
+#define RK_FEPHY_POWERUP		GRF_CLR_BIT(1)
277
+#define RK_FEPHY_INTERNAL_RMII_SEL	GRF_BIT(6)
278
+#define RK_FEPHY_24M_CLK_SEL		(GRF_BIT(8) | GRF_BIT(9))
279
+#define RK_FEPHY_PHY_ID			GRF_BIT(11)
280
+
281
+#define RK_FEPHY_BGS			HIWORD_UPDATE(0x0, 0xf, 0)
282
+
283
+#define RK_FEPHY_BGS_MAX		7
284
+
285
+static void rk_gmac_integrated_fephy_power(struct rk_priv_data *priv,
286
+					   unsigned int ctrl_offset,
287
+					   unsigned int bgs_offset,
288
+					   bool up)
289
+{
290
+	struct device *dev = &priv->pdev->dev;
291
+
292
+	if (IS_ERR(priv->grf) || !priv->phy_reset) {
293
+		dev_err(dev, "%s: Missing rockchip,grf or phy_reset property\n",
294
+			__func__);
295
+		return;
296
+	}
297
+
298
+	if (up) {
299
+		unsigned int bgs = priv->otp_data;
300
+
301
+		reset_control_assert(priv->phy_reset);
302
+		udelay(20);
303
+		regmap_write(priv->grf, ctrl_offset,
304
+			     RK_FEPHY_POWERUP |
305
+			     RK_FEPHY_INTERNAL_RMII_SEL |
306
+			     RK_FEPHY_24M_CLK_SEL |
307
+			     RK_FEPHY_PHY_ID);
308
+
309
+		if (bgs > (RK_FEPHY_BGS_MAX - priv->bgs_increment) &&
310
+		    bgs <= RK_FEPHY_BGS_MAX) {
311
+			bgs = HIWORD_UPDATE(RK_FEPHY_BGS_MAX, 0xf, 0);
312
+		} else {
313
+			bgs += priv->bgs_increment;
314
+			bgs &= 0xf;
315
+			bgs = HIWORD_UPDATE(bgs, 0xf, 0);
316
+		}
317
+
318
+		regmap_write(priv->grf, bgs_offset, bgs);
319
+		usleep_range(10 * 1000, 12 * 1000);
320
+		reset_control_deassert(priv->phy_reset);
321
+		usleep_range(50 * 1000, 60 * 1000);
322
+	} else {
323
+		regmap_write(priv->grf, ctrl_offset,
324
+			     RK_FEPHY_SHUTDOWN);
325
+	}
271326 }
272327 
273328 #define PX30_GRF_GMAC_CON1		0x0904
....@@ -688,7 +743,7 @@
688743 	.set_to_rmii = rk3228_set_to_rmii,
689744 	.set_rgmii_speed = rk3228_set_rgmii_speed,
690745 	.set_rmii_speed = rk3228_set_rmii_speed,
691
-	.integrated_phy_power = rk3228_integrated_phy_power,
746
+	.integrated_phy_power =  rk3228_integrated_phy_power,
692747 };
693748 
694749 #define RK3288_GRF_SOC_CON1	0x0248
....@@ -993,7 +1048,7 @@
9931048 	.set_to_rmii = rk3328_set_to_rmii,
9941049 	.set_rgmii_speed = rk3328_set_rgmii_speed,
9951050 	.set_rmii_speed = rk3328_set_rmii_speed,
996
-	.integrated_phy_power = rk3328_integrated_phy_power,
1051
+	.integrated_phy_power =  rk3328_integrated_phy_power,
9971052 };
9981053 
9991054 #define RK3366_GRF_SOC_CON6	0x0418
....@@ -1365,14 +1420,6 @@
13651420 #define RK3528_VO_GRF_MACPHY_CON0		0X6001c
13661421 #define RK3528_VO_GRF_MACPHY_CON1		0X60020
13671422 
1368
-#define RK3528_VO_GRF_MACPHY_SHUTDOWN		GRF_BIT(1)
1369
-#define RK3528_VO_GRF_MACPHY_POWERUP		GRF_CLR_BIT(1)
1370
-#define RK3528_VO_GRF_MACPHY_INTERNAL_RMII_SEL	GRF_BIT(6)
1371
-#define RK3528_VO_GRF_MACPHY_24M_CLK_SEL	(GRF_BIT(8) | GRF_BIT(9))
1372
-#define RK3528_VO_GRF_MACPHY_PHY_ID		GRF_BIT(11)
1373
-
1374
-#define RK3528_VO_GRF_MACPHY_BGS		HIWORD_UPDATE(0x0, 0xf, 0)
1375
-
13761423 static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
13771424 				int tx_delay, int rx_delay)
13781425 {
....@@ -1408,7 +1455,8 @@
14081455 			     RK3528_GMAC1_PHY_INTF_SEL_RMII);
14091456 	else
14101457 		regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,
1411
-			     RK3528_GMAC0_PHY_INTF_SEL_RMII);
1458
+			     RK3528_GMAC0_PHY_INTF_SEL_RMII |
1459
+			     RK3528_GMAC0_CLK_RMII_DIV2);
14121460 }
14131461 
14141462 static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
....@@ -1482,41 +1530,8 @@
14821530 
14831531 static void rk3528_integrated_sphy_power(struct rk_priv_data *priv, bool up)
14841532 {
1485
-	struct device *dev = &priv->pdev->dev;
1486
-	unsigned int id = priv->bus_id;
1487
-
1488
-	/* Only GMAC0 support integrated phy */
1489
-	if (id > 0)
1490
-		return;
1491
-
1492
-	if (IS_ERR(priv->grf) || !priv->phy_reset) {
1493
-		dev_err(dev, "%s: Missing rockchip,grf or phy_reset property\n",
1494
-			__func__);
1495
-		return;
1496
-	}
1497
-
1498
-	if (up) {
1499
-		unsigned int bgs = RK3528_VO_GRF_MACPHY_BGS;
1500
-
1501
-		reset_control_assert(priv->phy_reset);
1502
-		udelay(20);
1503
-		regmap_write(priv->grf, RK3528_VO_GRF_MACPHY_CON0,
1504
-			     RK3528_VO_GRF_MACPHY_POWERUP |
1505
-			     RK3528_VO_GRF_MACPHY_INTERNAL_RMII_SEL |
1506
-			     RK3528_VO_GRF_MACPHY_24M_CLK_SEL |
1507
-			     RK3528_VO_GRF_MACPHY_PHY_ID);
1508
-
1509
-		if (priv->otp_data > 0)
1510
-			bgs = HIWORD_UPDATE(priv->otp_data, 0xf, 0);
1511
-
1512
-		regmap_write(priv->grf, RK3528_VO_GRF_MACPHY_CON1, bgs);
1513
-		usleep_range(10 * 1000, 12 * 1000);
1514
-		reset_control_deassert(priv->phy_reset);
1515
-		usleep_range(50 * 1000, 60 * 1000);
1516
-	} else {
1517
-		regmap_write(priv->grf, RK3528_VO_GRF_MACPHY_CON0,
1518
-			     RK3528_VO_GRF_MACPHY_SHUTDOWN);
1519
-	}
1533
+	rk_gmac_integrated_fephy_power(priv, RK3528_VO_GRF_MACPHY_CON0,
1534
+				       RK3528_VO_GRF_MACPHY_CON1, up);
15201535 }
15211536 
15221537 static const struct rk_gmac_ops rk3528_ops = {
....@@ -1526,6 +1541,199 @@
15261541 	.set_rmii_speed = rk3528_set_rmii_speed,
15271542 	.set_clock_selection = rk3528_set_clock_selection,
15281543 	.integrated_phy_power = rk3528_integrated_sphy_power,
1544
+};
1545
+
1546
+/* sys_grf */
1547
+#define RK3562_GRF_SYS_SOC_CON0			0X0400
1548
+#define RK3562_GRF_SYS_SOC_CON1			0X0404
1549
+
1550
+#define RK3562_GMAC0_CLK_RMII_MODE		GRF_BIT(5)
1551
+#define RK3562_GMAC0_CLK_RGMII_MODE		GRF_CLR_BIT(5)
1552
+
1553
+#define RK3562_GMAC0_CLK_RMII_GATE		GRF_BIT(6)
1554
+#define RK3562_GMAC0_CLK_RMII_NOGATE		GRF_CLR_BIT(6)
1555
+
1556
+#define RK3562_GMAC0_CLK_RMII_DIV2		GRF_BIT(7)
1557
+#define RK3562_GMAC0_CLK_RMII_DIV20		GRF_CLR_BIT(7)
1558
+
1559
+#define RK3562_GMAC0_CLK_RGMII_DIV1		\
1560
+				(GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
1561
+#define RK3562_GMAC0_CLK_RGMII_DIV5		\
1562
+				(GRF_BIT(7) | GRF_BIT(8))
1563
+#define RK3562_GMAC0_CLK_RGMII_DIV50		\
1564
+				(GRF_CLR_BIT(7) | GRF_BIT(8))
1565
+
1566
+#define RK3562_GMAC0_CLK_RMII_DIV2		GRF_BIT(7)
1567
+#define RK3562_GMAC0_CLK_RMII_DIV20		GRF_CLR_BIT(7)
1568
+
1569
+#define RK3562_GMAC0_CLK_SELET_CRU		GRF_CLR_BIT(9)
1570
+#define RK3562_GMAC0_CLK_SELET_IO		GRF_BIT(9)
1571
+
1572
+#define RK3562_GMAC1_CLK_RMII_GATE		GRF_BIT(12)
1573
+#define RK3562_GMAC1_CLK_RMII_NOGATE		GRF_CLR_BIT(12)
1574
+
1575
+#define RK3562_GMAC1_CLK_RMII_DIV2		GRF_BIT(13)
1576
+#define RK3562_GMAC1_CLK_RMII_DIV20		GRF_CLR_BIT(13)
1577
+
1578
+#define RK3562_GMAC1_RMII_SPEED100		GRF_BIT(11)
1579
+#define RK3562_GMAC1_RMII_SPEED10		GRF_CLR_BIT(11)
1580
+
1581
+#define RK3562_GMAC1_CLK_SELET_CRU		GRF_CLR_BIT(15)
1582
+#define RK3562_GMAC1_CLK_SELET_IO		GRF_BIT(15)
1583
+
1584
+/* ioc_grf */
1585
+#define RK3562_GRF_IOC_GMAC_IOFUNC0_CON0	0X10400
1586
+#define RK3562_GRF_IOC_GMAC_IOFUNC0_CON1	0X10404
1587
+#define RK3562_GRF_IOC_GMAC_IOFUNC1_CON0	0X00400
1588
+#define RK3562_GRF_IOC_GMAC_IOFUNC1_CON1	0X00404
1589
+
1590
+#define RK3562_GMAC_RXCLK_DLY_ENABLE		GRF_BIT(1)
1591
+#define RK3562_GMAC_RXCLK_DLY_DISABLE		GRF_CLR_BIT(1)
1592
+#define RK3562_GMAC_TXCLK_DLY_ENABLE		GRF_BIT(0)
1593
+#define RK3562_GMAC_TXCLK_DLY_DISABLE		GRF_CLR_BIT(0)
1594
+
1595
+#define RK3562_GMAC_CLK_RX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 8)
1596
+#define RK3562_GMAC_CLK_TX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 0)
1597
+
1598
+#define RK3562_GMAC0_IO_EXTCLK_SELET_CRU	GRF_CLR_BIT(2)
1599
+#define RK3562_GMAC0_IO_EXTCLK_SELET_IO		GRF_BIT(2)
1600
+
1601
+#define RK3562_GMAC1_IO_EXTCLK_SELET_CRU	GRF_CLR_BIT(3)
1602
+#define RK3562_GMAC1_IO_EXTCLK_SELET_IO		GRF_BIT(3)
1603
+
1604
+static void rk3562_set_to_rgmii(struct rk_priv_data *bsp_priv,
1605
+				int tx_delay, int rx_delay)
1606
+{
1607
+	struct device *dev = &bsp_priv->pdev->dev;
1608
+
1609
+	if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
1610
+		dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n");
1611
+		return;
1612
+	}
1613
+
1614
+	if (bsp_priv->bus_id > 0)
1615
+		return;
1616
+
1617
+	regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0,
1618
+		     RK3562_GMAC0_CLK_RGMII_MODE);
1619
+
1620
+	regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC0_CON1,
1621
+		     DELAY_ENABLE(RK3562, tx_delay, rx_delay));
1622
+	regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC0_CON0,
1623
+		     DELAY_VALUE(RK3562, tx_delay, rx_delay));
1624
+
1625
+	regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC1_CON1,
1626
+		     DELAY_ENABLE(RK3562, tx_delay, rx_delay));
1627
+	regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC1_CON0,
1628
+		     DELAY_VALUE(RK3562, tx_delay, rx_delay));
1629
+}
1630
+
1631
+static void rk3562_set_to_rmii(struct rk_priv_data *bsp_priv)
1632
+{
1633
+	struct device *dev = &bsp_priv->pdev->dev;
1634
+
1635
+	if (IS_ERR(bsp_priv->grf)) {
1636
+		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1637
+		return;
1638
+	}
1639
+
1640
+	if (!bsp_priv->bus_id)
1641
+		regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0,
1642
+			     RK3562_GMAC0_CLK_RMII_MODE);
1643
+}
1644
+
1645
+static void rk3562_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1646
+{
1647
+	struct device *dev = &bsp_priv->pdev->dev;
1648
+	unsigned int val = 0, offset, id = bsp_priv->bus_id;
1649
+
1650
+	switch (speed) {
1651
+	case 10:
1652
+		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
1653
+			if (id > 0) {
1654
+				val = GMAC_RMII_CLK_DIV_BY_ID(RK3562, 1, 20);
1655
+				regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0,
1656
+					     RK3562_GMAC1_RMII_SPEED10);
1657
+			} else {
1658
+				val = GMAC_RMII_CLK_DIV_BY_ID(RK3562, 0, 20);
1659
+			}
1660
+		} else {
1661
+			val = GMAC_RGMII_CLK_DIV_BY_ID(RK3562, 0, 50);
1662
+		}
1663
+		break;
1664
+	case 100:
1665
+		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
1666
+			if (id > 0) {
1667
+				val = GMAC_RMII_CLK_DIV_BY_ID(RK3562, 1, 2);
1668
+				regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0,
1669
+					     RK3562_GMAC1_RMII_SPEED100);
1670
+			} else {
1671
+				val = GMAC_RMII_CLK_DIV_BY_ID(RK3562, 0, 2);
1672
+			}
1673
+		} else {
1674
+			val = GMAC_RGMII_CLK_DIV_BY_ID(RK3562, 0, 5);
1675
+		}
1676
+		break;
1677
+	case 1000:
1678
+		if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII)
1679
+			val = GMAC_RGMII_CLK_DIV_BY_ID(RK3562, 0, 1);
1680
+		else
1681
+			goto err;
1682
+		break;
1683
+	default:
1684
+		goto err;
1685
+	}
1686
+
1687
+	offset = (bsp_priv->bus_id > 0) ? RK3562_GRF_SYS_SOC_CON1 :
1688
+					  RK3562_GRF_SYS_SOC_CON0;
1689
+	regmap_write(bsp_priv->grf, offset, val);
1690
+
1691
+	return;
1692
+err:
1693
+	dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1694
+}
1695
+
1696
+static void rk3562_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
1697
+				       bool enable)
1698
+{
1699
+	struct device *dev = &bsp_priv->pdev->dev;
1700
+	unsigned int value;
1701
+
1702
+	if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
1703
+		dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n");
1704
+		return;
1705
+	}
1706
+
1707
+	if (!bsp_priv->bus_id) {
1708
+		value = input ? RK3562_GMAC0_CLK_SELET_IO :
1709
+				RK3562_GMAC0_CLK_SELET_CRU;
1710
+		value |= enable ? RK3562_GMAC0_CLK_RMII_NOGATE :
1711
+				  RK3562_GMAC0_CLK_RMII_GATE;
1712
+		regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON0, value);
1713
+
1714
+		value = input ? RK3562_GMAC0_IO_EXTCLK_SELET_IO :
1715
+				RK3562_GMAC0_IO_EXTCLK_SELET_CRU;
1716
+		regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC0_CON1, value);
1717
+		regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC1_CON1, value);
1718
+	} else {
1719
+		value = input ? RK3562_GMAC1_CLK_SELET_IO :
1720
+				RK3562_GMAC1_CLK_SELET_CRU;
1721
+		value |= enable ? RK3562_GMAC1_CLK_RMII_NOGATE :
1722
+				 RK3562_GMAC1_CLK_RMII_GATE;
1723
+		regmap_write(bsp_priv->grf, RK3562_GRF_SYS_SOC_CON1, value);
1724
+
1725
+		value = input ? RK3562_GMAC1_IO_EXTCLK_SELET_IO :
1726
+				RK3562_GMAC1_IO_EXTCLK_SELET_CRU;
1727
+		regmap_write(bsp_priv->php_grf, RK3562_GRF_IOC_GMAC_IOFUNC1_CON1, value);
1728
+	}
1729
+}
1730
+
1731
+static const struct rk_gmac_ops rk3562_ops = {
1732
+	.set_to_rgmii = rk3562_set_to_rgmii,
1733
+	.set_to_rmii = rk3562_set_to_rmii,
1734
+	.set_rgmii_speed = rk3562_set_gmac_speed,
1735
+	.set_rmii_speed = rk3562_set_gmac_speed,
1736
+	.set_clock_selection = rk3562_set_clock_selection,
15291737 };
15301738 
15311739 #define RK3568_GRF_GMAC0_CON0		0X0380
....@@ -1657,34 +1865,6 @@
16571865 			__func__, rate, ret);
16581866 }
16591867 
1660
-static void rk3568_set_gmac_sgmii_speed(struct rk_priv_data *bsp_priv, int speed)
1661
-{
1662
-	struct device *dev = &bsp_priv->pdev->dev;
1663
-	unsigned int ctrl;
1664
-
1665
-	/* Only gmac1 set the speed for port1 */
1666
-	if (!bsp_priv->bus_id)
1667
-		return;
1668
-
1669
-	switch (speed) {
1670
-	case 10:
1671
-		ctrl = BMCR_SPEED10;
1672
-		break;
1673
-	case 100:
1674
-		ctrl = BMCR_SPEED100;
1675
-		break;
1676
-	case 1000:
1677
-		ctrl = BMCR_SPEED1000;
1678
-		break;
1679
-	default:
1680
-		dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1681
-		return;
1682
-	}
1683
-
1684
-	xpcs_write(bsp_priv, SR_MII_OFFSET(bsp_priv->bus_id) + MII_BMCR,
1685
-		   ctrl | BMCR_FULLDPLX);
1686
-}
1687
-
16881868 static const struct rk_gmac_ops rk3568_ops = {
16891869 	.set_to_rgmii = rk3568_set_to_rgmii,
16901870 	.set_to_rmii = rk3568_set_to_rmii,
....@@ -1692,7 +1872,202 @@
16921872 	.set_to_qsgmii = rk3568_set_to_qsgmii,
16931873 	.set_rgmii_speed = rk3568_set_gmac_speed,
16941874 	.set_rmii_speed = rk3568_set_gmac_speed,
1695
-	.set_sgmii_speed = rk3568_set_gmac_sgmii_speed,
1875
+};
1876
+
1877
+/* sys_grf */
1878
+#define RK3588_GRF_GMAC_CON7			0X031c
1879
+#define RK3588_GRF_GMAC_CON8			0X0320
1880
+#define RK3588_GRF_GMAC_CON9			0X0324
1881
+
1882
+#define RK3588_GMAC_RXCLK_DLY_ENABLE(id)	GRF_BIT(2 * (id) + 3)
1883
+#define RK3588_GMAC_RXCLK_DLY_DISABLE(id)	GRF_CLR_BIT(2 * (id) + 3)
1884
+#define RK3588_GMAC_TXCLK_DLY_ENABLE(id)	GRF_BIT(2 * (id) + 2)
1885
+#define RK3588_GMAC_TXCLK_DLY_DISABLE(id)	GRF_CLR_BIT(2 * (id) + 2)
1886
+
1887
+#define RK3588_GMAC_CLK_RX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 8)
1888
+#define RK3588_GMAC_CLK_TX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 0)
1889
+
1890
+/* php_grf */
1891
+#define RK3588_GRF_GMAC_CON0			0X0008
1892
+#define RK3588_GRF_CLK_CON1			0X0070
1893
+
1894
+#define RK3588_GMAC_PHY_INTF_SEL_RGMII(id)	\
1895
+	(GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6))
1896
+#define RK3588_GMAC_PHY_INTF_SEL_RMII(id)	\
1897
+	(GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6))
1898
+
1899
+#define RK3588_GMAC_CLK_RMII_MODE(id)		GRF_BIT(5 * (id))
1900
+#define RK3588_GMAC_CLK_RGMII_MODE(id)		GRF_CLR_BIT(5 * (id))
1901
+
1902
+#define RK3588_GMAC_CLK_SELET_CRU(id)		GRF_BIT(5 * (id) + 4)
1903
+#define RK3588_GMAC_CLK_SELET_IO(id)		GRF_CLR_BIT(5 * (id) + 4)
1904
+
1905
+#define RK3588_GMA_CLK_RMII_DIV2(id)		GRF_BIT(5 * (id) + 2)
1906
+#define RK3588_GMA_CLK_RMII_DIV20(id)		GRF_CLR_BIT(5 * (id) + 2)
1907
+
1908
+#define RK3588_GMAC_CLK_RGMII_DIV1(id)		\
1909
+			(GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3))
1910
+#define RK3588_GMAC_CLK_RGMII_DIV5(id)		\
1911
+			(GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
1912
+#define RK3588_GMAC_CLK_RGMII_DIV50(id)		\
1913
+			(GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
1914
+
1915
+#define RK3588_GMAC_CLK_RMII_GATE(id)		GRF_BIT(5 * (id) + 1)
1916
+#define RK3588_GMAC_CLK_RMII_NOGATE(id)		GRF_CLR_BIT(5 * (id) + 1)
1917
+
1918
+static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
1919
+				int tx_delay, int rx_delay)
1920
+{
1921
+	struct device *dev = &bsp_priv->pdev->dev;
1922
+	u32 offset_con, id = bsp_priv->bus_id;
1923
+
1924
+	if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
1925
+		dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n");
1926
+		return;
1927
+	}
1928
+
1929
+	offset_con = bsp_priv->bus_id == 1 ? RK3588_GRF_GMAC_CON9 :
1930
+					     RK3588_GRF_GMAC_CON8;
1931
+
1932
+	regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
1933
+		     RK3588_GMAC_PHY_INTF_SEL_RGMII(id));
1934
+
1935
+	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
1936
+		     RK3588_GMAC_CLK_RGMII_MODE(id));
1937
+
1938
+	regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7,
1939
+		     DELAY_ENABLE_BY_ID(RK3588, tx_delay, rx_delay, id));
1940
+
1941
+	regmap_write(bsp_priv->grf, offset_con,
1942
+		     DELAY_VALUE(RK3588, tx_delay, rx_delay));
1943
+}
1944
+
1945
+static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
1946
+{
1947
+	struct device *dev = &bsp_priv->pdev->dev;
1948
+
1949
+	if (IS_ERR(bsp_priv->php_grf)) {
1950
+		dev_err(dev, "%s: Missing rockchip,php_grf property\n", __func__);
1951
+		return;
1952
+	}
1953
+
1954
+	regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
1955
+		     RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->bus_id));
1956
+
1957
+	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
1958
+		     RK3588_GMAC_CLK_RMII_MODE(bsp_priv->bus_id));
1959
+}
1960
+
1961
+static void rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1962
+{
1963
+	struct device *dev = &bsp_priv->pdev->dev;
1964
+	unsigned int val = 0, id = bsp_priv->bus_id;
1965
+
1966
+	switch (speed) {
1967
+	case 10:
1968
+		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1969
+			val = RK3588_GMA_CLK_RMII_DIV20(id);
1970
+		else
1971
+			val = RK3588_GMAC_CLK_RGMII_DIV50(id);
1972
+		break;
1973
+	case 100:
1974
+		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1975
+			val = RK3588_GMA_CLK_RMII_DIV2(id);
1976
+		else
1977
+			val = RK3588_GMAC_CLK_RGMII_DIV5(id);
1978
+		break;
1979
+	case 1000:
1980
+		if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII)
1981
+			val = RK3588_GMAC_CLK_RGMII_DIV1(id);
1982
+		else
1983
+			goto err;
1984
+		break;
1985
+	default:
1986
+		goto err;
1987
+	}
1988
+
1989
+	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
1990
+
1991
+	return;
1992
+err:
1993
+	dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1994
+}
1995
+
1996
+static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
1997
+				       bool enable)
1998
+{
1999
+	unsigned int val = input ? RK3588_GMAC_CLK_SELET_IO(bsp_priv->bus_id) :
2000
+				   RK3588_GMAC_CLK_SELET_CRU(bsp_priv->bus_id);
2001
+
2002
+	val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->bus_id) :
2003
+			RK3588_GMAC_CLK_RMII_GATE(bsp_priv->bus_id);
2004
+
2005
+	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
2006
+}
2007
+
2008
+static const struct rk_gmac_ops rk3588_ops = {
2009
+	.set_to_rgmii = rk3588_set_to_rgmii,
2010
+	.set_to_rmii = rk3588_set_to_rmii,
2011
+	.set_rgmii_speed = rk3588_set_gmac_speed,
2012
+	.set_rmii_speed = rk3588_set_gmac_speed,
2013
+	.set_clock_selection = rk3588_set_clock_selection,
2014
+};
2015
+
2016
+#define RV1106_VOGRF_GMAC_CLK_CON		0X60004
2017
+
2018
+#define RV1106_VOGRF_MACPHY_RMII_MODE		GRF_BIT(0)
2019
+#define RV1106_VOGRF_GMAC_CLK_RMII_DIV2		GRF_BIT(2)
2020
+#define RV1106_VOGRF_GMAC_CLK_RMII_DIV20	GRF_CLR_BIT(2)
2021
+
2022
+#define RV1106_VOGRF_MACPHY_CON0		0X60028
2023
+#define RV1106_VOGRF_MACPHY_CON1		0X6002C
2024
+
2025
+static void rv1106_set_to_rmii(struct rk_priv_data *bsp_priv)
2026
+{
2027
+	struct device *dev = &bsp_priv->pdev->dev;
2028
+
2029
+	if (IS_ERR(bsp_priv->grf)) {
2030
+		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
2031
+		return;
2032
+	}
2033
+
2034
+	regmap_write(bsp_priv->grf, RV1106_VOGRF_GMAC_CLK_CON,
2035
+		     RV1106_VOGRF_MACPHY_RMII_MODE |
2036
+		     RV1106_VOGRF_GMAC_CLK_RMII_DIV2);
2037
+}
2038
+
2039
+static void rv1106_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
2040
+{
2041
+	struct device *dev = &bsp_priv->pdev->dev;
2042
+	unsigned int val = 0;
2043
+
2044
+	if (IS_ERR(bsp_priv->grf)) {
2045
+		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
2046
+		return;
2047
+	}
2048
+
2049
+	if (speed == 10) {
2050
+		val = RV1106_VOGRF_GMAC_CLK_RMII_DIV20;
2051
+	} else if (speed == 100) {
2052
+		val = RV1106_VOGRF_GMAC_CLK_RMII_DIV2;
2053
+	} else {
2054
+		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
2055
+		return;
2056
+	}
2057
+
2058
+	regmap_write(bsp_priv->grf, RV1106_VOGRF_GMAC_CLK_CON, val);
2059
+}
2060
+
2061
+static void rv1106_integrated_sphy_power(struct rk_priv_data *priv, bool up)
2062
+{
2063
+	rk_gmac_integrated_fephy_power(priv, RV1106_VOGRF_MACPHY_CON0,
2064
+				       RV1106_VOGRF_MACPHY_CON1, up);
2065
+}
2066
+
2067
+static const struct rk_gmac_ops rv1106_ops = {
2068
+	.set_to_rmii = rv1106_set_to_rmii,
2069
+	.set_rmii_speed = rv1106_set_rmii_speed,
2070
+	.integrated_phy_power = rv1106_integrated_sphy_power,
16962071 };
16972072 
16982073 #define RV1108_GRF_GMAC_CON0		0X0900
....@@ -1989,8 +2364,8 @@
19892364 				clk_prepare_enable(bsp_priv->clk_xpcs_eee);
19902365 
19912366 			if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
1992
-				bsp_priv->ops->set_clock_selection(bsp_priv, bsp_priv->clock_input,
1993
-								   true);
2367
+				bsp_priv->ops->set_clock_selection(bsp_priv,
2368
+					       bsp_priv->clock_input, true);
19942369 
19952370 			/**
19962371 			 * if (!IS_ERR(bsp_priv->clk_mac))
....@@ -2002,8 +2377,8 @@
20022377 	} else {
20032378 		if (bsp_priv->clk_enabled) {
20042379 			if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
2005
-				bsp_priv->ops->set_clock_selection(bsp_priv, bsp_priv->clock_input,
2006
-								   false);
2380
+				bsp_priv->ops->set_clock_selection(bsp_priv,
2381
+					      bsp_priv->clock_input, false);
20072382 
20082383 			if (phy_iface == PHY_INTERFACE_MODE_RMII) {
20092384 				clk_disable_unprepare(bsp_priv->mac_clk_rx);
....@@ -2074,7 +2449,7 @@
20742449 	if (!bsp_priv)
20752450 		return ERR_PTR(-ENOMEM);
20762451 
2077
-	bsp_priv->phy_iface = of_get_phy_mode(dev->of_node);
2452
+	of_get_phy_mode(dev->of_node, &bsp_priv->phy_iface);
20782453 	bsp_priv->ops = ops;
20792454 	bsp_priv->bus_id = plat->bus_id;
20802455 
....@@ -2125,14 +2500,19 @@
21252500 
21262501 	bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
21272502 							"rockchip,grf");
2503
+	bsp_priv->php_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
2504
+							    "rockchip,php_grf");
21282505 	bsp_priv->xpcs = syscon_regmap_lookup_by_phandle(dev->of_node,
21292506 							 "rockchip,xpcs");
21302507 	if (!IS_ERR(bsp_priv->xpcs)) {
2131
-		bsp_priv->comphy = devm_of_phy_get(&pdev->dev, dev->of_node, NULL);
2132
-		if (IS_ERR(bsp_priv->comphy)) {
2133
-			bsp_priv->comphy = NULL;
2508
+		struct phy *comphy;
2509
+
2510
+		comphy = devm_of_phy_get(&pdev->dev, dev->of_node, NULL);
2511
+		if (IS_ERR(comphy))
21342512 			dev_err(dev, "devm_of_phy_get error\n");
2135
-		}
2513
+		ret = phy_init(comphy);
2514
+		if (ret)
2515
+			dev_err(dev, "phy_init error\n");
21362516 	}
21372517 
21382518 	if (plat->phy_node) {
....@@ -2147,6 +2527,17 @@
21472527 			if (IS_ERR(bsp_priv->phy_reset)) {
21482528 				dev_err(&pdev->dev, "No PHY reset control found.\n");
21492529 				bsp_priv->phy_reset = NULL;
2530
+			}
2531
+
2532
+			if (of_property_read_u32(plat->phy_node, "bgs,increment",
2533
+						 &bsp_priv->bgs_increment)) {
2534
+				bsp_priv->bgs_increment = 0;
2535
+			} else {
2536
+				if (bsp_priv->bgs_increment > RK_FEPHY_BGS_MAX) {
2537
+					dev_err(dev, "%s: error bgs increment: %d\n",
2538
+						__func__, bsp_priv->bgs_increment);
2539
+					bsp_priv->bgs_increment = RK_FEPHY_BGS_MAX;
2540
+				}
21502541 			}
21512542 
21522543 			/* Read bgs from OTP if it exists */
....@@ -2217,23 +2608,11 @@
22172608 		break;
22182609 	case PHY_INTERFACE_MODE_SGMII:
22192610 		dev_info(dev, "init for SGMII\n");
2220
-		ret = phy_init(bsp_priv->comphy);
2221
-		if (ret) {
2222
-			dev_err(dev, "phy_init error: %d\n", ret);
2223
-			return ret;
2224
-		}
2225
-
22262611 		if (bsp_priv->ops && bsp_priv->ops->set_to_sgmii)
22272612 			bsp_priv->ops->set_to_sgmii(bsp_priv);
22282613 		break;
22292614 	case PHY_INTERFACE_MODE_QSGMII:
22302615 		dev_info(dev, "init for QSGMII\n");
2231
-		ret = phy_init(bsp_priv->comphy);
2232
-		if (ret) {
2233
-			dev_err(dev, "phy_init error: %d\n", ret);
2234
-			return ret;
2235
-		}
2236
-
22372616 		if (bsp_priv->ops && bsp_priv->ops->set_to_qsgmii)
22382617 			bsp_priv->ops->set_to_qsgmii(bsp_priv);
22392618 		break;
....@@ -2247,7 +2626,6 @@
22472626 		return ret;
22482627 	}
22492628 
2250
-	pm_runtime_enable(dev);
22512629 	pm_runtime_get_sync(dev);
22522630 
22532631 	return 0;
....@@ -2255,14 +2633,7 @@
22552633 
22562634 static void rk_gmac_powerdown(struct rk_priv_data *gmac)
22572635 {
2258
-	struct device *dev = &gmac->pdev->dev;
2259
-
2260
-	if (gmac->phy_iface == PHY_INTERFACE_MODE_SGMII ||
2261
-	    gmac->phy_iface == PHY_INTERFACE_MODE_QSGMII)
2262
-		phy_exit(gmac->comphy);
2263
-
2264
-	pm_runtime_put_sync(dev);
2265
-	pm_runtime_disable(dev);
2636
+	pm_runtime_put_sync(&gmac->pdev->dev);
22662637 
22672638 	rk_gmac_phy_power_on(gmac, false);
22682639 	gmac_clk_enable(gmac, false);
....@@ -2286,8 +2657,6 @@
22862657 			bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
22872658 		break;
22882659 	case PHY_INTERFACE_MODE_SGMII:
2289
-		if (bsp_priv->ops && bsp_priv->ops->set_sgmii_speed)
2290
-			bsp_priv->ops->set_sgmii_speed(bsp_priv, speed);
22912660 	case PHY_INTERFACE_MODE_QSGMII:
22922661 		break;
22932662 	default:
....@@ -2342,21 +2711,17 @@
23422711 }
23432712 EXPORT_SYMBOL(dwmac_rk_get_phy_interface);
23442713 
2345
-void __weak rk_devinfo_get_eth_mac(u8 *mac)
2346
-{
2347
-}
2348
-
2349
-
23502714 static unsigned char macaddr[6];
23512715 extern ssize_t at24_mac_read(unsigned char* addr);
2352
-void rk_get_eth_addr(void *priv, unsigned char *addr)
2716
+static void rk_get_eth_addr(void *priv, unsigned char *addr)
23532717 {
23542718 	struct rk_priv_data *bsp_priv = priv;
23552719 	struct device *dev = &bsp_priv->pdev->dev;
2356
-	unsigned char ethaddr[ETH_ALEN * MAX_ETH] = {0};
2357
-	int ret,i, id = bsp_priv->bus_id;
2720
+	//unsigned char ethaddr[ETH_ALEN * MAX_ETH] = {0};
2721
+	//int ret, id = bsp_priv->bus_id;
2722
+	int i;
2723
+
23582724 #if 0
2359
-	rk_devinfo_get_eth_mac(addr);
23602725 	if (is_valid_ether_addr(addr))
23612726 		goto out;
23622727 
....@@ -2387,7 +2752,8 @@
23872752 		memcpy(addr, &ethaddr[id * ETH_ALEN], ETH_ALEN);
23882753 	}
23892754 #endif
2390
-     #if 1
2755
+	
2756
+	#if 1
23912757         if (at24_mac_read(macaddr) > 0) {
23922758                 printk("ben %s: at24_mac_read Success!! \n", __func__);
23932759                 memcpy(addr, macaddr, 6);
....@@ -2402,7 +2768,6 @@
24022768                 goto out;
24032769         }
24042770         #endif
2405
-
24062771 out:
24072772 	dev_err(dev, "%s: mac address: %pM\n", __func__, addr);
24082773 }
....@@ -2431,6 +2796,7 @@
24312796 	if (!of_device_is_compatible(pdev->dev.of_node, "snps,dwmac-4.20a"))
24322797 		plat_dat->has_gmac = true;
24332798 
2799
+	plat_dat->sph_disable = true;
24342800 	plat_dat->fix_mac_speed = rk_fix_speed;
24352801 	plat_dat->get_eth_addr = rk_get_eth_addr;
24362802 	plat_dat->integrated_phy_power = rk_integrated_phy_power;
....@@ -2543,10 +2909,19 @@
25432909 #ifdef CONFIG_CPU_RK3528
25442910 	{ .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops },
25452911 #endif
2912
+#ifdef CONFIG_CPU_RK3562
2913
+	{ .compatible = "rockchip,rk3562-gmac", .data = &rk3562_ops },
2914
+#endif
25462915 #ifdef CONFIG_CPU_RK3568
25472916 	{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
25482917 #endif
2549
-#ifdef CONFIG_CPU_RV110X
2918
+#ifdef CONFIG_CPU_RK3588
2919
+	{ .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
2920
+#endif
2921
+#ifdef CONFIG_CPU_RV1106
2922
+	{ .compatible = "rockchip,rv1106-gmac", .data = &rv1106_ops },
2923
+#endif
2924
+#ifdef CONFIG_CPU_RV1108
25502925 	{ .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
25512926 #endif
25522927 #ifdef CONFIG_CPU_RV1126
....@@ -2565,7 +2940,8 @@
25652940 		.of_match_table = rk_gmac_dwmac_match,
25662941 	},
25672942 };
2568
-module_platform_driver(rk_gmac_dwmac_driver);
2943
+//module_platform_driver(rk_gmac_dwmac_driver);
2944
+module_platform_driver1(rk_gmac_dwmac_driver);
25692945 
25702946 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
25712947 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");