~hc/RK356X_SDK_RELEASE.git

..	..	@@ -33,6 +33,7 @@
33	33	*/
34	34
35	35	#include <linux/clk.h>
	36	+#include <linux/compat.h>
36	37	#include <linux/iopoll.h>
37	38	#include <linux/pm_runtime.h>
38	39	#include <linux/regmap.h>
..	..	@@ -42,12 +43,13 @@
42	43	#include <linux/kfifo.h>
43	44	#include <linux/interrupt.h>
44	45	#include <linux/rk-preisp.h>
45		-#include <linux/rkisp21-config.h>
	46	+#include <linux/rk-isp21-config.h>
46	47	#include <linux/iommu.h>
47	48	#include <media/v4l2-event.h>
48	49	#include <media/media-entity.h>
49	50
50	51	#include "common.h"
	52	+#include "isp_external.h"
51	53	#include "regs.h"
52	54	#include "rkisp_tb_helper.h"
53	55
..	..	@@ -83,11 +85,7 @@
83	85	* +---------------------------------------------------------+
84	86	*/
85	87
86		-struct backup_reg {
87		- const u32 base;
88		- const u32 shd;
89		- u32 val;
90		-};
	88	+static void rkisp_config_cmsk(struct rkisp_device *dev);
91	89
92	90	static inline struct rkisp_device sd_to_isp_dev(struct v4l2_subdev sd)
93	91	{
..	..	@@ -188,41 +186,50 @@
188	186	u32 code = dev->isp_sdev.in_frm.code;
189	187	u32 src_w = dev->isp_sdev.in_frm.width;
190	188	u32 src_h = dev->isp_sdev.in_frm.height;
191		- u32 dest_w, dest_h, w, h;
	189	+ u32 dest_w, dest_h, w, h, max_size, max_h, max_w;
192	190	int ret = 0;
193	191
194	192	if (!crop)
195	193	return -EINVAL;
196	194
197		- if (dev->isp_ver == ISP_V12) {
198		- w = clamp_t(u32, src_w,
199		- CIF_ISP_INPUT_W_MIN,
200		- CIF_ISP_INPUT_W_MAX_V12);
201		- h = clamp_t(u32, src_h,
202		- CIF_ISP_INPUT_H_MIN,
203		- CIF_ISP_INPUT_H_MAX_V12);
204		- } else if (dev->isp_ver == ISP_V13) {
205		- w = clamp_t(u32, src_w,
206		- CIF_ISP_INPUT_W_MIN,
207		- CIF_ISP_INPUT_W_MAX_V13);
208		- h = clamp_t(u32, src_h,
209		- CIF_ISP_INPUT_H_MIN,
210		- CIF_ISP_INPUT_H_MAX_V13);
211		- } else if (dev->isp_ver == ISP_V21) {
212		- w = clamp_t(u32, src_w,
213		- CIF_ISP_INPUT_W_MIN,
214		- CIF_ISP_INPUT_W_MAX_V21);
215		- h = clamp_t(u32, src_h,
216		- CIF_ISP_INPUT_H_MIN,
217		- CIF_ISP_INPUT_H_MAX_V21);
218		- } else {
219		- w = clamp_t(u32, src_w,
220		- CIF_ISP_INPUT_W_MIN,
221		- CIF_ISP_INPUT_W_MAX);
222		- h = clamp_t(u32, src_h,
223		- CIF_ISP_INPUT_H_MIN,
224		- CIF_ISP_INPUT_H_MAX);
	195	+ memset(&sel, 0, sizeof(sel));
	196	+ switch (dev->isp_ver) {
	197	+ case ISP_V12:
	198	+ max_w = CIF_ISP_INPUT_W_MAX_V12;
	199	+ max_h = CIF_ISP_INPUT_H_MAX_V12;
	200	+ break;
	201	+ case ISP_V13:
	202	+ max_w = CIF_ISP_INPUT_W_MAX_V13;
	203	+ max_h = CIF_ISP_INPUT_H_MAX_V13;
	204	+ break;
	205	+ case ISP_V21:
	206	+ max_w = CIF_ISP_INPUT_W_MAX_V21;
	207	+ max_h = CIF_ISP_INPUT_H_MAX_V21;
	208	+ break;
	209	+ case ISP_V30:
	210	+ max_w = dev->hw_dev->unite ?
	211	+ CIF_ISP_INPUT_W_MAX_V30_UNITE : CIF_ISP_INPUT_W_MAX_V30;
	212	+ max_h = dev->hw_dev->unite ?
	213	+ CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30;
	214	+ break;
	215	+ case ISP_V32:
	216	+ max_w = dev->hw_dev->unite ?
	217	+ CIF_ISP_INPUT_W_MAX_V32_UNITE : CIF_ISP_INPUT_W_MAX_V32;
	218	+ max_h = dev->hw_dev->unite ?
	219	+ CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32;
	220	+ break;
	221	+ case ISP_V32_L:
	222	+ max_w = CIF_ISP_INPUT_W_MAX_V32_L;
	223	+ max_h = CIF_ISP_INPUT_H_MAX_V32_L;
	224	+ break;
	225	+ default:
	226	+ max_w = CIF_ISP_INPUT_W_MAX;
	227	+ max_h = CIF_ISP_INPUT_H_MAX;
225	228	}
	229	+ max_size = max_w * max_h;
	230	+ w = clamp_t(u32, src_w, CIF_ISP_INPUT_W_MIN, max_w);
	231	+ max_h = max_size / w;
	232	+ h = clamp_t(u32, src_h, CIF_ISP_INPUT_H_MIN, max_h);
226	233
227	234	if (dev->active_sensor)
228	235	sensor = dev->active_sensor->sd;
..	..	@@ -343,35 +350,51 @@
343	350	return -ENODEV;
344	351
345	352	sensor = sd_to_sensor(dev, sensor_sd);
346		- ret = v4l2_subdev_call(sensor->sd, video, g_mbus_config,
347		- &sensor->mbus);
	353	+ if (!sensor)
	354	+ return -ENODEV;
	355	+ ret = v4l2_subdev_call(sensor->sd, pad, get_mbus_config,
	356	+ 0, &sensor->mbus);
348	357	if (ret && ret != -ENOIOCTLCMD)
349	358	return ret;
350	359
351		- if (sensor->mbus.type == V4L2_MBUS_CSI2) {
	360	+ sensor->fmt[0].pad = 0;
	361	+ sensor->fmt[0].which = V4L2_SUBDEV_FORMAT_ACTIVE;
	362	+ ret = v4l2_subdev_call(sensor->sd, pad, get_fmt,
	363	+ &sensor->cfg, &sensor->fmt[0]);
	364	+ if (ret && ret != -ENOIOCTLCMD)
	365	+ return ret;
	366	+
	367	+ if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY &&
	368	+ dev->isp_ver < ISP_V30) {
352	369	u8 vc = 0;
353	370
354		- memset(dev->csi_dev.mipi_di, 0,
355		- sizeof(dev->csi_dev.mipi_di));
356		- memset(sensor->fmt, 0, sizeof(sensor->fmt));
	371	+ sensor_sd = get_remote_sensor(sensor->sd);
	372	+ if (!sensor_sd)
	373	+ return -ENODEV;
	374	+ memset(dev->csi_dev.mipi_di, 0, sizeof(dev->csi_dev.mipi_di));
357	375	for (i = 0; i < dev->csi_dev.max_pad - 1; i++) {
	376	+ struct rkmodule_channel_info ch = { 0 };
	377	+
358	378	fmt = &sensor->fmt[i];
359		- fmt->pad = i;
360		- fmt->which = V4L2_SUBDEV_FORMAT_ACTIVE;
361		- ret = v4l2_subdev_call(sensor->sd, pad, get_fmt,
362		- &sensor->cfg, fmt);
363		- if (ret && ret != -ENOIOCTLCMD)
364		- return ret;
	379	+ ch.index = i;
	380	+ ret = v4l2_subdev_call(sensor_sd, core, ioctl,
	381	+ RKMODULE_GET_CHANNEL_INFO, &ch);
	382	+ if (ret) {
	383	+ if (i)
	384	+ *fmt = sensor->fmt[0];
	385	+ } else {
	386	+ fmt->format.width = ch.width;
	387	+ fmt->format.height = ch.height;
	388	+ fmt->format.code = ch.bus_fmt;
	389	+ }
365	390	ret = mbus_pixelcode_to_mipi_dt(fmt->format.code);
366	391	if (ret < 0) {
367	392	v4l2_err(&dev->v4l2_dev,
368	393	"Invalid mipi data type\n");
369	394	return ret;
370	395	}
371		- /* v4l2_subdev_format reserved[0]
372		- * using as mipi virtual channel
373		- */
374		- switch (fmt->reserved[0]) {
	396	+
	397	+ switch (ch.vc) {
375	398	case V4L2_MBUS_CSI2_CHANNEL_3:
376	399	vc = 3;
377	400	break;
..	..	@@ -393,18 +416,14 @@
393	416	fmt->format.width,
394	417	fmt->format.height);
395	418	}
396		- } else {
397		- sensor->fmt[0].pad = 0;
398		- sensor->fmt[0].which = V4L2_SUBDEV_FORMAT_ACTIVE;
399		- ret = v4l2_subdev_call(sensor->sd, pad, get_fmt,
400		- &sensor->cfg, &sensor->fmt[0]);
401		- if (ret && ret != -ENOIOCTLCMD)
402		- return ret;
403	419	}
404	420
405	421	v4l2_subdev_call(sensor->sd, video, g_frame_interval, &sensor->fi);
406	422	dev->active_sensor = sensor;
407		-
	423	+ i = dev->dev_id;
	424	+ if (sensor->fi.interval.numerator)
	425	+ dev->hw_dev->isp_size[i].fps =
	426	+ sensor->fi.interval.denominator / sensor->fi.interval.numerator;
408	427	return ret;
409	428	}
410	429
..	..	@@ -471,6 +490,86 @@
471	490	return pixelformat;
472	491	}
473	492
	493	+static void rkisp_dvfs(struct rkisp_device *dev)
	494	+{
	495	+ struct rkisp_hw_dev *hw = dev->hw_dev;
	496	+ u64 data_rate = 0;
	497	+ int i, fps, num = 0;
	498	+
	499	+ if (!hw->is_dvfs)
	500	+ return;
	501	+ hw->is_dvfs = false;
	502	+ for (i = 0; i < hw->dev_num; i++) {
	503	+ if (!hw->isp_size[i].is_on)
	504	+ continue;
	505	+ fps = hw->isp_size[i].fps;
	506	+ if (!fps)
	507	+ fps = 30;
	508	+ data_rate += (fps * hw->isp_size[i].size);
	509	+ num++;
	510	+ }
	511	+ do_div(data_rate, 1000 * 1000);
	512	+ /* increase margin: 25% * num */
	513	+ data_rate += (data_rate >> 2) * num;
	514	+ /* one frame two-run, data double */
	515	+ if (hw->is_multi_overflow && num > 1)
	516	+ data_rate *= 2;
	517	+ /* compare with isp clock adjustment table */
	518	+ for (i = 0; i < hw->num_clk_rate_tbl; i++)
	519	+ if (data_rate <= hw->clk_rate_tbl[i].clk_rate)
	520	+ break;
	521	+ if (i == hw->num_clk_rate_tbl)
	522	+ i--;
	523	+
	524	+ /* set isp clock rate */
	525	+ rkisp_set_clk_rate(hw->clks[0], hw->clk_rate_tbl[i].clk_rate * 1000000UL);
	526	+ if (hw->unite == ISP_UNITE_TWO)
	527	+ rkisp_set_clk_rate(hw->clks[5], hw->clk_rate_tbl[i].clk_rate * 1000000UL);
	528	+ /* aclk equal to core clk */
	529	+ if (dev->isp_ver == ISP_V32)
	530	+ rkisp_set_clk_rate(hw->clks[1], hw->clk_rate_tbl[i].clk_rate * 1000000UL);
	531	+ dev_info(hw->dev, "set isp clk = %luHz\n", clk_get_rate(hw->clks[0]));
	532	+}
	533	+
	534	+static void rkisp_multi_overflow_hdl(struct rkisp_device *dev, bool on)
	535	+{
	536	+ struct rkisp_hw_dev *hw = dev->hw_dev;
	537	+
	538	+ if (on) {
	539	+ /* enable mi */
	540	+ rkisp_update_regs(dev, ISP3X_MI_WR_CTRL, ISP3X_MI_WR_CTRL);
	541	+ rkisp_update_regs(dev, ISP3X_ISP_CTRL1, ISP3X_ISP_CTRL1);
	542	+ if (dev->isp_ver == ISP_V30) {
	543	+ rkisp_update_regs(dev, ISP3X_MPFBC_CTRL, ISP3X_MPFBC_CTRL);
	544	+ rkisp_update_regs(dev, ISP3X_MI_BP_WR_CTRL, ISP3X_MI_BP_WR_CTRL);
	545	+ rkisp_update_regs(dev, ISP3X_SWS_CFG, ISP3X_SWS_CFG);
	546	+ } else if (dev->isp_ver == ISP_V32) {
	547	+ rkisp_update_regs(dev, ISP3X_MI_BP_WR_CTRL, ISP3X_MI_BP_WR_CTRL);
	548	+ rkisp_update_regs(dev, ISP32_MI_BPDS_WR_CTRL, ISP32_MI_BPDS_WR_CTRL);
	549	+ rkisp_update_regs(dev, ISP32_MI_MPDS_WR_CTRL, ISP32_MI_MPDS_WR_CTRL);
	550	+ }
	551	+ } else {
	552	+ /* disabled mi. rv1106 sdmmc workaround, 3a_wr no close */
	553	+ writel(CIF_MI_CTRL_INIT_OFFSET_EN \| CIF_MI_CTRL_INIT_BASE_EN,
	554	+ hw->base_addr + ISP3X_MI_WR_CTRL);
	555	+ if (dev->isp_ver == ISP_V30) {
	556	+ writel(0, hw->base_addr + ISP3X_MPFBC_CTRL);
	557	+ writel(0, hw->base_addr + ISP3X_MI_BP_WR_CTRL);
	558	+ writel(0xc, hw->base_addr + ISP3X_SWS_CFG);
	559	+ if (hw->unite == ISP_UNITE_TWO) {
	560	+ writel(0, hw->base_next_addr + ISP3X_MI_WR_CTRL);
	561	+ writel(0, hw->base_next_addr + ISP3X_MPFBC_CTRL);
	562	+ writel(0, hw->base_next_addr + ISP3X_MI_BP_WR_CTRL);
	563	+ writel(0xc, hw->base_next_addr + ISP3X_SWS_CFG);
	564	+ }
	565	+ } else if (dev->isp_ver == ISP_V32) {
	566	+ writel(0, hw->base_addr + ISP3X_MI_BP_WR_CTRL);
	567	+ writel(0, hw->base_addr + ISP32_MI_BPDS_WR_CTRL);
	568	+ writel(0, hw->base_addr + ISP32_MI_MPDS_WR_CTRL);
	569	+ }
	570	+ }
	571	+ rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true);
	572	+}
474	573
475	574	/*
476	575	* for hdr read back mode, rawrd read back data
..	..	@@ -479,6 +578,7 @@
479	578	void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, bool is_try)
480	579	{
481	580	struct rkisp_isp_params_vdev *params_vdev = &dev->params_vdev;
	581	+ struct rkisp_isp_stats_vdev *stats_vdev = &dev->stats_vdev;
482	582	struct rkisp_hw_dev *hw = dev->hw_dev;
483	583	u32 val, cur_frame_id, tmp, rd_mode;
484	584	u64 iq_feature = hw->iq_feature;
..	..	@@ -488,8 +588,12 @@
488	588	hw->cur_dev_id = dev->dev_id;
489	589	rkisp_dmarx_get_frame(dev, &cur_frame_id, NULL, NULL, true);
490	590
	591	+ /* isp process the same frame */
	592	+ if (is_try)
	593	+ goto run_next;
	594	+
491	595	val = 0;
492		- if (mode & T_START_X1) {
	596	+ if (mode & (T_START_X1 \| T_START_C)) {
493	597	rd_mode = HDR_RDBK_FRAME1;
494	598	} else if (mode & T_START_X2) {
495	599	rd_mode = HDR_RDBK_FRAME2;
..	..	@@ -502,6 +606,11 @@
502	606	val = rkisp_read(dev, ISP_HDRMGE_BASE, false) & 0xf;
503	607	}
504	608
	609	+ if (mode & T_START_C)
	610	+ rkisp_expander_config(dev, NULL, true);
	611	+ else
	612	+ rkisp_expander_config(dev, NULL, false);
	613	+
505	614	if (is_feature_on) {
506	615	if ((ISP2X_MODULE_HDRMGE & ~iq_feature) && (val & SW_HDRMGE_EN)) {
507	616	v4l2_err(&dev->v4l2_dev, "hdrmge is not supported\n");
..	..	@@ -509,24 +618,22 @@
509	618	}
510	619	}
511	620
512		- tmp = rkisp_read(dev, ISP_HDRMGE_BASE, false) & 0xf;
513		- if (val != tmp) {
514		- rkisp_write(dev, ISP_HDRMGE_BASE, val, false);
	621	+ if (rd_mode != dev->rd_mode) {
	622	+ rkisp_unite_set_bits(dev, ISP_HDRMGE_BASE, ISP_HDRMGE_MODE_MASK, val, false);
515	623	dev->skip_frame = 2;
516	624	is_upd = true;
517	625	}
518	626
519		- if (dev->isp_ver == ISP_V20 && dev->dmarx_dev.trigger == T_MANUAL && !is_try) {
520		- if (dev->rd_mode != rd_mode && RKMODULE_EXTEND_LINE != 0) {
	627	+ if (dev->isp_ver == ISP_V20 && dev->dmarx_dev.trigger == T_MANUAL) {
	628	+ if (dev->rd_mode != rd_mode && dev->br_dev.en) {
521	629	tmp = dev->isp_sdev.in_crop.height;
522	630	val = rkisp_read(dev, CIF_DUAL_CROP_CTRL, false);
523	631	if (rd_mode == HDR_RDBK_FRAME1) {
524		- val \|= CIF_DUAL_CROP_MP_MODE_YUV \| CIF_DUAL_CROP_SP_MODE_YUV;
	632	+ val \|= CIF_DUAL_CROP_MP_MODE_YUV;
525	633	tmp += RKMODULE_EXTEND_LINE;
526	634	} else {
527		- val &= ~(CIF_DUAL_CROP_MP_MODE_YUV \| CIF_DUAL_CROP_SP_MODE_YUV);
	635	+ val &= ~CIF_DUAL_CROP_MP_MODE_YUV;
528	636	}
529		- val \|= CIF_DUAL_CROP_CFG_UPD;
530	637	rkisp_write(dev, CIF_DUAL_CROP_CTRL, val, false);
531	638	rkisp_write(dev, CIF_ISP_ACQ_V_SIZE, tmp, false);
532	639	rkisp_write(dev, CIF_ISP_OUT_V_SIZE, tmp, false);
..	..	@@ -538,19 +645,38 @@
538	645	}
539	646	dev->rd_mode = rd_mode;
540	647
541		- rkisp_params_first_cfg(&dev->params_vdev, &dev->isp_sdev.in_fmt,
542		- dev->isp_sdev.quantization);
543		- rkisp_params_cfg(params_vdev, cur_frame_id);
	648	+ if (hw->unite != ISP_UNITE_ONE \|\| dev->unite_index == ISP_UNITE_LEFT) {
	649	+ rkisp_params_first_cfg(&dev->params_vdev, &dev->isp_sdev.in_fmt,
	650	+ dev->isp_sdev.quantization);
	651	+ rkisp_params_cfg(params_vdev, cur_frame_id);
	652	+ rkisp_config_cmsk(dev);
	653	+ rkisp_stream_frame_start(dev, 0);
	654	+ }
544	655
545		- if (!hw->is_single && !is_try) {
	656	+ if (!hw->is_single) {
	657	+ /* multi sensor need to reset isp resize mode if scale up */
	658	+ val = 0;
	659	+ if (rkisp_read(dev, ISP3X_MAIN_RESIZE_CTRL, true) & 0xf0)
	660	+ val \|= BIT(3);
	661	+ if (dev->isp_ver != ISP_V32_L &&
	662	+ rkisp_read(dev, ISP3X_SELF_RESIZE_CTRL, true) & 0xf0)
	663	+ val \|= BIT(4);
	664	+ if (rkisp_read(dev, ISP32_BP_RESIZE_CTRL, true) & 0xf0)
	665	+ val \|= BIT(12);
	666	+ if (val) {
	667	+ writel(val, hw->base_addr + CIF_IRCL);
	668	+ writel(0, hw->base_addr + CIF_IRCL);
	669	+ }
	670	+
546	671	rkisp_update_regs(dev, CTRL_VI_ISP_PATH, SUPER_IMP_COLOR_CR);
547		- rkisp_update_regs(dev, DUAL_CROP_M_H_OFFS, DUAL_CROP_S_V_SIZE);
548		- rkisp_update_regs(dev, ISP_ACQ_PROP, DUAL_CROP_CTRL);
549		- rkisp_update_regs(dev, MAIN_RESIZE_SCALE_HY, MI_WR_CTRL);
550		- rkisp_update_regs(dev, SELF_RESIZE_SCALE_HY, MAIN_RESIZE_CTRL);
551		- rkisp_update_regs(dev, ISP_GAMMA_OUT_CTRL, SELF_RESIZE_CTRL);
	672	+ rkisp_update_regs(dev, DUAL_CROP_M_H_OFFS, ISP3X_DUAL_CROP_FBC_V_SIZE);
	673	+ rkisp_update_regs(dev, ISP_ACQ_H_OFFS, DUAL_CROP_CTRL);
	674	+ rkisp_update_regs(dev, SELF_RESIZE_SCALE_HY, MI_WR_CTRL);
	675	+ rkisp_update_regs(dev, ISP32_BP_RESIZE_SCALE_HY, SELF_RESIZE_CTRL);
	676	+ rkisp_update_regs(dev, MAIN_RESIZE_SCALE_HY, ISP32_BP_RESIZE_CTRL);
	677	+ rkisp_update_regs(dev, ISP_GAMMA_OUT_CTRL, MAIN_RESIZE_CTRL);
552	678	rkisp_update_regs(dev, MI_RD_CTRL2, ISP_LSC_CTRL);
553		- rkisp_update_regs(dev, MI_MP_WR_Y_BASE, MI_MP_WR_Y_LLENGTH);
	679	+ rkisp_update_regs(dev, MI_MP_WR_Y_BASE, MI_WR_CTRL2 - 4);
554	680	rkisp_update_regs(dev, ISP_LSC_XGRAD_01, ISP_RAWAWB_RAM_DATA);
555	681	if (dev->isp_ver == ISP_V20 &&
556	682	(rkisp_read(dev, ISP_DHAZ_CTRL, false) & ISP_DHAZ_ENMUX \|\|
..	..	@@ -560,68 +686,221 @@
560	686	val = rkisp_read(dev, MI_WR_CTRL2, false);
561	687	rkisp_set_bits(dev, MI_WR_CTRL2, 0, val, true);
562	688	rkisp_write(dev, MI_WR_INIT, ISP21_SP_FORCE_UPD \| ISP21_MP_FORCE_UPD, true);
563		- /* sensor mode & index */
	689	+ } else {
	690	+ if (dev->isp_ver == ISP_V32_L)
	691	+ rkisp_write(dev, ISP32_SELF_SCALE_UPDATE, ISP32_SCALE_FORCE_UPD, true);
	692	+ rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true);
	693	+ }
	694	+ /* sensor mode & index */
	695	+ if (dev->isp_ver >= ISP_V21) {
564	696	val = rkisp_read_reg_cache(dev, ISP_ACQ_H_OFFS);
565		- val \|= ISP21_SENSOR_MODE(hw->dev_num >= 3 ? 2 : hw->dev_num - 1) \|
566		- ISP21_SENSOR_INDEX(dev->dev_id);
	697	+ val \|= ISP21_SENSOR_INDEX(dev->multi_index);
	698	+ if (dev->isp_ver == ISP_V32_L)
	699	+ val \|= ISP32L_SENSOR_MODE(dev->multi_mode);
	700	+ else
	701	+ val \|= ISP21_SENSOR_MODE(dev->multi_mode);
567	702	writel(val, hw->base_addr + ISP_ACQ_H_OFFS);
	703	+ if (hw->unite == ISP_UNITE_TWO)
	704	+ writel(val, hw->base_next_addr + ISP_ACQ_H_OFFS);
	705	+ v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
	706	+ "sensor mode:%d index:%d \| 0x%x\n",
	707	+ dev->multi_mode, dev->multi_index, val);
568	708	}
569	709	is_upd = true;
570	710	}
571	711
572		- if (dev->isp_ver == ISP_V21)
	712	+ if (dev->isp_ver > ISP_V20)
573	713	dma2frm = 0;
574	714	if (dma2frm > 2)
575	715	dma2frm = 2;
576	716	if (dma2frm == 2)
577	717	dev->rdbk_cnt_x3++;
578		- else if (dma2frm == 1)
	718	+ else if (dma2frm == 1 \|\| dev->sw_rd_cnt)
579	719	dev->rdbk_cnt_x2++;
580	720	else
581	721	dev->rdbk_cnt_x1++;
582	722	dev->rdbk_cnt++;
	723	+ if (dev->isp_ver == ISP_V20)
	724	+ params_vdev->rdbk_times = dma2frm + 1;
583	725
584		- rkisp_params_cfgsram(params_vdev);
585		- params_vdev->rdbk_times = dma2frm + 1;
	726	+run_next:
	727	+ rkisp_params_cfgsram(params_vdev, true);
	728	+ stats_vdev->rdbk_drop = false;
	729	+ if (dev->is_frame_double) {
	730	+ is_upd = true;
	731	+ if (is_try) {
	732	+ /* the frame second running to on mi */
	733	+ rkisp_multi_overflow_hdl(dev, true);
	734	+ rkisp_update_regs(dev, ISP_LDCH_BASE, ISP_LDCH_BASE);
586	735
587		- /* read 3d lut at frame end */
	736	+ val = ISP3X_YNR_FST_FRAME \| ISP3X_DHAZ_FST_FRAME \| ISP3X_CNR_FST_FRAME;
	737	+ if (dev->isp_ver == ISP_V32)
	738	+ val \|= ISP32_SHP_FST_FRAME;
	739	+ else
	740	+ val \|= ISP3X_CNR_FST_FRAME;
	741	+ rkisp_unite_clear_bits(dev, ISP3X_ISP_CTRL1, val, false);
	742	+ val = rkisp_read_reg_cache(dev, ISP3X_DRC_IIRWG_GAIN);
	743	+ writel(val, hw->base_addr + ISP3X_DRC_IIRWG_GAIN);
	744	+ if (hw->unite == ISP_UNITE_TWO)
	745	+ writel(val, hw->base_next_addr + ISP3X_DRC_IIRWG_GAIN);
	746	+ val = rkisp_read_reg_cache(dev, ISP3X_DRC_EXPLRATIO);
	747	+ writel(val, hw->base_addr + ISP3X_DRC_EXPLRATIO);
	748	+ if (hw->unite == ISP_UNITE_TWO)
	749	+ writel(val, hw->base_next_addr + ISP3X_DRC_EXPLRATIO);
	750	+ val = rkisp_read_reg_cache(dev, ISP3X_YNR_GLOBAL_CTRL);
	751	+ writel(val, hw->base_addr + ISP3X_YNR_GLOBAL_CTRL);
	752	+ if (hw->unite == ISP_UNITE_TWO)
	753	+ writel(val, hw->base_next_addr + ISP3X_YNR_GLOBAL_CTRL);
	754	+ if (dev->isp_ver == ISP_V21 \|\| dev->isp_ver == ISP_V30) {
	755	+ val = rkisp_read_reg_cache(dev, ISP3X_CNR_CTRL);
	756	+ writel(val, hw->base_addr + ISP3X_CNR_CTRL);
	757	+ if (hw->unite == ISP_UNITE_TWO)
	758	+ writel(val, hw->base_next_addr + ISP3X_CNR_CTRL);
	759	+ }
	760	+ } else {
	761	+ /* the frame first running to off mi to save bandwidth */
	762	+ rkisp_multi_overflow_hdl(dev, false);
	763	+
	764	+ /* FST_FRAME no to read sram thumb */
	765	+ val = ISP3X_YNR_FST_FRAME \| ISP3X_DHAZ_FST_FRAME;
	766	+ if (dev->isp_ver == ISP_V32)
	767	+ val \|= ISP32_SHP_FST_FRAME;
	768	+ else
	769	+ val \|= ISP3X_CNR_FST_FRAME;
	770	+ rkisp_unite_set_bits(dev, ISP3X_ISP_CTRL1, 0, val, false);
	771	+ /* ADRC low iir thumb weight for first sensor switch */
	772	+ val = rkisp_read_reg_cache(dev, ISP3X_DRC_IIRWG_GAIN);
	773	+ val &= ~ISP3X_DRC_IIR_WEIGHT_MASK;
	774	+ writel(val, hw->base_addr + ISP3X_DRC_IIRWG_GAIN);
	775	+ if (hw->unite == ISP_UNITE_TWO)
	776	+ writel(val, hw->base_next_addr + ISP3X_DRC_IIRWG_GAIN);
	777	+ /* ADRC iir5x5 and cur3x3 weight */
	778	+ val = rkisp_read_reg_cache(dev, ISP3X_DRC_EXPLRATIO);
	779	+ val &= ~ISP3X_DRC_WEIPRE_FRAME_MASK;
	780	+ writel(val, hw->base_addr + ISP3X_DRC_EXPLRATIO);
	781	+ if (hw->unite == ISP_UNITE_TWO)
	782	+ writel(val, hw->base_next_addr + ISP3X_DRC_EXPLRATIO);
	783	+ /* YNR_THUMB_MIX_CUR_EN for thumb read addr to 0 */
	784	+ val = rkisp_read_reg_cache(dev, ISP3X_YNR_GLOBAL_CTRL);
	785	+ val \|= ISP3X_YNR_THUMB_MIX_CUR_EN;
	786	+ writel(val, hw->base_addr + ISP3X_YNR_GLOBAL_CTRL);
	787	+ if (hw->unite == ISP_UNITE_TWO)
	788	+ writel(val, hw->base_next_addr + ISP3X_YNR_GLOBAL_CTRL);
	789	+ if (dev->isp_ver == ISP_V21 \|\| dev->isp_ver == ISP_V30) {
	790	+ /* CNR_THUMB_MIX_CUR_EN for thumb read addr to 0 */
	791	+ val = rkisp_read_reg_cache(dev, ISP3X_CNR_CTRL);
	792	+ val \|= ISP3X_CNR_THUMB_MIX_CUR_EN;
	793	+ writel(val, hw->base_addr + ISP3X_CNR_CTRL);
	794	+ if (hw->unite == ISP_UNITE_TWO)
	795	+ writel(val, hw->base_next_addr + ISP3X_CNR_CTRL);
	796	+ }
	797	+ stats_vdev->rdbk_drop = true;
	798	+ }
	799	+ }
	800	+
	801	+ /* disable isp force update to read 3dlut
	802	+ * 3dlut auto update at frame end for single sensor
	803	+ */
588	804	if (hw->is_single && is_upd &&
589	805	rkisp_read_reg_cache(dev, ISP_3DLUT_UPDATE) & 0x1) {
590		- rkisp_write(dev, ISP_3DLUT_UPDATE, 0, true);
	806	+ rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 0, true);
591	807	is_3dlut_upd = true;
592	808	}
593	809	if (is_upd) {
594	810	val = rkisp_read(dev, ISP_CTRL, false);
595	811	val \|= CIF_ISP_CTRL_ISP_CFG_UPD;
596		- rkisp_write(dev, ISP_CTRL, val, true);
	812	+ rkisp_unite_write(dev, ISP_CTRL, val, true);
	813	+ /* bayer pat after ISP_CFG_UPD for multi sensor to read lsc r/g/b table */
	814	+ rkisp_update_regs(dev, ISP3X_ISP_CTRL1, ISP3X_ISP_CTRL1);
597	815	/* fix ldch multi sensor case:
598	816	* ldch will pre-read data when en and isp force upd or frame end,
599	817	* udelay for ldch pre-read data.
600	818	* ldch en=0 before start for frame end to stop ldch read data.
601	819	*/
602		- if (!hw->is_single &&
603		- (rkisp_read(dev, ISP_LDCH_BASE, true) & 0x1)) {
	820	+ val = rkisp_read(dev, ISP_LDCH_BASE, true);
	821	+ if (!hw->is_single && val & BIT(0)) {
604	822	udelay(50);
605		- writel(0, hw->base_addr + ISP_LDCH_BASE);
	823	+ val &= ~(BIT(0) \| BIT(31));
	824	+ writel(val, hw->base_addr + ISP_LDCH_BASE);
	825	+ if (hw->unite == ISP_UNITE_TWO)
	826	+ writel(val, hw->base_next_addr + ISP_LDCH_BASE);
606	827	}
607	828	}
608	829	if (is_3dlut_upd)
609		- rkisp_write(dev, ISP_3DLUT_UPDATE, 1, true);
	830	+ rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 1, true);
610	831
611		- memset(dev->filt_state, 0, sizeof(dev->filt_state));
612		- dev->filt_state[RDBK_F_VS] = dma2frm;
	832	+ /* if output stream enable, wait it end */
	833	+ val = rkisp_read(dev, CIF_MI_CTRL_SHD, true);
	834	+ if (val & CIF_MI_CTRL_SHD_MP_OUT_ENABLED)
	835	+ dev->irq_ends_mask \|= ISP_FRAME_MP;
	836	+ else
	837	+ dev->irq_ends_mask &= ~ISP_FRAME_MP;
	838	+ if (val & CIF_MI_CTRL_SHD_SP_OUT_ENABLED)
	839	+ dev->irq_ends_mask \|= ISP_FRAME_SP;
	840	+ else
	841	+ dev->irq_ends_mask &= ~ISP_FRAME_SP;
	842	+ if ((dev->isp_ver == ISP_V20 &&
	843	+ rkisp_read(dev, ISP_MPFBC_CTRL, true) & SW_MPFBC_EN) \|\|
	844	+ (dev->isp_ver == ISP_V30 &&
	845	+ rkisp_read(dev, ISP3X_MPFBC_CTRL, true) & ISP3X_MPFBC_EN_SHD))
	846	+ dev->irq_ends_mask \|= ISP_FRAME_MPFBC;
	847	+ else
	848	+ dev->irq_ends_mask &= ~ISP_FRAME_MPFBC;
	849	+ if ((dev->isp_ver == ISP_V30 &&
	850	+ rkisp_read(dev, ISP3X_MI_BP_WR_CTRL, true) & ISP3X_BP_ENABLE) \|\|
	851	+ (dev->isp_ver == ISP_V32 &&
	852	+ rkisp_read(dev, ISP32_MI_WR_CTRL2_SHD, true) & ISP32_BP_EN_OUT_SHD))
	853	+ dev->irq_ends_mask \|= ISP_FRAME_BP;
	854	+ else
	855	+ dev->irq_ends_mask &= ~ISP_FRAME_BP;
613	856
614	857	val = rkisp_read(dev, CSI2RX_CTRL0, true);
615	858	val &= ~SW_IBUF_OP_MODE(0xf);
616	859	tmp = SW_IBUF_OP_MODE(dev->rd_mode);
617	860	val \|= tmp \| SW_CSI2RX_EN \| SW_DMA_2FRM_MODE(dma2frm);
	861	+ if (dev->isp_ver > ISP_V20)
	862	+ dma2frm = dev->sw_rd_cnt;
618	863	v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
619		- "readback frame:%d time:%d 0x%x\n",
620		- cur_frame_id, dma2frm + 1, val);
621		- if (!dma2frm)
622		- rkisp_bridge_update_mi(dev, 0);
	864	+ "readback frame:%d time:%d 0x%x try:%d\n",
	865	+ cur_frame_id, dma2frm + 1, val, is_try);
623	866	if (!hw->is_shutdown)
624		- rkisp_write(dev, CSI2RX_CTRL0, val, true);
	867	+ rkisp_unite_write(dev, CSI2RX_CTRL0, val, true);
	868	+}
	869	+
	870	+static void rkisp_fast_switch_rx_buf(struct rkisp_device *dev, bool is_current)
	871	+{
	872	+ struct rkisp_stream *stream;
	873	+ struct rkisp_buffer *buf;
	874	+ u32 i, val;
	875	+
	876	+ if (!dev->is_rtt_first)
	877	+ return;
	878	+
	879	+ for (i = RKISP_STREAM_RAWRD0; i < RKISP_MAX_DMARX_STREAM; i++) {
	880	+ stream = &dev->dmarx_dev.stream[i];
	881	+ if (!stream->ops)
	882	+ continue;
	883	+ buf = NULL;
	884	+ if (is_current)
	885	+ buf = stream->curr_buf;
	886	+ else if (!list_empty(&stream->buf_queue))
	887	+ buf = list_first_entry(&stream->buf_queue,
	888	+ struct rkisp_buffer, queue);
	889	+ if (!buf)
	890	+ continue;
	891	+ val = buf->buff_addr[RKISP_PLANE_Y];
	892	+ /* f1 -> f0 -> f1 for normal
	893	+ * L:f1 L:f1 -> L:f0 S:f0 -> L:f1 S:f1 for hdr2
	894	+ */
	895	+ if (dev->rd_mode == HDR_RDBK_FRAME2 && !is_current &&
	896	+ rkisp_read_reg_cache(dev, ISP3X_HDRMGE_GAIN0) == 0xfff0040) {
	897	+ if (i == RKISP_STREAM_RAWRD2)
	898	+ continue;
	899	+ else
	900	+ rkisp_write(dev, ISP3X_MI_RAWS_RD_BASE, val, false);
	901	+ }
	902	+ rkisp_write(dev, stream->config->mi.y_base_ad_init, val, false);
	903	+ }
625	904	}
626	905
627	906	static void rkisp_rdbk_trigger_handle(struct rkisp_device *dev, u32 cmd)
..	..	@@ -633,20 +912,44 @@
633	912	int i, times = -1, max = 0, id = 0;
634	913	int len[DEV_MAX] = { 0 };
635	914	u32 mode = 0;
	915	+ bool is_try = false;
636	916
637	917	spin_lock_irqsave(&hw->rdbk_lock, lock_flags);
638		- if (cmd == T_CMD_END)
	918	+ if (cmd == T_CMD_END) {
	919	+ if (dev->sw_rd_cnt) {
	920	+ dev->sw_rd_cnt--;
	921	+ isp = dev;
	922	+ is_try = true;
	923	+ times = 0;
	924	+ if (hw->unite == ISP_UNITE_ONE) {
	925	+ if (dev->sw_rd_cnt < 2)
	926	+ isp->unite_index = ISP_UNITE_RIGHT;
	927	+ if (!hw->is_multi_overflow \|\| (dev->sw_rd_cnt & 0x1))
	928	+ is_try = false;
	929	+ }
	930	+ goto end;
	931	+ }
639	932	hw->is_idle = true;
	933	+ hw->pre_dev_id = dev->dev_id;
	934	+ }
640	935	if (hw->is_shutdown)
641	936	hw->is_idle = false;
642	937	if (!hw->is_idle)
643	938	goto end;
644	939	if (hw->monitor.state & ISP_MIPI_ERROR && hw->monitor.is_en)
645	940	goto end;
	941	+ if (!IS_HDR_RDBK(dev->rd_mode))
	942	+ goto end;
	943	+ if (dev->is_suspend) {
	944	+ if (dev->suspend_sync)
	945	+ complete(&dev->pm_cmpl);
	946	+ goto end;
	947	+ }
646	948
647	949	for (i = 0; i < hw->dev_num; i++) {
648	950	isp = hw->isp[i];
649		- if (!(isp->isp_state & ISP_START))
	951	+ if (!isp \|\|
	952	+ (isp && (!(isp->isp_state & ISP_START) \|\| isp->is_suspend)))
650	953	continue;
651	954	rkisp_rdbk_trigger_event(isp, T_CMD_LEN, &len[i]);
652	955	if (max < len[i]) {
..	..	@@ -655,10 +958,14 @@
655	958	}
656	959	}
657	960
	961	+ /* wait 2 frame to start isp for fast */
	962	+ if (dev->is_rtt_first && max == 1 && !atomic_read(&dev->isp_sdev.frm_sync_seq))
	963	+ goto end;
	964	+
658	965	if (max) {
659		- v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
660		- "trigger fifo len:%d\n", max);
661	966	isp = hw->isp[id];
	967	+ v4l2_dbg(2, rkisp_debug, &isp->v4l2_dev,
	968	+ "trigger fifo len:%d\n", max);
662	969	rkisp_rdbk_trigger_event(isp, T_CMD_DEQUEUE, &t);
663	970	isp->dmarx_dev.pre_frame = isp->dmarx_dev.cur_frame;
664	971	if (t.frame_id > isp->dmarx_dev.pre_frame.id &&
..	..	@@ -669,15 +976,52 @@
669	976	isp->dmarx_dev.cur_frame.sof_timestamp = t.sof_timestamp;
670	977	isp->dmarx_dev.cur_frame.timestamp = t.frame_timestamp;
671	978	isp->isp_sdev.frm_timestamp = t.sof_timestamp;
	979	+ atomic_set(&isp->isp_sdev.frm_sync_seq, t.frame_id + 1);
672	980	mode = t.mode;
673	981	times = t.times;
674	982	hw->cur_dev_id = id;
675	983	hw->is_idle = false;
	984	+ /* this frame will read count by isp */
	985	+ isp->sw_rd_cnt = 0;
	986	+ /* frame double for multi camera resolution out of hardware limit
	987	+ * first for HW save this camera information, and second to output image
	988	+ */
	989	+ isp->is_frame_double = false;
	990	+ if (hw->is_multi_overflow &&
	991	+ (hw->unite == ISP_UNITE_ONE \|\|
	992	+ (hw->pre_dev_id != -1 && hw->pre_dev_id != id))) {
	993	+ isp->is_frame_double = true;
	994	+ isp->sw_rd_cnt = 1;
	995	+ times = 0;
	996	+ }
	997	+ /* resolution out of hardware limit
	998	+ * frame is vertically divided into left and right
	999	+ */
	1000	+ isp->unite_index = ISP_UNITE_LEFT;
	1001	+ if (hw->unite == ISP_UNITE_ONE) {
	1002	+ isp->sw_rd_cnt *= 2;
	1003	+ isp->sw_rd_cnt += 1;
	1004	+ }
	1005	+ /* first frame handle twice for thunderboot
	1006	+ * first output stats to AIQ and wait new params to run second
	1007	+ */
	1008	+ if (isp->is_rtt_first && t.frame_id == 0) {
	1009	+ isp->is_first_double = true;
	1010	+ isp->skip_frame = 1;
	1011	+ if (hw->unite != ISP_UNITE_ONE) {
	1012	+ isp->sw_rd_cnt = 0;
	1013	+ isp->is_frame_double = false;
	1014	+ }
	1015	+ rkisp_fast_switch_rx_buf(isp, false);
	1016	+ } else {
	1017	+ isp->is_rtt_first = false;
	1018	+ }
	1019	+ isp->params_vdev.rdbk_times = isp->sw_rd_cnt + 1;
676	1020	}
677	1021	end:
678	1022	spin_unlock_irqrestore(&hw->rdbk_lock, lock_flags);
679	1023	if (times >= 0)
680		- rkisp_trigger_read_back(isp, times, mode, false);
	1024	+ rkisp_trigger_read_back(isp, times, mode, is_try);
681	1025	}
682	1026
683	1027	int rkisp_rdbk_trigger_event(struct rkisp_device dev, u32 cmd, void arg)
..	..	@@ -686,9 +1030,6 @@
686	1030	struct isp2x_csi_trigger *trigger = NULL;
687	1031	unsigned long lock_flags = 0;
688	1032	int val, ret = 0;
689		-
690		- if (dev->dmarx_dev.trigger != T_MANUAL)
691		- return 0;
692	1033
693	1034	spin_lock_irqsave(&dev->rdbk_lock, lock_flags);
694	1035	switch (cmd) {
..	..	@@ -721,6 +1062,14 @@
721	1062	return ret;
722	1063	}
723	1064
	1065	+static void rkisp_rdbk_work(struct work_struct *work)
	1066	+{
	1067	+ struct rkisp_device *dev = container_of(work, struct rkisp_device, rdbk_work);
	1068	+
	1069	+ rkisp_dvfs(dev);
	1070	+ rkisp_rdbk_trigger_event(dev, T_CMD_END, NULL);
	1071	+}
	1072	+
724	1073	void rkisp_check_idle(struct rkisp_device *dev, u32 irq)
725	1074	{
726	1075	u32 val = 0;
..	..	@@ -735,13 +1084,38 @@
735	1084	if (!completion_done(&dev->hw_dev->monitor.cmpl))
736	1085	complete(&dev->hw_dev->monitor.cmpl);
737	1086	}
738		- if (dev->irq_ends != dev->irq_ends_mask \|\| !IS_HDR_RDBK(dev->rd_mode))
	1087	+ if ((dev->irq_ends & dev->irq_ends_mask) != dev->irq_ends_mask \|\|
	1088	+ !IS_HDR_RDBK(dev->rd_mode))
739	1089	return;
740	1090
741		- if (!(dev->irq_ends_mask & (ISP_FRAME_MP \| ISP_FRAME_SP \| ISP_FRAME_MPFBC)))
742		- dev->isp_state = ISP_STOP;
	1091	+ if (dev->sw_rd_cnt)
	1092	+ goto end;
743	1093
744		- dev->irq_ends = 0;
	1094	+ if (dev->is_first_double) {
	1095	+ rkisp_fast_switch_rx_buf(dev, true);
	1096	+ dev->is_rtt_first = false;
	1097	+ dev->skip_frame = 0;
	1098	+ dev->irq_ends = 0;
	1099	+ return;
	1100	+ }
	1101	+
	1102	+ /* check output stream is off */
	1103	+ val = ISP_FRAME_MP \| ISP_FRAME_SP \| ISP_FRAME_MPFBC \| ISP_FRAME_BP;
	1104	+ if (!(dev->irq_ends_mask & val)) {
	1105	+ u32 state = dev->isp_state;
	1106	+ struct rkisp_stream *s;
	1107	+
	1108	+ for (val = 0; val < RKISP_STREAM_VIR; val++) {
	1109	+ s = &dev->cap_dev.stream[val];
	1110	+ dev->isp_state = ISP_STOP;
	1111	+ if (s->streaming) {
	1112	+ dev->isp_state = state;
	1113	+ break;
	1114	+ }
	1115	+ }
	1116	+ }
	1117	+
	1118	+ val = 0;
745	1119	switch (dev->rd_mode) {
746	1120	case HDR_RDBK_FRAME3://for rd1 rd0 rd2
747	1121	val \|= RAW1_RD_FRAME;
..	..	@@ -754,9 +1128,12 @@
754	1128	/* FALLTHROUGH */
755	1129	}
756	1130	rkisp2_rawrd_isr(val, dev);
757		- if (!(dev->irq_ends_mask & (ISP_FRAME_MP \| ISP_FRAME_SP \| ISP_FRAME_MPFBC)))
758		- dev->isp_state = ISP_STOP;
759		- if (dev->dmarx_dev.trigger == T_MANUAL)
	1131	+
	1132	+end:
	1133	+ dev->irq_ends = 0;
	1134	+ if (dev->hw_dev->is_dvfs)
	1135	+ schedule_work(&dev->rdbk_work);
	1136	+ else
760	1137	rkisp_rdbk_trigger_event(dev, T_CMD_END, NULL);
761	1138	if (dev->isp_state == ISP_STOP)
762	1139	wake_up(&dev->sync_onoff);
..	..	@@ -779,113 +1156,48 @@
779	1156	*/
780	1157	static void rkisp_config_ism(struct rkisp_device *dev)
781	1158	{
782		- void __iomem *base = dev->base_addr;
783	1159	struct v4l2_rect *out_crop = &dev->isp_sdev.out_crop;
784		- u32 val;
	1160	+ u32 width = out_crop->width, mult = 1;
	1161	+ u32 unite = dev->hw_dev->unite;
785	1162
786	1163	/* isp2.0 no ism */
787		- if (dev->isp_ver == ISP_V20 \|\| dev->isp_ver == ISP_V21)
	1164	+ if (dev->isp_ver == ISP_V20 \|\| dev->isp_ver == ISP_V21 \|\|
	1165	+ dev->isp_ver == ISP_V32_L)
788	1166	return;
789	1167
790		- writel(0, base + CIF_ISP_IS_RECENTER);
791		- writel(0, base + CIF_ISP_IS_MAX_DX);
792		- writel(0, base + CIF_ISP_IS_MAX_DY);
793		- writel(0, base + CIF_ISP_IS_DISPLACE);
794		- writel(out_crop->left, base + CIF_ISP_IS_H_OFFS);
795		- writel(out_crop->top, base + CIF_ISP_IS_V_OFFS);
796		- writel(out_crop->width, base + CIF_ISP_IS_H_SIZE);
	1168	+ if (unite)
	1169	+ width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
	1170	+ rkisp_unite_write(dev, CIF_ISP_IS_RECENTER, 0, false);
	1171	+ rkisp_unite_write(dev, CIF_ISP_IS_MAX_DX, 0, false);
	1172	+ rkisp_unite_write(dev, CIF_ISP_IS_MAX_DY, 0, false);
	1173	+ rkisp_unite_write(dev, CIF_ISP_IS_DISPLACE, 0, false);
	1174	+ rkisp_unite_write(dev, CIF_ISP_IS_H_OFFS, out_crop->left, false);
	1175	+ rkisp_unite_write(dev, CIF_ISP_IS_V_OFFS, out_crop->top, false);
	1176	+ rkisp_unite_write(dev, CIF_ISP_IS_H_SIZE, width, false);
797	1177	if (dev->cap_dev.stream[RKISP_STREAM_SP].interlaced)
798		- writel(out_crop->height / 2, base + CIF_ISP_IS_V_SIZE);
799		- else
800		- writel(out_crop->height, base + CIF_ISP_IS_V_SIZE);
	1178	+ mult = 2;
	1179	+ rkisp_unite_write(dev, CIF_ISP_IS_V_SIZE, out_crop->height / mult, false);
	1180	+
	1181	+ if (dev->isp_ver == ISP_V30 \|\| dev->isp_ver == ISP_V32)
	1182	+ return;
801	1183
802	1184	/* IS(Image Stabilization) is always on, working as output crop */
803		- writel(1, base + CIF_ISP_IS_CTRL);
804		- val = readl(base + CIF_ISP_CTRL);
805		- val \|= CIF_ISP_CTRL_ISP_CFG_UPD;
806		- writel(val, base + CIF_ISP_CTRL);
	1185	+ rkisp_write(dev, CIF_ISP_IS_CTRL, 1, false);
807	1186	}
808	1187
809		-static int rkisp_reset_handle_v2x(struct rkisp_device *dev)
	1188	+static int rkisp_reset_handle(struct rkisp_device *dev)
810	1189	{
811		- void __iomem *base = dev->base_addr;
812		- void *reg_buf = NULL;
813		- u32 reg, reg1, i;
814		- struct backup_reg backup[] = {
815		- {
816		- .base = MI_MP_WR_Y_BASE,
817		- .shd = MI_MP_WR_Y_BASE_SHD,
818		- }, {
819		- .base = MI_MP_WR_CB_BASE,
820		- .shd = MI_MP_WR_CB_BASE_SHD,
821		- }, {
822		- .base = MI_MP_WR_CR_BASE,
823		- .shd = MI_MP_WR_CR_BASE_SHD,
824		- }, {
825		- .base = MI_SP_WR_Y_BASE,
826		- .shd = MI_SP_WR_Y_BASE_SHD,
827		- }, {
828		- .base = MI_SP_WR_CB_BASE,
829		- .shd = MI_SP_WR_CB_BASE_AD_SHD,
830		- }, {
831		- .base = MI_SP_WR_CR_BASE,
832		- .shd = MI_SP_WR_CR_BASE_AD_SHD,
833		- }, {
834		- .base = MI_RAW0_WR_BASE,
835		- .shd = MI_RAW0_WR_BASE_SHD,
836		- }, {
837		- .base = MI_RAW1_WR_BASE,
838		- .shd = MI_RAW1_WR_BASE_SHD,
839		- }, {
840		- .base = MI_RAW2_WR_BASE,
841		- .shd = MI_RAW2_WR_BASE_SHD,
842		- }, {
843		- .base = MI_RAW3_WR_BASE,
844		- .shd = MI_RAW3_WR_BASE_SHD,
845		- }, {
846		- .base = MI_RAW0_RD_BASE,
847		- .shd = MI_RAW0_RD_BASE_SHD,
848		- }, {
849		- .base = MI_RAW1_RD_BASE,
850		- .shd = MI_RAW1_RD_BASE_SHD,
851		- }, {
852		- .base = MI_RAW2_RD_BASE,
853		- .shd = MI_RAW2_RD_BASE_SHD,
854		- }, {
855		- .base = MI_GAIN_WR_BASE,
856		- .shd = MI_GAIN_WR_BASE_SHD,
857		- }
858		- };
859		-
860		- reg_buf = kzalloc(RKISP_ISP_SW_REG_SIZE, GFP_KERNEL);
861		- if (!reg_buf)
862		- return -ENOMEM;
	1190	+ u32 val;
863	1191
864	1192	dev_info(dev->dev, "%s enter\n", __func__);
	1193	+ rkisp_hw_reg_save(dev->hw_dev);
865	1194
866		- memcpy_fromio(reg_buf, base, RKISP_ISP_SW_REG_SIZE);
867	1195	rkisp_soft_reset(dev->hw_dev, true);
868	1196
869		- /* process special reg */
870		- reg = reg_buf + ISP_CTRL;
871		- *reg &= ~(CIF_ISP_CTRL_ISP_ENABLE \|
872		- CIF_ISP_CTRL_ISP_INFORM_ENABLE \|
873		- CIF_ISP_CTRL_ISP_CFG_UPD);
874		- reg = reg_buf + MI_WR_INIT;
875		- *reg = 0;
876		- reg = reg_buf + CSI2RX_CTRL0;
877		- *reg &= ~SW_CSI2RX_EN;
878		- /* skip mmu range */
879		- memcpy_toio(base, reg_buf, ISP21_MI_BAY3D_RD_BASE_SHD);
880		- memcpy_toio(base + CSI2RX_CTRL0, reg_buf + CSI2RX_CTRL0,
881		- RKISP_ISP_SW_REG_SIZE - CSI2RX_CTRL0);
882		- /* config shd_reg to base_reg */
883		- for (i = 0; i < ARRAY_SIZE(backup); i++) {
884		- reg = reg_buf + backup[i].base;
885		- reg1 = reg_buf + backup[i].shd;
886		- backup[i].val = *reg;
887		- writel(*reg1, base + backup[i].base);
888		- }
	1197	+ rkisp_hw_reg_restore(dev->hw_dev);
	1198	+
	1199	+ val = CIF_ISP_DATA_LOSS \| CIF_ISP_PIC_SIZE_ERROR;
	1200	+ rkisp_unite_set_bits(dev, CIF_ISP_IMSC, 0, val, true);
889	1201
890	1202	/* clear state */
891	1203	dev->isp_err_cnt = 0;
..	..	@@ -893,40 +1205,12 @@
893	1205	rkisp_set_state(&dev->isp_state, ISP_FRAME_END);
894	1206	dev->hw_dev->monitor.state = ISP_FRAME_END;
895	1207
896		- /* update module */
897		- reg = reg_buf + DUAL_CROP_CTRL;
898		- if (*reg & 0xf)
899		- writel(*reg \| CIF_DUAL_CROP_CFG_UPD, base + DUAL_CROP_CTRL);
900		- reg = reg_buf + SELF_RESIZE_CTRL;
901		- if (*reg & 0xf)
902		- writel(*reg \| CIF_RSZ_CTRL_CFG_UPD, base + SELF_RESIZE_CTRL);
903		- reg = reg_buf + MAIN_RESIZE_CTRL;
904		- if (*reg & 0xf)
905		- writel(*reg \| CIF_RSZ_CTRL_CFG_UPD, base + MAIN_RESIZE_CTRL);
906		-
907		- /* update mi and isp, base_reg will update to shd_reg */
908		- force_cfg_update(dev);
909		- reg = reg_buf + ISP_CTRL;
910		- *reg \|= CIF_ISP_CTRL_ISP_ENABLE \|
911		- CIF_ISP_CTRL_ISP_INFORM_ENABLE \|
912		- CIF_ISP_CTRL_ISP_CFG_UPD;
913		- writel(*reg, base + ISP_CTRL);
914		- udelay(50);
915		- /* config base_reg */
916		- for (i = 0; i < ARRAY_SIZE(backup); i++)
917		- writel(backup[i].val, base + backup[i].base);
918		- /* mpfbc base_reg = shd_reg, write is base but read is shd */
919		- if (dev->isp_ver == ISP_V20)
920		- writel(rkisp_read_reg_cache(dev, ISP_MPFBC_HEAD_PTR),
921		- base + ISP_MPFBC_HEAD_PTR);
922		- rkisp_set_bits(dev, CIF_ISP_IMSC, 0, CIF_ISP_DATA_LOSS \| CIF_ISP_PIC_SIZE_ERROR, true);
923	1208	if (IS_HDR_RDBK(dev->hdr.op_mode)) {
924	1209	if (!dev->hw_dev->is_idle)
925	1210	rkisp_trigger_read_back(dev, 1, 0, true);
926	1211	else
927	1212	rkisp_rdbk_trigger_event(dev, T_CMD_QUEUE, NULL);
928	1213	}
929		- kfree(reg_buf);
930	1214	dev_info(dev->dev, "%s exit\n", __func__);
931	1215	return 0;
932	1216	}
..	..	@@ -940,11 +1224,6 @@
940	1224	struct rkisp_pipeline *p;
941	1225	int ret, i, j, timeout = 5, mipi_irq_cnt = 0;
942	1226
943		- if (!monitor->reset_handle) {
944		- monitor->is_en = false;
945		- return;
946		- }
947		-
948	1227	dev_info(hw->dev, "%s enter\n", __func__);
949	1228	while (!(monitor->state & ISP_STOP) && monitor->is_en) {
950	1229	ret = wait_for_completion_timeout(&monitor->cmpl,
..	..	@@ -952,15 +1231,18 @@
952	1231	/* isp stop to exit
953	1232	* isp err to reset
954	1233	* mipi err wait isp idle, then reset
	1234	+ * online vicap if isp err, notify vicap reset, then vicap notify isp reset
	1235	+ * by ioctl RKISP_VICAP_CMD_SET_STREAM
955	1236	*/
956	1237	if (monitor->state & ISP_STOP \|\|
	1238	+ monitor->state & ISP_CIF_RESET \|\|
957	1239	(ret && !(monitor->state & ISP_ERROR)) \|\|
958	1240	(!ret &&
959	1241	monitor->state & ISP_FRAME_END &&
960	1242	!(monitor->state & ISP_MIPI_ERROR))) {
961	1243	for (i = 0; i < hw->dev_num; i++) {
962	1244	isp = hw->isp[i];
963		- if (!(isp->isp_inp & INP_CSI))
	1245	+ if (!isp \|\| (isp && !(isp->isp_inp & INP_CSI)))
964	1246	continue;
965	1247	if (!(isp->isp_state & ISP_START))
966	1248	break;
..	..	@@ -982,6 +1264,8 @@
982	1264	}
983	1265	for (i = 0; i < hw->dev_num; i++) {
984	1266	isp = hw->isp[i];
	1267	+ if (!isp)
	1268	+ continue;
985	1269	if (isp->isp_inp & INP_CSI \|\|
986	1270	isp->isp_inp & INP_DVP \|\|
987	1271	isp->isp_inp & INP_LVDS) {
..	..	@@ -1000,14 +1284,28 @@
1000	1284
1001	1285	/* restart isp */
1002	1286	isp = hw->isp[hw->cur_dev_id];
1003		- ret = monitor->reset_handle(isp);
1004		- if (ret) {
1005		- monitor->is_en = false;
1006		- break;
	1287	+ if (!IS_HDR_RDBK(isp->hdr.op_mode) && isp->isp_ver >= ISP_V30) {
	1288	+ struct v4l2_subdev *remote = NULL;
	1289	+ struct v4l2_subdev *isp_subdev = NULL;
	1290	+
	1291	+ isp_subdev = &(isp->isp_sdev.sd);
	1292	+ remote = get_remote_sensor(isp_subdev);
	1293	+ v4l2_subdev_call(remote, core, ioctl,
	1294	+ RKISP_VICAP_CMD_SET_RESET, NULL);
	1295	+ monitor->state \|= ISP_CIF_RESET;
	1296	+ continue;
	1297	+ } else {
	1298	+ ret = rkisp_reset_handle(isp);
	1299	+ if (ret) {
	1300	+ monitor->is_en = false;
	1301	+ break;
	1302	+ }
1007	1303	}
1008	1304
1009	1305	for (i = 0; i < hw->dev_num; i++) {
1010	1306	isp = hw->isp[i];
	1307	+ if (!isp)
	1308	+ continue;
1011	1309	if (isp->isp_inp & INP_CSI \|\|
1012	1310	isp->isp_inp & INP_DVP \|\|
1013	1311	isp->isp_inp & INP_LVDS) {
..	..	@@ -1035,9 +1333,6 @@
1035	1333	struct rkisp_monitor *monitor = &dev->hw_dev->monitor;
1036	1334
1037	1335	monitor->dev = dev->hw_dev;
1038		- monitor->reset_handle = NULL;
1039		- if (dev->isp_ver == ISP_V20 \|\| dev->isp_ver == ISP_V21)
1040		- monitor->reset_handle = rkisp_reset_handle_v2x;
1041	1336
1042	1337	init_completion(&monitor->cmpl);
1043	1338	INIT_WORK(&monitor->work, rkisp_restart_monitor);
..	..	@@ -1061,6 +1356,8 @@
1061	1356	*/
1062	1357	static void rkisp_config_color_space(struct rkisp_device *dev)
1063	1358	{
	1359	+ u32 val = 0;
	1360	+
1064	1361	u16 bt601_coeff[] = {
1065	1362	0x0026, 0x004b, 0x000f,
1066	1363	0x01ea, 0x01d6, 0x0040,
..	..	@@ -1092,16 +1389,222 @@
1092	1389	}
1093	1390
1094	1391	for (i = 0; i < 9; i++)
1095		- rkisp_write(dev, CIF_ISP_CC_COEFF_0 + i * 4, *(coeff + i), false);
	1392	+ rkisp_unite_write(dev, CIF_ISP_CC_COEFF_0 + i * 4,
	1393	+ *(coeff + i), false);
	1394	+
	1395	+ val = rkisp_read_reg_cache(dev, CIF_ISP_CTRL);
1096	1396
1097	1397	if (dev->isp_sdev.quantization == V4L2_QUANTIZATION_FULL_RANGE)
1098		- rkisp_set_bits(dev, CIF_ISP_CTRL, 0,
1099		- CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA \|
1100		- CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA, false);
	1398	+ rkisp_unite_write(dev, CIF_ISP_CTRL, val \|
	1399	+ CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA \|
	1400	+ CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA, false);
1101	1401	else
1102		- rkisp_clear_bits(dev, CIF_ISP_CTRL,
1103		- CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA \|
1104		- CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA, false);
	1402	+ rkisp_unite_write(dev, CIF_ISP_CTRL, val &
	1403	+ ~(CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA \|
	1404	+ CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA), false);
	1405	+}
	1406	+
	1407	+static void rkisp_config_cmsk_single(struct rkisp_device *dev,
	1408	+ struct rkisp_cmsk_cfg *cfg)
	1409	+{
	1410	+ u32 i, val, ctrl = 0;
	1411	+ u32 mp_en = cfg->win[0].win_en;
	1412	+ u32 sp_en = cfg->win[1].win_en;
	1413	+ u32 bp_en = cfg->win[2].win_en;
	1414	+ u32 win_max = (dev->isp_ver == ISP_V30) ?
	1415	+ RKISP_CMSK_WIN_MAX_V30 : RKISP_CMSK_WIN_MAX;
	1416	+
	1417	+ if (mp_en) {
	1418	+ ctrl \|= ISP3X_SW_CMSK_EN_MP;
	1419	+ rkisp_write(dev, ISP3X_CMSK_CTRL1, mp_en, false);
	1420	+ val = cfg->win[0].mode;
	1421	+ rkisp_write(dev, ISP3X_CMSK_CTRL4, val, false);
	1422	+ }
	1423	+
	1424	+ if (sp_en) {
	1425	+ ctrl \|= ISP3X_SW_CMSK_EN_SP;
	1426	+ rkisp_write(dev, ISP3X_CMSK_CTRL2, sp_en, false);
	1427	+ val = cfg->win[1].mode;
	1428	+ rkisp_write(dev, ISP3X_CMSK_CTRL5, val, false);
	1429	+ }
	1430	+
	1431	+ if (bp_en) {
	1432	+ ctrl \|= ISP3X_SW_CMSK_EN_BP;
	1433	+ rkisp_write(dev, ISP3X_CMSK_CTRL3, bp_en, false);
	1434	+ val = cfg->win[2].mode;
	1435	+ rkisp_write(dev, ISP3X_CMSK_CTRL6, val, false);
	1436	+ }
	1437	+
	1438	+ for (i = 0; i < win_max; i++) {
	1439	+ if (!(mp_en & BIT(i)) && !(sp_en & BIT(i)) && !(bp_en & BIT(i)))
	1440	+ continue;
	1441	+
	1442	+ val = ISP3X_SW_CMSK_YUV(cfg->win[i].cover_color_y,
	1443	+ cfg->win[i].cover_color_u,
	1444	+ cfg->win[i].cover_color_v);
	1445	+ rkisp_write(dev, ISP3X_CMSK_YUV0 + i * 4, val, false);
	1446	+
	1447	+ val = ISP_PACK_2SHORT(cfg->win[i].h_offs, cfg->win[i].v_offs);
	1448	+ rkisp_write(dev, ISP3X_CMSK_OFFS0 + i * 8, val, false);
	1449	+
	1450	+ val = ISP_PACK_2SHORT(cfg->win[i].h_size, cfg->win[i].v_size);
	1451	+ rkisp_write(dev, ISP3X_CMSK_SIZE0 + i * 8, val, false);
	1452	+ }
	1453	+
	1454	+ if (ctrl) {
	1455	+ val = ISP_PACK_2SHORT(dev->isp_sdev.out_crop.width,
	1456	+ dev->isp_sdev.out_crop.height);
	1457	+ rkisp_write(dev, ISP3X_CMSK_PIC_SIZE, val, false);
	1458	+ ctrl \|= ISP3X_SW_CMSK_EN \| ISP3X_SW_CMSK_ORDER_MODE;
	1459	+ ctrl \|= ISP3X_SW_CMSK_BLKSIZE(cfg->mosaic_block);
	1460	+ }
	1461	+ rkisp_write(dev, ISP3X_CMSK_CTRL0, ctrl, false);
	1462	+
	1463	+ val = rkisp_read(dev, ISP3X_CMSK_CTRL0, true);
	1464	+ if (dev->hw_dev->is_single &&
	1465	+ ((val & ISP32_SW_CMSK_EN_PATH) != (val & ISP32_SW_CMSK_EN_PATH_SHD)))
	1466	+ rkisp_write(dev, ISP3X_CMSK_CTRL0, val \| ISP3X_SW_CMSK_FORCE_UPD, true);
	1467	+}
	1468	+
	1469	+static void rkisp_config_cmsk_dual(struct rkisp_device *dev,
	1470	+ struct rkisp_cmsk_cfg *cfg)
	1471	+{
	1472	+ struct rkisp_cmsk_cfg left = *cfg;
	1473	+ struct rkisp_cmsk_cfg right = *cfg;
	1474	+ u32 width = dev->isp_sdev.out_crop.width;
	1475	+ u32 height = dev->isp_sdev.out_crop.height;
	1476	+ u32 w = width / 2;
	1477	+ u32 i, val, h_offs, h_size, ctrl;
	1478	+ u8 mp_en = cfg->win[0].win_en;
	1479	+ u8 sp_en = cfg->win[1].win_en;
	1480	+ u8 bp_en = cfg->win[2].win_en;
	1481	+ u32 win_max = (dev->isp_ver == ISP_V30) ?
	1482	+ RKISP_CMSK_WIN_MAX_V30 : RKISP_CMSK_WIN_MAX;
	1483	+
	1484	+ for (i = 0; i < win_max; i++) {
	1485	+ if (!(mp_en & BIT(i)) && !(sp_en & BIT(i)) && !(bp_en & BIT(i)))
	1486	+ continue;
	1487	+
	1488	+ h_offs = cfg->win[i].h_offs;
	1489	+ h_size = cfg->win[i].h_size;
	1490	+ if (h_offs + h_size <= w) {
	1491	+ /* cmsk window at left isp */
	1492	+ right.win[0].win_en &= ~BIT(i);
	1493	+ right.win[1].win_en &= ~BIT(i);
	1494	+ right.win[2].win_en &= ~BIT(i);
	1495	+ } else if (h_offs >= w) {
	1496	+ /* cmsk window at right isp */
	1497	+ left.win[0].win_en &= ~BIT(i);
	1498	+ left.win[1].win_en &= ~BIT(i);
	1499	+ left.win[2].win_en &= ~BIT(i);
	1500	+ right.win[i].h_offs = h_offs - w + RKMOUDLE_UNITE_EXTEND_PIXEL;
	1501	+ } else {
	1502	+ /* cmsk window at dual isp */
	1503	+ left.win[i].h_size = ALIGN(w - h_offs, 8);
	1504	+
	1505	+ right.win[i].h_offs = RKMOUDLE_UNITE_EXTEND_PIXEL;
	1506	+ val = h_offs + h_size - w;
	1507	+ right.win[i].h_size = ALIGN(val, 8);
	1508	+ right.win[i].h_offs -= right.win[i].h_size - val;
	1509	+ }
	1510	+
	1511	+ val = ISP3X_SW_CMSK_YUV(left.win[i].cover_color_y,
	1512	+ left.win[i].cover_color_u,
	1513	+ left.win[i].cover_color_v);
	1514	+ rkisp_write(dev, ISP3X_CMSK_YUV0 + i * 4, val, false);
	1515	+ rkisp_next_write(dev, ISP3X_CMSK_YUV0 + i * 4, val, false);
	1516	+
	1517	+ val = ISP_PACK_2SHORT(left.win[i].h_offs, left.win[i].v_offs);
	1518	+ rkisp_write(dev, ISP3X_CMSK_OFFS0 + i * 8, val, false);
	1519	+ val = ISP_PACK_2SHORT(left.win[i].h_size, left.win[i].v_size);
	1520	+ rkisp_write(dev, ISP3X_CMSK_SIZE0 + i * 8, val, false);
	1521	+
	1522	+ val = ISP_PACK_2SHORT(right.win[i].h_offs, right.win[i].v_offs);
	1523	+ rkisp_next_write(dev, ISP3X_CMSK_OFFS0 + i * 8, val, false);
	1524	+ val = ISP_PACK_2SHORT(right.win[i].h_size, right.win[i].v_size);
	1525	+ rkisp_next_write(dev, ISP3X_CMSK_SIZE0 + i * 8, val, false);
	1526	+ }
	1527	+
	1528	+ w += RKMOUDLE_UNITE_EXTEND_PIXEL;
	1529	+ ctrl = 0;
	1530	+ if (left.win[0].win_en) {
	1531	+ ctrl \|= ISP3X_SW_CMSK_EN_MP;
	1532	+ rkisp_write(dev, ISP3X_CMSK_CTRL1, left.win[0].win_en, false);
	1533	+ val = left.win[0].mode;
	1534	+ rkisp_write(dev, ISP3X_CMSK_CTRL4, val, false);
	1535	+ }
	1536	+ if (left.win[1].win_en) {
	1537	+ ctrl \|= ISP3X_SW_CMSK_EN_SP;
	1538	+ rkisp_write(dev, ISP3X_CMSK_CTRL2, left.win[1].win_en, false);
	1539	+ val = left.win[1].mode;
	1540	+ rkisp_write(dev, ISP3X_CMSK_CTRL5, val, false);
	1541	+ }
	1542	+ if (left.win[2].win_en) {
	1543	+ ctrl \|= ISP3X_SW_CMSK_EN_BP;
	1544	+ rkisp_write(dev, ISP3X_CMSK_CTRL3, left.win[2].win_en, false);
	1545	+ val = left.win[2].mode;
	1546	+ rkisp_write(dev, ISP3X_CMSK_CTRL6, val, false);
	1547	+ }
	1548	+ if (ctrl) {
	1549	+ val = ISP_PACK_2SHORT(w, height);
	1550	+ rkisp_write(dev, ISP3X_CMSK_PIC_SIZE, val, false);
	1551	+ ctrl \|= ISP3X_SW_CMSK_EN \| ISP3X_SW_CMSK_ORDER_MODE;
	1552	+ }
	1553	+ rkisp_write(dev, ISP3X_CMSK_CTRL0, ctrl, false);
	1554	+
	1555	+ ctrl = 0;
	1556	+ if (right.win[0].win_en) {
	1557	+ ctrl \|= ISP3X_SW_CMSK_EN_MP;
	1558	+ rkisp_next_write(dev, ISP3X_CMSK_CTRL1, right.win[0].win_en, false);
	1559	+ val = right.win[0].mode;
	1560	+ rkisp_next_write(dev, ISP3X_CMSK_CTRL4, val, false);
	1561	+ }
	1562	+ if (right.win[1].win_en) {
	1563	+ ctrl \|= ISP3X_SW_CMSK_EN_SP;
	1564	+ rkisp_next_write(dev, ISP3X_CMSK_CTRL2, right.win[1].win_en, false);
	1565	+ val = right.win[1].mode;
	1566	+ rkisp_next_write(dev, ISP3X_CMSK_CTRL5, val, false);
	1567	+ }
	1568	+ if (right.win[2].win_en) {
	1569	+ ctrl \|= ISP3X_SW_CMSK_EN_BP;
	1570	+ rkisp_next_write(dev, ISP3X_CMSK_CTRL3, right.win[2].win_en, false);
	1571	+ val = right.win[2].mode;
	1572	+ rkisp_next_write(dev, ISP3X_CMSK_CTRL6, val, false);
	1573	+ }
	1574	+ if (ctrl) {
	1575	+ val = ISP_PACK_2SHORT(w, height);
	1576	+ rkisp_next_write(dev, ISP3X_CMSK_PIC_SIZE, val, false);
	1577	+ ctrl \|= ISP3X_SW_CMSK_EN \| ISP3X_SW_CMSK_ORDER_MODE;
	1578	+ }
	1579	+ rkisp_next_write(dev, ISP3X_CMSK_CTRL0, ctrl, false);
	1580	+
	1581	+ val = rkisp_next_read(dev, ISP3X_CMSK_CTRL0, true);
	1582	+ if (dev->hw_dev->is_single &&
	1583	+ ((val & ISP32_SW_CMSK_EN_PATH) != (val & ISP32_SW_CMSK_EN_PATH_SHD)))
	1584	+ rkisp_next_write(dev, ISP3X_CMSK_CTRL0, val \| ISP3X_SW_CMSK_FORCE_UPD, false);
	1585	+}
	1586	+
	1587	+static void rkisp_config_cmsk(struct rkisp_device *dev)
	1588	+{
	1589	+ unsigned long lock_flags = 0;
	1590	+ struct rkisp_cmsk_cfg cfg;
	1591	+
	1592	+ if (dev->isp_ver != ISP_V30 && dev->isp_ver != ISP_V32)
	1593	+ return;
	1594	+
	1595	+ spin_lock_irqsave(&dev->cmsk_lock, lock_flags);
	1596	+ if (!dev->is_cmsk_upd) {
	1597	+ spin_unlock_irqrestore(&dev->cmsk_lock, lock_flags);
	1598	+ return;
	1599	+ }
	1600	+ dev->is_cmsk_upd = false;
	1601	+ cfg = dev->cmsk_cfg;
	1602	+ spin_unlock_irqrestore(&dev->cmsk_lock, lock_flags);
	1603	+
	1604	+ if (!dev->hw_dev->unite)
	1605	+ rkisp_config_cmsk_single(dev, &cfg);
	1606	+ else
	1607	+ rkisp_config_cmsk_dual(dev, &cfg);
1105	1608	}
1106	1609
1107	1610	/*
..	..	@@ -1113,17 +1616,20 @@
1113	1616	struct ispsd_out_fmt *out_fmt;
1114	1617	struct v4l2_rect *in_crop;
1115	1618	struct rkisp_sensor_info *sensor;
	1619	+ bool is_unite = !!dev->hw_dev->unite;
1116	1620	u32 isp_ctrl = 0;
1117	1621	u32 irq_mask = 0;
1118	1622	u32 signal = 0;
1119	1623	u32 acq_mult = 0;
1120	1624	u32 acq_prop = 0;
1121	1625	u32 extend_line = 0;
	1626	+ u32 width;
1122	1627
1123	1628	sensor = dev->active_sensor;
1124	1629	in_fmt = &dev->isp_sdev.in_fmt;
1125	1630	out_fmt = &dev->isp_sdev.out_fmt;
1126	1631	in_crop = &dev->isp_sdev.in_crop;
	1632	+ width = in_crop->width;
1127	1633
1128	1634	if (in_fmt->fmt_type == FMT_BAYER) {
1129	1635	acq_mult = 1;
..	..	@@ -1139,21 +1645,21 @@
1139	1645	if (in_fmt->mbus_code == MEDIA_BUS_FMT_Y8_1X8 \|\|
1140	1646	in_fmt->mbus_code == MEDIA_BUS_FMT_Y10_1X10 \|\|
1141	1647	in_fmt->mbus_code == MEDIA_BUS_FMT_Y12_1X12) {
1142		- if (dev->isp_ver == ISP_V20 \|\| dev->isp_ver == ISP_V21)
1143		- rkisp_write(dev, ISP_DEBAYER_CONTROL, 0, false);
	1648	+ if (dev->isp_ver >= ISP_V20)
	1649	+ rkisp_unite_write(dev, ISP_DEBAYER_CONTROL, 0, false);
1144	1650	else
1145	1651	rkisp_write(dev, CIF_ISP_DEMOSAIC,
1146		- CIF_ISP_DEMOSAIC_BYPASS \|
1147		- CIF_ISP_DEMOSAIC_TH(0xc), false);
	1652	+ CIF_ISP_DEMOSAIC_BYPASS \|
	1653	+ CIF_ISP_DEMOSAIC_TH(0xc), false);
1148	1654	} else {
1149		- if (dev->isp_ver == ISP_V20 \|\| dev->isp_ver == ISP_V21)
1150		- rkisp_write(dev, ISP_DEBAYER_CONTROL,
1151		- SW_DEBAYER_EN \|
1152		- SW_DEBAYER_FILTER_G_EN \|
1153		- SW_DEBAYER_FILTER_C_EN, false);
	1655	+ if (dev->isp_ver >= ISP_V20)
	1656	+ rkisp_unite_write(dev, ISP_DEBAYER_CONTROL,
	1657	+ SW_DEBAYER_EN \|
	1658	+ SW_DEBAYER_FILTER_G_EN \|
	1659	+ SW_DEBAYER_FILTER_C_EN, false);
1154	1660	else
1155	1661	rkisp_write(dev, CIF_ISP_DEMOSAIC,
1156		- CIF_ISP_DEMOSAIC_TH(0xc), false);
	1662	+ CIF_ISP_DEMOSAIC_TH(0xc), false);
1157	1663	}
1158	1664
1159	1665	if (sensor && sensor->mbus.type == V4L2_MBUS_BT656)
..	..	@@ -1171,7 +1677,7 @@
1171	1677	} else if (in_fmt->fmt_type == FMT_YUV) {
1172	1678	acq_mult = 2;
1173	1679	if (sensor &&
1174		- (sensor->mbus.type == V4L2_MBUS_CSI2 \|\|
	1680	+ (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
1175	1681	sensor->mbus.type == V4L2_MBUS_CCP2)) {
1176	1682	isp_ctrl = CIF_ISP_CTRL_ISP_MODE_ITU601;
1177	1683	} else {
..	..	@@ -1203,39 +1709,46 @@
1203	1709	signal \|= CIF_ISP_ACQ_PROP_HSYNC_LOW;
1204	1710	}
1205	1711
1206		- rkisp_write(dev, CIF_ISP_CTRL, isp_ctrl, false);
	1712	+ if (rkisp_read_reg_cache(dev, CIF_ISP_CTRL) & ISP32_MIR_ENABLE)
	1713	+ isp_ctrl \|= ISP32_MIR_ENABLE;
	1714	+
	1715	+ rkisp_unite_write(dev, CIF_ISP_CTRL, isp_ctrl, false);
1207	1716	acq_prop \|= signal \| in_fmt->yuv_seq \|
1208	1717	CIF_ISP_ACQ_PROP_BAYER_PAT(in_fmt->bayer_pat) \|
1209	1718	CIF_ISP_ACQ_PROP_FIELD_SEL_ALL;
1210		- rkisp_write(dev, CIF_ISP_ACQ_PROP, acq_prop, false);
1211		- rkisp_write(dev, CIF_ISP_ACQ_NR_FRAMES, 0, true);
	1719	+ rkisp_unite_write(dev, CIF_ISP_ACQ_PROP, acq_prop, false);
	1720	+ rkisp_unite_write(dev, CIF_ISP_ACQ_NR_FRAMES, 0, true);
1212	1721
	1722	+ if (is_unite)
	1723	+ width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
1213	1724	/* Acquisition Size */
1214		- rkisp_write(dev, CIF_ISP_ACQ_H_OFFS, acq_mult * in_crop->left, false);
1215		- rkisp_write(dev, CIF_ISP_ACQ_V_OFFS, in_crop->top, false);
1216		- rkisp_write(dev, CIF_ISP_ACQ_H_SIZE, acq_mult * in_crop->width, false);
	1725	+ rkisp_unite_write(dev, CIF_ISP_ACQ_H_OFFS, acq_mult * in_crop->left, false);
	1726	+ rkisp_unite_write(dev, CIF_ISP_ACQ_V_OFFS, in_crop->top, false);
	1727	+ rkisp_unite_write(dev, CIF_ISP_ACQ_H_SIZE, acq_mult * width, false);
1217	1728
1218	1729	/* ISP Out Area differ with ACQ is only FIFO, so don't crop in this */
1219		- rkisp_write(dev, CIF_ISP_OUT_H_OFFS, 0, true);
1220		- rkisp_write(dev, CIF_ISP_OUT_V_OFFS, 0, true);
1221		- rkisp_write(dev, CIF_ISP_OUT_H_SIZE, in_crop->width, false);
	1730	+ rkisp_unite_write(dev, CIF_ISP_OUT_H_OFFS, 0, true);
	1731	+ rkisp_unite_write(dev, CIF_ISP_OUT_V_OFFS, 0, true);
	1732	+ rkisp_unite_write(dev, CIF_ISP_OUT_H_SIZE, width, false);
1222	1733
1223	1734	if (dev->cap_dev.stream[RKISP_STREAM_SP].interlaced) {
1224		- rkisp_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height / 2, false);
1225		- rkisp_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height / 2, false);
	1735	+ rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height / 2, false);
	1736	+ rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height / 2, false);
1226	1737	} else {
1227		- rkisp_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height + extend_line, false);
1228		- rkisp_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height + extend_line, false);
	1738	+ rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height + extend_line, false);
	1739	+ rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height + extend_line, false);
1229	1740	}
1230	1741
1231	1742	/* interrupt mask */
1232		- irq_mask \|= CIF_ISP_FRAME \| CIF_ISP_V_START \| CIF_ISP_PIC_SIZE_ERROR \|
1233		- CIF_ISP_FRAME_IN;
1234		- if (dev->isp_ver == ISP_V20 \|\| dev->isp_ver == ISP_V21)
	1743	+ irq_mask \|= CIF_ISP_FRAME \| CIF_ISP_V_START \| CIF_ISP_PIC_SIZE_ERROR;
	1744	+ if (dev->isp_ver >= ISP_V20)
1235	1745	irq_mask \|= ISP2X_LSC_LUT_ERR;
1236		- rkisp_write(dev, CIF_ISP_IMSC, irq_mask, true);
	1746	+ if (dev->is_pre_on)
	1747	+ irq_mask \|= CIF_ISP_FRAME_IN;
	1748	+ rkisp_unite_write(dev, CIF_ISP_IMSC, irq_mask, true);
1237	1749
1238		- if ((dev->isp_ver == ISP_V20 \|\| dev->isp_ver == ISP_V21) &&
	1750	+ if ((dev->isp_ver == ISP_V20 \|\|
	1751	+ dev->isp_ver == ISP_V21) &&
1239	1752	IS_HDR_RDBK(dev->hdr.op_mode)) {
1240	1753	irq_mask = ISP2X_3A_RAWAE_BIG;
1241	1754	rkisp_write(dev, ISP_ISP3A_IMSC, irq_mask, true);
..	..	@@ -1252,6 +1765,8 @@
1252	1765	rkisp_update_regs(dev, CIF_ISP_ACQ_H_OFFS, CIF_ISP_ACQ_V_SIZE);
1253	1766	rkisp_update_regs(dev, CIF_ISP_OUT_H_SIZE, CIF_ISP_OUT_V_SIZE);
1254	1767	}
	1768	+
	1769	+ rkisp_config_cmsk(dev);
1255	1770	return 0;
1256	1771	}
1257	1772
..	..	@@ -1355,12 +1870,12 @@
1355	1870	/* Configure MUX */
1356	1871	static int rkisp_config_path(struct rkisp_device *dev)
1357	1872	{
1358		- int ret = 0;
1359	1873	struct rkisp_sensor_info *sensor = dev->active_sensor;
1360		- u32 dpcl = readl(dev->base_addr + CIF_VI_DPCL);
	1874	+ int ret = 0;
	1875	+ u32 dpcl = 0;
1361	1876
1362	1877	/* isp input interface selects */
1363		- if ((sensor && sensor->mbus.type == V4L2_MBUS_CSI2) \|\|
	1878	+ if ((sensor && sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) \|\|
1364	1879	dev->isp_inp & (INP_RAWRD0 \| INP_RAWRD1 \| INP_RAWRD2 \| INP_CIF)) {
1365	1880	/* mipi sensor->isp or isp read from ddr */
1366	1881	dpcl \|= CIF_VI_DPCL_IF_SEL_MIPI;
..	..	@@ -1382,8 +1897,10 @@
1382	1897	ret = -EINVAL;
1383	1898	}
1384	1899
1385		- writel(dpcl, dev->base_addr + CIF_VI_DPCL);
	1900	+ if (dev->isp_ver == ISP_V32)
	1901	+ dpcl \|= BIT(0);
1386	1902
	1903	+ rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true);
1387	1904	return ret;
1388	1905	}
1389	1906
..	..	@@ -1455,7 +1972,7 @@
1455	1972	int ret = 1000;
1456	1973
1457	1974	if (!rkisp_is_need_3a(dev) \|\| dev->isp_ver == ISP_V20 \|\|
1458		- !params_vdev->is_subs_evt)
	1975	+ !params_vdev->is_subs_evt \|\| dev->hw_dev->is_shutdown)
1459	1976	return;
1460	1977
1461	1978	v4l2_event_queue(vdev, &ev);
..	..	@@ -1472,6 +1989,7 @@
1472	1989	/* Mess register operations to stop isp */
1473	1990	static int rkisp_isp_stop(struct rkisp_device *dev)
1474	1991	{
	1992	+ struct rkisp_hw_dev *hw = dev->hw_dev;
1475	1993	void __iomem *base = dev->base_addr;
1476	1994	unsigned long old_rate, safe_rate;
1477	1995	u32 val;
..	..	@@ -1479,17 +1997,10 @@
1479	1997
1480	1998	v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1481	1999	"%s refcnt:%d\n", __func__,
1482		- atomic_read(&dev->hw_dev->refcnt));
	2000	+ atomic_read(&hw->refcnt));
1483	2001
1484		- if (atomic_read(&dev->hw_dev->refcnt) > 1)
	2002	+ if (atomic_read(&hw->refcnt) > 1)
1485	2003	goto end;
1486		-
1487		- if (dev->hw_dev->monitor.is_en) {
1488		- dev->hw_dev->monitor.is_en = 0;
1489		- dev->hw_dev->monitor.state = ISP_STOP;
1490		- if (!completion_done(&dev->hw_dev->monitor.cmpl))
1491		- complete(&dev->hw_dev->monitor.cmpl);
1492		- }
1493	2004	/*
1494	2005	* ISP(mi) stop in mi frame end -> Stop ISP(mipi) ->
1495	2006	* Stop ISP(isp) ->wait for ISP isp off
..	..	@@ -1502,7 +2013,7 @@
1502	2013	readl(base + CIF_ISP_CSI0_ERR1);
1503	2014	readl(base + CIF_ISP_CSI0_ERR2);
1504	2015	readl(base + CIF_ISP_CSI0_ERR3);
1505		- } else if (dev->isp_ver == ISP_V20 \|\| dev->isp_ver == ISP_V21) {
	2016	+ } else if (dev->isp_ver >= ISP_V20) {
1506	2017	writel(0, base + CSI2RX_MASK_PHY);
1507	2018	writel(0, base + CSI2RX_MASK_PACKET);
1508	2019	writel(0, base + CSI2RX_MASK_OVERFLOW);
..	..	@@ -1519,7 +2030,7 @@
1519	2030	writel(0, base + CIF_ISP_IMSC);
1520	2031	writel(~0, base + CIF_ISP_ICR);
1521	2032
1522		- if (dev->isp_ver == ISP_V20 \|\| dev->isp_ver == ISP_V21) {
	2033	+ if (dev->isp_ver >= ISP_V20) {
1523	2034	writel(0, base + ISP_ISP3A_IMSC);
1524	2035	writel(~0, base + ISP_ISP3A_ICR);
1525	2036	}
..	..	@@ -1535,7 +2046,7 @@
1535	2046	udelay(20);
1536	2047	}
1537	2048	/* stop lsc to avoid lsclut error */
1538		- if (dev->isp_ver == ISP_V20 \|\| dev->isp_ver == ISP_V21)
	2049	+ if (dev->isp_ver >= ISP_V20)
1539	2050	writel(0, base + ISP_LSC_CTRL);
1540	2051	/* stop ISP */
1541	2052	val = readl(base + CIF_ISP_CTRL);
..	..	@@ -1544,6 +2055,9 @@
1544	2055
1545	2056	val = readl(base + CIF_ISP_CTRL);
1546	2057	writel(val \| CIF_ISP_CTRL_ISP_CFG_UPD, base + CIF_ISP_CTRL);
	2058	+ if (hw->unite == ISP_UNITE_TWO)
	2059	+ rkisp_next_write(dev, CIF_ISP_CTRL,
	2060	+ val \| CIF_ISP_CTRL_ISP_CFG_UPD, true);
1547	2061
1548	2062	readx_poll_timeout_atomic(readl, base + CIF_ISP_RIS,
1549	2063	val, val & CIF_ISP_OFF, 20, 100);
..	..	@@ -1551,19 +2065,19 @@
1551	2065	"MI_CTRL:%x, ISP_CTRL:%x\n",
1552	2066	readl(base + CIF_MI_CTRL), readl(base + CIF_ISP_CTRL));
1553	2067
1554		- val = rkisp_read(dev, CTRL_VI_ISP_CLK_CTRL, true);
1555	2068	if (!in_interrupt()) {
1556	2069	/* normal case */
1557	2070	/* check the isp_clk before isp reset operation */
1558		- old_rate = clk_get_rate(dev->hw_dev->clks[0]);
1559		- safe_rate = dev->hw_dev->clk_rate_tbl[0].clk_rate * 1000000UL;
	2071	+ old_rate = clk_get_rate(hw->clks[0]);
	2072	+ safe_rate = hw->clk_rate_tbl[0].clk_rate * 1000000UL;
1560	2073	if (old_rate > safe_rate) {
1561		- rkisp_set_clk_rate(dev->hw_dev->clks[0], safe_rate);
	2074	+ rkisp_set_clk_rate(hw->clks[0], safe_rate);
	2075	+ if (hw->unite == ISP_UNITE_TWO)
	2076	+ rkisp_set_clk_rate(hw->clks[5], safe_rate);
1562	2077	udelay(100);
1563	2078	}
1564		- rkisp_soft_reset(dev->hw_dev, false);
	2079	+ rkisp_soft_reset(hw, false);
1565	2080	}
1566		- rkisp_write(dev, CTRL_VI_ISP_CLK_CTRL, val, true);
1567	2081
1568	2082	if (dev->isp_ver == ISP_V12 \|\| dev->isp_ver == ISP_V13) {
1569	2083	writel(0, base + CIF_ISP_CSI0_CSI2_RESETN);
..	..	@@ -1571,19 +2085,28 @@
1571	2085	writel(0, base + CIF_ISP_CSI0_MASK1);
1572	2086	writel(0, base + CIF_ISP_CSI0_MASK2);
1573	2087	writel(0, base + CIF_ISP_CSI0_MASK3);
1574		- } else if (dev->isp_ver == ISP_V20 \|\| dev->isp_ver == ISP_V21) {
	2088	+ } else if (dev->isp_ver >= ISP_V20) {
1575	2089	writel(0, base + CSI2RX_CSI2_RESETN);
	2090	+ if (hw->unite == ISP_UNITE_TWO)
	2091	+ rkisp_next_write(dev, CSI2RX_CSI2_RESETN, 0, true);
1576	2092	}
1577	2093
1578		- dev->hw_dev->is_idle = true;
1579		- dev->hw_dev->is_mi_update = false;
	2094	+ hw->is_dvfs = false;
	2095	+ hw->is_runing = false;
	2096	+ hw->is_idle = true;
	2097	+ hw->is_mi_update = false;
	2098	+ hw->pre_dev_id = -1;
1580	2099	end:
1581	2100	dev->irq_ends_mask = 0;
1582	2101	dev->hdr.op_mode = 0;
	2102	+ dev->sw_rd_cnt = 0;
	2103	+ dev->stats_vdev.rdbk_drop = false;
1583	2104	rkisp_set_state(&dev->isp_state, ISP_STOP);
1584	2105
1585		- if (dev->isp_ver == ISP_V20 \|\| dev->isp_ver == ISP_V21)
	2106	+ if (dev->isp_ver >= ISP_V20)
1586	2107	kfifo_reset(&dev->rdbk_kfifo);
	2108	+ if (dev->isp_ver == ISP_V30 \|\| dev->isp_ver == ISP_V32)
	2109	+ memset(&dev->cmsk_cfg, 0, sizeof(dev->cmsk_cfg));
1587	2110	if (dev->emd_vc <= CIF_ISP_ADD_DATA_VC_MAX) {
1588	2111	for (i = 0; i < RKISP_EMDDATA_FIFO_MAX; i++)
1589	2112	kfifo_free(&dev->emd_data_fifo[i].mipi_kfifo);
..	..	@@ -1601,15 +2124,37 @@
1601	2124	{
1602	2125	struct rkisp_sensor_info *sensor = dev->active_sensor;
1603	2126	void __iomem *base = dev->base_addr;
1604		- u32 val;
1605	2127	bool is_direct = true;
	2128	+ u32 val;
1606	2129
1607	2130	v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1608		- "%s refcnt:%d\n", __func__,
1609		- atomic_read(&dev->hw_dev->refcnt));
	2131	+ "%s refcnt:%d link_num:%d\n", __func__,
	2132	+ atomic_read(&dev->hw_dev->refcnt),
	2133	+ dev->hw_dev->dev_link_num);
	2134	+
	2135	+ dev->cap_dev.is_done_early = false;
	2136	+ if (dev->cap_dev.wait_line >= dev->isp_sdev.out_crop.height)
	2137	+ dev->cap_dev.wait_line = 0;
	2138	+ if (dev->cap_dev.wait_line) {
	2139	+ dev->cap_dev.is_done_early = true;
	2140	+ if (dev->isp_ver >= ISP_V32) {
	2141	+ val = dev->cap_dev.wait_line;
	2142	+ rkisp_write(dev, ISP32_ISP_IRQ_CFG0, val << 16, false);
	2143	+ rkisp_set_bits(dev, CIF_ISP_IMSC, 0, ISP3X_OUT_FRM_HALF, false);
	2144	+ } else {
	2145	+ /* using AF 15x15 block */
	2146	+ val = dev->isp_sdev.out_crop.height / 15;
	2147	+ val = dev->cap_dev.wait_line / val;
	2148	+ val = ISP3X_RAWAF_INELINE0(val) \| ISP3X_RAWAF_INTLINE0_EN;
	2149	+ rkisp_unite_write(dev, ISP3X_RAWAF_INT_LINE, val, false);
	2150	+ rkisp_unite_set_bits(dev, ISP_ISP3A_IMSC, 0, ISP2X_3A_RAWAF, false);
	2151	+ rkisp_unite_clear_bits(dev, CIF_ISP_IMSC, ISP2X_LSC_LUT_ERR, false);
	2152	+ dev->rawaf_irq_cnt = 0;
	2153	+ }
	2154	+ }
1610	2155
1611	2156	/* Activate MIPI */
1612		- if (sensor && sensor->mbus.type == V4L2_MBUS_CSI2) {
	2157	+ if (sensor && sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
1613	2158	if (dev->isp_ver == ISP_V12 \|\| dev->isp_ver == ISP_V13) {
1614	2159	/* clear interrupts state */
1615	2160	readl(base + CIF_ISP_CSI0_ERR1);
..	..	@@ -1624,19 +2169,19 @@
1624	2169	}
1625	2170	}
1626	2171	/* Activate ISP */
1627		- val = rkisp_read(dev, CIF_ISP_CTRL, false);
	2172	+ val = rkisp_read_reg_cache(dev, CIF_ISP_CTRL);
1628	2173	val \|= CIF_ISP_CTRL_ISP_CFG_UPD \| CIF_ISP_CTRL_ISP_ENABLE \|
1629	2174	CIF_ISP_CTRL_ISP_INFORM_ENABLE \| CIF_ISP_CTRL_ISP_CFG_UPD_PERMANENT;
1630	2175	if (dev->isp_ver == ISP_V20)
1631	2176	val \|= NOC_HURRY_PRIORITY(2) \| NOC_HURRY_W_MODE(2) \| NOC_HURRY_R_MODE(1);
1632	2177	if (atomic_read(&dev->hw_dev->refcnt) > 1)
1633	2178	is_direct = false;
1634		- rkisp_write(dev, CIF_ISP_CTRL, val, is_direct);
	2179	+ rkisp_unite_write(dev, CIF_ISP_CTRL, val, is_direct);
	2180	+ rkisp_clear_reg_cache_bits(dev, CIF_ISP_CTRL, CIF_ISP_CTRL_ISP_CFG_UPD);
1635	2181
1636	2182	dev->isp_err_cnt = 0;
1637	2183	dev->isp_isr_cnt = 0;
1638		- dev->isp_state = ISP_START \| ISP_FRAME_END;
1639		- dev->irq_ends_mask \|= ISP_FRAME_END \| ISP_FRAME_IN;
	2184	+ dev->irq_ends_mask \|= ISP_FRAME_END;
1640	2185	dev->irq_ends = 0;
1641	2186
1642	2187	/* XXX: Is the 1000us too long?
..	..	@@ -2076,7 +2621,7 @@
2076	2621	struct rkisp_isp_subdev *isp_sd = sd_to_isp_sd(sd);
2077	2622	struct rkisp_device *dev = sd_to_isp_dev(sd);
2078	2623	struct v4l2_rect *crop;
2079		- u32 max_w, max_h;
	2624	+ u32 max_w, max_h, max_size;
2080	2625
2081	2626	if (!sel)
2082	2627	goto err;
..	..	@@ -2097,19 +2642,42 @@
2097	2642	crop->left = 0;
2098	2643	crop->top = 0;
2099	2644	if (sel->pad == RKISP_ISP_PAD_SINK) {
2100		- if (dev->isp_ver == ISP_V12) {
	2645	+ switch (dev->isp_ver) {
	2646	+ case ISP_V12:
2101	2647	max_w = CIF_ISP_INPUT_W_MAX_V12;
2102	2648	max_h = CIF_ISP_INPUT_H_MAX_V12;
2103		- } else if (dev->isp_ver == ISP_V13) {
	2649	+ break;
	2650	+ case ISP_V13:
2104	2651	max_w = CIF_ISP_INPUT_W_MAX_V13;
2105	2652	max_h = CIF_ISP_INPUT_H_MAX_V13;
2106		- } else if (dev->isp_ver == ISP_V21) {
	2653	+ break;
	2654	+ case ISP_V21:
2107	2655	max_w = CIF_ISP_INPUT_W_MAX_V21;
2108	2656	max_h = CIF_ISP_INPUT_H_MAX_V21;
2109		- } else {
	2657	+ break;
	2658	+ case ISP_V30:
	2659	+ max_w = dev->hw_dev->unite ?
	2660	+ CIF_ISP_INPUT_W_MAX_V30_UNITE : CIF_ISP_INPUT_W_MAX_V30;
	2661	+ max_h = dev->hw_dev->unite ?
	2662	+ CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30;
	2663	+ break;
	2664	+ case ISP_V32:
	2665	+ max_w = dev->hw_dev->unite ?
	2666	+ CIF_ISP_INPUT_W_MAX_V32_UNITE : CIF_ISP_INPUT_W_MAX_V32;
	2667	+ max_h = dev->hw_dev->unite ?
	2668	+ CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32;
	2669	+ break;
	2670	+ case ISP_V32_L:
	2671	+ max_w = CIF_ISP_INPUT_W_MAX_V32_L;
	2672	+ max_h = CIF_ISP_INPUT_H_MAX_V32_L;
	2673	+ break;
	2674	+ default:
2110	2675	max_w = CIF_ISP_INPUT_W_MAX;
2111	2676	max_h = CIF_ISP_INPUT_H_MAX;
2112	2677	}
	2678	+ max_size = max_w * max_h;
	2679	+ max_h = max_size / isp_sd->in_frm.width;
	2680	+
2113	2681	crop->width = min_t(u32, isp_sd->in_frm.width, max_w);
2114	2682	crop->height = min_t(u32, isp_sd->in_frm.height, max_h);
2115	2683	}
..	..	@@ -2125,6 +2693,40 @@
2125	2693	return 0;
2126	2694	err:
2127	2695	return -EINVAL;
	2696	+}
	2697	+
	2698	+static void rkisp_check_stream_dcrop(struct rkisp_device *dev,
	2699	+ struct v4l2_rect *crop)
	2700	+{
	2701	+ struct rkisp_stream *stream;
	2702	+ struct v4l2_rect *dcrop;
	2703	+ u32 i;
	2704	+
	2705	+ for (i = 0; i < RKISP_MAX_STREAM; i++) {
	2706	+ if (i != RKISP_STREAM_MP && i != RKISP_STREAM_SP &&
	2707	+ i != RKISP_STREAM_FBC && i != RKISP_STREAM_BP)
	2708	+ continue;
	2709	+ stream = &dev->cap_dev.stream[i];
	2710	+ dcrop = &stream->dcrop;
	2711	+ v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
	2712	+ "%s id:%d %dx%d(%d %d) from %dx%d(%d %d)\n",
	2713	+ __func__, i,
	2714	+ dcrop->width, dcrop->height, dcrop->left, dcrop->top,
	2715	+ crop->width, crop->height, crop->left, crop->top);
	2716	+ /* make sure dcrop window in isp output window */
	2717	+ if (dcrop->width > crop->width) {
	2718	+ dcrop->width = crop->width;
	2719	+ dcrop->left = 0;
	2720	+ } else if ((dcrop->left + dcrop->width) > crop->width) {
	2721	+ dcrop->left = crop->width - dcrop->width;
	2722	+ }
	2723	+ if (dcrop->height > crop->height) {
	2724	+ dcrop->height = crop->height;
	2725	+ dcrop->top = 0;
	2726	+ } else if ((dcrop->top + dcrop->height) > crop->height) {
	2727	+ dcrop->top = crop->height - dcrop->height;
	2728	+ }
	2729	+ }
2128	2730	}
2129	2731
2130	2732	static int rkisp_isp_sd_set_selection(struct v4l2_subdev *sd,
..	..	@@ -2158,18 +2760,20 @@
2158	2760
2159	2761	if (sel->pad == RKISP_ISP_PAD_SINK) {
2160	2762	isp_sd->in_crop = *crop;
2161		- /* ISP20 don't have out crop */
2162		- if (dev->isp_ver == ISP_V20 \|\| dev->isp_ver == ISP_V21) {
	2763	+ /* don't have out crop */
	2764	+ if (dev->isp_ver >= ISP_V20) {
2163	2765	isp_sd->out_crop = *crop;
2164	2766	isp_sd->out_crop.left = 0;
2165	2767	isp_sd->out_crop.top = 0;
2166	2768	dev->br_dev.crop = isp_sd->out_crop;
2167	2769	}
2168	2770	} else {
2169		- if (dev->isp_ver == ISP_V20 \|\| dev->isp_ver == ISP_V21)
	2771	+ if (dev->isp_ver >= ISP_V20)
2170	2772	*crop = isp_sd->out_crop;
2171	2773	isp_sd->out_crop = *crop;
2172	2774	}
	2775	+
	2776	+ rkisp_check_stream_dcrop(dev, crop);
2173	2777
2174	2778	return 0;
2175	2779	err:
..	..	@@ -2225,53 +2829,301 @@
2225	2829	struct rkisp_stream *stream;
2226	2830	int i;
2227	2831
	2832	+ rkisp_stats_first_ddr_config(&dev->stats_vdev);
2228	2833	if (dev->hw_dev->is_mi_update)
2229	2834	return;
2230	2835
2231		- rkisp_stats_first_ddr_config(&dev->stats_vdev);
2232	2836	rkisp_config_dmatx_valid_buf(dev);
2233	2837
2234	2838	force_cfg_update(dev);
2235	2839
2236	2840	hdr_update_dmatx_buf(dev);
2237		- if (dev->br_dev.en && dev->isp_ver == ISP_V20) {
2238		- stream = &dev->cap_dev.stream[RKISP_STREAM_SP];
2239		- rkisp_update_spstream_buf(stream);
2240		- }
2241	2841	if (dev->hw_dev->is_single) {
2242	2842	for (i = 0; i < RKISP_MAX_STREAM; i++) {
2243	2843	stream = &dev->cap_dev.stream[i];
2244		- if (stream->streaming)
2245		- stream->ops->frame_end(stream);
	2844	+ if (stream->id == RKISP_STREAM_VIR \|\|
	2845	+ stream->id == RKISP_STREAM_LUMA)
	2846	+ continue;
	2847	+ if (stream->streaming && !stream->curr_buf)
	2848	+ stream->ops->frame_end(stream, FRAME_INIT);
2246	2849	}
2247	2850	}
	2851	+ rkisp_stats_next_ddr_config(&dev->stats_vdev);
2248	2852	}
2249	2853
2250	2854	static int rkisp_isp_sd_s_stream(struct v4l2_subdev *sd, int on)
2251	2855	{
2252	2856	struct rkisp_device *isp_dev = sd_to_isp_dev(sd);
	2857	+ struct rkisp_hw_dev *hw_dev = isp_dev->hw_dev;
	2858	+ int ret;
2253	2859
2254	2860	if (!on) {
2255		- rkisp_stop_3a_run(isp_dev);
2256		- wait_event_timeout(isp_dev->sync_onoff,
2257		- isp_dev->irq_ends_mask == (ISP_FRAME_END \| ISP_FRAME_IN) &&
2258		- (!IS_HDR_RDBK(isp_dev->rd_mode) \|\|
2259		- isp_dev->isp_state & ISP_STOP), msecs_to_jiffies(5));
	2861	+ if (IS_HDR_RDBK(isp_dev->rd_mode)) {
	2862	+ struct rkisp_stream *s;
	2863	+ int i;
	2864	+
	2865	+ for (i = RKISP_STREAM_RAWRD0; i <= RKISP_STREAM_RAWRD2; i++) {
	2866	+ s = &isp_dev->dmarx_dev.stream[i];
	2867	+ if (s->stopping)
	2868	+ wake_up(&s->done);
	2869	+ }
	2870	+ }
	2871	+ ret = wait_event_timeout(isp_dev->sync_onoff,
	2872	+ isp_dev->isp_state & ISP_STOP \|\|
	2873	+ !IS_HDR_RDBK(isp_dev->rd_mode),
	2874	+ msecs_to_jiffies(500));
	2875	+ if (!ret)
	2876	+ v4l2_warn(&isp_dev->v4l2_dev, "%s wait timeout, mode:%d state:0x%x\n",
	2877	+ __func__, isp_dev->rd_mode, isp_dev->isp_state);
2260	2878	rkisp_isp_stop(isp_dev);
2261		- atomic_dec(&isp_dev->hw_dev->refcnt);
	2879	+ atomic_dec(&hw_dev->refcnt);
2262	2880	rkisp_params_stream_stop(&isp_dev->params_vdev);
	2881	+ atomic_set(&isp_dev->isp_sdev.frm_sync_seq, 0);
	2882	+ rkisp_stop_3a_run(isp_dev);
2263	2883	return 0;
2264	2884	}
2265	2885
	2886	+ hw_dev->is_runing = true;
2266	2887	rkisp_start_3a_run(isp_dev);
2267	2888	memset(&isp_dev->isp_sdev.dbg, 0, sizeof(isp_dev->isp_sdev.dbg));
2268		- atomic_inc(&isp_dev->hw_dev->refcnt);
2269		- atomic_set(&isp_dev->isp_sdev.frm_sync_seq, 0);
2270		- rkisp_global_update_mi(isp_dev);
	2889	+ if (atomic_inc_return(&hw_dev->refcnt) > hw_dev->dev_link_num) {
	2890	+ dev_err(isp_dev->dev, "%s fail: input link before hw start\n", __func__);
	2891	+ atomic_dec(&hw_dev->refcnt);
	2892	+ return -EINVAL;
	2893	+ }
	2894	+
2271	2895	rkisp_config_cif(isp_dev);
2272	2896	rkisp_isp_start(isp_dev);
	2897	+ rkisp_global_update_mi(isp_dev);
	2898	+ isp_dev->isp_state = ISP_START \| ISP_FRAME_END;
2273	2899	rkisp_rdbk_trigger_event(isp_dev, T_CMD_QUEUE, NULL);
2274	2900	return 0;
	2901	+}
	2902	+
	2903	+static void rkisp_rx_buf_free(struct rkisp_device dev, struct rkisp_rx_buf dbufs)
	2904	+{
	2905	+ const struct vb2_mem_ops *g_ops = dev->hw_dev->mem_ops;
	2906	+ struct rkisp_rx_buf_pool *pool;
	2907	+ int i = 0;
	2908	+
	2909	+ if (!dbufs)
	2910	+ return;
	2911	+
	2912	+ for (i = 0; i < RKISP_RX_BUF_POOL_MAX; i++) {
	2913	+ pool = &dev->pv_pool[i];
	2914	+ if (dbufs == pool->dbufs) {
	2915	+ if (pool->mem_priv) {
	2916	+ g_ops->unmap_dmabuf(pool->mem_priv);
	2917	+ g_ops->detach_dmabuf(pool->mem_priv);
	2918	+ dma_buf_put(pool->dbufs->dbuf);
	2919	+ pool->mem_priv = NULL;
	2920	+ }
	2921	+ pool->dbufs = NULL;
	2922	+ break;
	2923	+ }
	2924	+ }
	2925	+}
	2926	+
	2927	+static void rkisp_rx_qbuf_online(struct rkisp_stream *stream,
	2928	+ struct rkisp_rx_buf_pool *pool)
	2929	+{
	2930	+ struct rkisp_device *dev = stream->ispdev;
	2931	+ u32 val = pool->buf.buff_addr[RKISP_PLANE_Y];
	2932	+
	2933	+ rkisp_write(dev, stream->config->mi.y_base_ad_init, val, false);
	2934	+ if (dev->hw_dev->unite == ISP_UNITE_TWO) {
	2935	+ u32 offs = stream->out_fmt.width / 2 - RKMOUDLE_UNITE_EXTEND_PIXEL;
	2936	+
	2937	+ if (stream->memory)
	2938	+ offs *= DIV_ROUND_UP(stream->out_isp_fmt.bpp[0], 8);
	2939	+ else
	2940	+ offs = offs * stream->out_isp_fmt.bpp[0] / 8;
	2941	+ val += offs;
	2942	+ rkisp_next_write(dev, stream->config->mi.y_base_ad_init, val, false);
	2943	+ }
	2944	+}
	2945	+
	2946	+static void rkisp_rx_qbuf_rdbk(struct rkisp_stream *stream,
	2947	+ struct rkisp_rx_buf_pool *pool)
	2948	+{
	2949	+ struct rkisp_device *dev = stream->ispdev;
	2950	+ unsigned long lock_flags = 0;
	2951	+ struct rkisp_buffer *ispbuf = &pool->buf;
	2952	+ struct isp2x_csi_trigger trigger = {
	2953	+ .frame_timestamp = ispbuf->vb.vb2_buf.timestamp,
	2954	+ .sof_timestamp = ispbuf->vb.vb2_buf.timestamp,
	2955	+ .frame_id = ispbuf->vb.sequence,
	2956	+ .mode = 0,
	2957	+ .times = 0,
	2958	+ };
	2959	+ spin_lock_irqsave(&stream->vbq_lock, lock_flags);
	2960	+ if (list_empty(&stream->buf_queue) && !stream->curr_buf) {
	2961	+ stream->curr_buf = ispbuf;
	2962	+ stream->ops->update_mi(stream);
	2963	+ } else {
	2964	+ list_add_tail(&ispbuf->queue, &stream->buf_queue);
	2965	+ }
	2966	+ spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
	2967	+ if (stream->id == RKISP_STREAM_RAWRD2)
	2968	+ rkisp_rdbk_trigger_event(dev, T_CMD_QUEUE, &trigger);
	2969	+}
	2970	+
	2971	+static int rkisp_rx_qbuf(struct rkisp_device *dev,
	2972	+ struct rkisp_rx_buf *dbufs)
	2973	+{
	2974	+ struct rkisp_stream *stream;
	2975	+ struct rkisp_rx_buf_pool *pool;
	2976	+ int i;
	2977	+
	2978	+ for (i = 0; i < RKISP_RX_BUF_POOL_MAX; i++) {
	2979	+ pool = &dev->pv_pool[i];
	2980	+ if (dbufs == pool->dbufs)
	2981	+ break;
	2982	+ }
	2983	+
	2984	+ if (pool->dbufs == NULL \|\| pool->dbufs != dbufs)
	2985	+ return -EINVAL;
	2986	+ switch (dbufs->type) {
	2987	+ case BUF_SHORT:
	2988	+ stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2];
	2989	+ break;
	2990	+ case BUF_MIDDLE:
	2991	+ stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD0];
	2992	+ break;
	2993	+ case BUF_LONG:
	2994	+ default:
	2995	+ stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD1];
	2996	+ }
	2997	+
	2998	+ v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
	2999	+ "%s rd_mode:%d seq:%d dma:0x%x\n",
	3000	+ __func__, dev->rd_mode, dbufs->sequence,
	3001	+ pool->buf.buff_addr[RKISP_PLANE_Y]);
	3002	+
	3003	+ if (!IS_HDR_RDBK(dev->rd_mode)) {
	3004	+ rkisp_rx_qbuf_online(stream, pool);
	3005	+ } else {
	3006	+ pool->buf.vb.vb2_buf.timestamp = dbufs->timestamp;
	3007	+ pool->buf.vb.sequence = dbufs->sequence;
	3008	+ rkisp_rx_qbuf_rdbk(stream, pool);
	3009	+ }
	3010	+ return 0;
	3011	+}
	3012	+
	3013	+void rkisp_rx_buf_pool_free(struct rkisp_device *dev)
	3014	+{
	3015	+ const struct vb2_mem_ops *g_ops = dev->hw_dev->mem_ops;
	3016	+ struct rkisp_rx_buf_pool *pool;
	3017	+ int i;
	3018	+
	3019	+ for (i = 0; i < RKISP_RX_BUF_POOL_MAX; i++) {
	3020	+ pool = &dev->pv_pool[i];
	3021	+ if (!pool->dbufs)
	3022	+ break;
	3023	+ if (pool->mem_priv) {
	3024	+ g_ops->unmap_dmabuf(pool->mem_priv);
	3025	+ g_ops->detach_dmabuf(pool->mem_priv);
	3026	+ dma_buf_put(pool->dbufs->dbuf);
	3027	+ pool->mem_priv = NULL;
	3028	+ }
	3029	+ pool->dbufs = NULL;
	3030	+ }
	3031	+}
	3032	+
	3033	+static int rkisp_rx_buf_pool_init(struct rkisp_device *dev,
	3034	+ struct rkisp_rx_buf *dbufs)
	3035	+{
	3036	+ const struct vb2_mem_ops *g_ops = dev->hw_dev->mem_ops;
	3037	+ struct rkisp_stream *stream;
	3038	+ struct rkisp_rx_buf_pool *pool;
	3039	+ struct sg_table *sg_tbl;
	3040	+ dma_addr_t dma;
	3041	+ int i, ret;
	3042	+ void mem, vaddr = NULL;
	3043	+
	3044	+ for (i = 0; i < RKISP_RX_BUF_POOL_MAX; i++) {
	3045	+ pool = &dev->pv_pool[i];
	3046	+ if (!pool->dbufs)
	3047	+ break;
	3048	+ }
	3049	+
	3050	+ pool->dbufs = dbufs;
	3051	+ v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
	3052	+ "%s type:0x%x first:%d dbufs[%d]:%p", __func__,
	3053	+ dbufs->type, dbufs->is_first, i, dbufs);
	3054	+
	3055	+ if (dbufs->is_resmem) {
	3056	+ dma = dbufs->dma;
	3057	+ goto end;
	3058	+ }
	3059	+ mem = g_ops->attach_dmabuf(dev->hw_dev->dev, dbufs->dbuf,
	3060	+ dbufs->dbuf->size, DMA_BIDIRECTIONAL);
	3061	+ if (IS_ERR(mem)) {
	3062	+ ret = PTR_ERR(mem);
	3063	+ goto err;
	3064	+ }
	3065	+ pool->mem_priv = mem;
	3066	+ ret = g_ops->map_dmabuf(mem);
	3067	+ if (ret)
	3068	+ goto err;
	3069	+ if (dev->hw_dev->is_dma_sg_ops) {
	3070	+ sg_tbl = (struct sg_table *)g_ops->cookie(mem);
	3071	+ dma = sg_dma_address(sg_tbl->sgl);
	3072	+ } else {
	3073	+ dma = ((dma_addr_t )g_ops->cookie(mem));
	3074	+ }
	3075	+ get_dma_buf(dbufs->dbuf);
	3076	+ vaddr = g_ops->vaddr(mem);
	3077	+end:
	3078	+ dbufs->is_init = true;
	3079	+ pool->buf.other = dbufs;
	3080	+ pool->buf.buff_addr[RKISP_PLANE_Y] = dma;
	3081	+ pool->buf.vaddr[RKISP_PLANE_Y] = vaddr;
	3082	+
	3083	+ switch (dbufs->type) {
	3084	+ case BUF_SHORT:
	3085	+ stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2];
	3086	+ break;
	3087	+ case BUF_MIDDLE:
	3088	+ stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD0];
	3089	+ break;
	3090	+ case BUF_LONG:
	3091	+ default:
	3092	+ stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD1];
	3093	+ }
	3094	+ if (dbufs->is_first) {
	3095	+ stream->memory = 0;
	3096	+ if (dbufs->is_uncompact)
	3097	+ stream->memory = SW_CSI_RAW_WR_SIMG_MODE;
	3098	+ rkisp_dmarx_set_fmt(stream, stream->out_fmt);
	3099	+ stream->ops->config_mi(stream);
	3100	+ dbufs->is_first = false;
	3101	+ }
	3102	+ v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
	3103	+ "%s dma:0x%x vaddr:%p", __func__, (u32)dma, vaddr);
	3104	+ return 0;
	3105	+err:
	3106	+ rkisp_rx_buf_pool_free(dev);
	3107	+ return ret;
	3108	+}
	3109	+
	3110	+static int rkisp_sd_s_rx_buffer(struct v4l2_subdev *sd,
	3111	+ void buf, unsigned int size)
	3112	+{
	3113	+ struct rkisp_device *dev = sd_to_isp_dev(sd);
	3114	+ struct rkisp_rx_buf *dbufs;
	3115	+ int ret = 0;
	3116	+
	3117	+ if (!buf)
	3118	+ return -EINVAL;
	3119	+
	3120	+ dbufs = buf;
	3121	+ if (!dbufs->is_init)
	3122	+ ret = rkisp_rx_buf_pool_init(dev, dbufs);
	3123	+ if (!ret)
	3124	+ ret = rkisp_rx_qbuf(dev, dbufs);
	3125	+
	3126	+ return ret;
2275	3127	}
2276	3128
2277	3129	static int rkisp_isp_sd_s_power(struct v4l2_subdev *sd, int on)
..	..	@@ -2279,14 +3131,11 @@
2279	3131	struct rkisp_device *isp_dev = sd_to_isp_dev(sd);
2280	3132	int ret;
2281	3133
2282		- if (isp_dev->hw_dev->is_thunderboot)
2283		- return 0;
2284		-
2285	3134	v4l2_dbg(1, rkisp_debug, &isp_dev->v4l2_dev,
2286	3135	"%s on:%d\n", __func__, on);
2287	3136
2288	3137	if (on) {
2289		- if (isp_dev->isp_ver == ISP_V20 \|\| isp_dev->isp_ver == ISP_V21)
	3138	+ if (isp_dev->isp_ver >= ISP_V20)
2290	3139	kfifo_reset(&isp_dev->rdbk_kfifo);
2291	3140	ret = pm_runtime_get_sync(isp_dev->dev);
2292	3141	} else {
..	..	@@ -2316,6 +3165,15 @@
2316	3165	dev = sd_to_isp_dev(sd);
2317	3166	if (!dev)
2318	3167	return -ENODEV;
	3168	+
	3169	+ if (dev->hw_dev->is_runing &&
	3170	+ (!dev->isp_inp \|\|
	3171	+ !(dev->isp_inp & ~rawrd) \|\|
	3172	+ !strcmp(remote->entity->name, CSI_DEV_NAME) \|\|
	3173	+ strstr(remote->entity->name, "rkcif"))) {
	3174	+ v4l2_err(sd, "no support link for isp hw working\n");
	3175	+ return -EINVAL;
	3176	+ }
2319	3177
2320	3178	if (!strcmp(remote->entity->name, DMA_VDEV_NAME)) {
2321	3179	stream = &dev->dmarx_dev.stream[RKISP_STREAM_DMARX];
..	..	@@ -2365,6 +3223,18 @@
2365	3223	} else {
2366	3224	dev->isp_inp &= ~INP_RAWRD2;
2367	3225	}
	3226	+ } else if (!strcmp(remote->entity->name, FBC_VDEV_NAME)) {
	3227	+ stream = &dev->cap_dev.stream[RKISP_STREAM_FBC];
	3228	+ } else if (!strcmp(remote->entity->name, BP_VDEV_NAME)) {
	3229	+ stream = &dev->cap_dev.stream[RKISP_STREAM_BP];
	3230	+ } else if (!strcmp(remote->entity->name, MPDS_VDEV_NAME)) {
	3231	+ stream = &dev->cap_dev.stream[RKISP_STREAM_MPDS];
	3232	+ } else if (!strcmp(remote->entity->name, BPDS_VDEV_NAME)) {
	3233	+ stream = &dev->cap_dev.stream[RKISP_STREAM_BPDS];
	3234	+ } else if (!strcmp(remote->entity->name, LUMA_VDEV_NAME)) {
	3235	+ stream = &dev->cap_dev.stream[RKISP_STREAM_LUMA];
	3236	+ } else if (!strcmp(remote->entity->name, VIR_VDEV_NAME)) {
	3237	+ stream = &dev->cap_dev.stream[RKISP_STREAM_VIR];
2368	3238	} else if (!strcmp(remote->entity->name, SP_VDEV_NAME)) {
2369	3239	stream = &dev->cap_dev.stream[RKISP_STREAM_SP];
2370	3240	} else if (!strcmp(remote->entity->name, MP_VDEV_NAME)) {
..	..	@@ -2409,11 +3279,31 @@
2409	3279
2410	3280	if (stream)
2411	3281	stream->linked = flags & MEDIA_LNK_FL_ENABLED;
2412		- if (dev->isp_inp & rawrd)
	3282	+ if (dev->isp_inp & rawrd) {
2413	3283	dev->dmarx_dev.trigger = T_MANUAL;
2414		- else
	3284	+ dev->is_rdbk_auto = false;
	3285	+ } else {
2415	3286	dev->dmarx_dev.trigger = T_AUTO;
	3287	+ }
	3288	+ if (dev->isp_inp & INP_CIF) {
	3289	+ struct v4l2_subdev *remote = get_remote_sensor(sd);
	3290	+ struct rkisp_vicap_mode mode;
2416	3291
	3292	+ memset(&mode, 0, sizeof(mode));
	3293	+ mode.name = dev->name;
	3294	+ mode.rdbk_mode = !!(dev->isp_inp & rawrd);
	3295	+ /* read back mode only */
	3296	+ if (dev->isp_ver < ISP_V30 \|\| !dev->hw_dev->is_single)
	3297	+ mode.rdbk_mode = RKISP_VICAP_RDBK_AIQ;
	3298	+ v4l2_subdev_call(remote, core, ioctl,
	3299	+ RKISP_VICAP_CMD_MODE, &mode);
	3300	+ dev->vicap_in = mode.input;
	3301	+ }
	3302	+
	3303	+ if (!dev->isp_inp)
	3304	+ dev->is_hw_link = false;
	3305	+ else
	3306	+ dev->is_hw_link = true;
2417	3307	v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
2418	3308	"isp input:0x%x\n", dev->isp_inp);
2419	3309	return 0;
..	..	@@ -2461,7 +3351,6 @@
2461	3351	atomic_inc_return(&isp->frm_sync_seq) - 1,
2462	3352	};
2463	3353
2464		- event.timestamp = ns_to_timespec(ktime_get_ns());
2465	3354	v4l2_event_queue(isp->sd.devnode, &event);
2466	3355	}
2467	3356
..	..	@@ -2478,24 +3367,148 @@
2478	3367	return v4l2_event_subscribe(fh, sub, ISP_V4L2_EVENT_ELEMS, NULL);
2479	3368	}
2480	3369
	3370	+static int rkisp_get_info(struct rkisp_device dev, struct rkisp_isp_info info)
	3371	+{
	3372	+ struct v4l2_rect *in_crop = &dev->isp_sdev.in_crop;
	3373	+ u32 rd_mode, mode = 0, bit = 0;
	3374	+ int ret;
	3375	+
	3376	+ if (!(dev->isp_state & ISP_START)) {
	3377	+ struct rkmodule_hdr_cfg cfg;
	3378	+
	3379	+ ret = rkisp_csi_get_hdr_cfg(dev, &cfg);
	3380	+ if (ret)
	3381	+ return ret;
	3382	+ rd_mode = cfg.hdr_mode;
	3383	+ if (rd_mode == HDR_COMPR)
	3384	+ bit = cfg.compr.bit > 20 ? 20 : cfg.compr.bit;
	3385	+ } else {
	3386	+ rd_mode = dev->rd_mode;
	3387	+ bit = dev->hdr.compr_bit;
	3388	+ }
	3389	+
	3390	+ switch (rd_mode) {
	3391	+ case HDR_RDBK_FRAME2:
	3392	+ case HDR_FRAMEX2_DDR:
	3393	+ case HDR_LINEX2_DDR:
	3394	+ mode = RKISP_ISP_HDR2;
	3395	+ break;
	3396	+ case HDR_RDBK_FRAME3:
	3397	+ case HDR_FRAMEX3_DDR:
	3398	+ case HDR_LINEX3_DDR:
	3399	+ mode = RKISP_ISP_HDR3;
	3400	+ break;
	3401	+ default:
	3402	+ mode = RKISP_ISP_NORMAL;
	3403	+ }
	3404	+ if (bit)
	3405	+ mode = RKISP_ISP_COMPR;
	3406	+ info->compr_bit = bit;
	3407	+
	3408	+ if (dev->is_bigmode)
	3409	+ mode \|= RKISP_ISP_BIGMODE;
	3410	+ info->mode = mode;
	3411	+ if (dev->hw_dev->unite)
	3412	+ info->act_width = in_crop->width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
	3413	+ else
	3414	+ info->act_width = in_crop->width;
	3415	+ info->act_height = in_crop->height;
	3416	+ return 0;
	3417	+}
	3418	+
	3419	+static int rkisp_set_work_mode_by_vicap(struct rkisp_device *isp_dev,
	3420	+ struct rkisp_vicap_mode *vicap_mode)
	3421	+{
	3422	+ struct rkisp_hw_dev *hw = isp_dev->hw_dev;
	3423	+ int rd_mode = isp_dev->rd_mode;
	3424	+
	3425	+ isp_dev->is_suspend_one_frame = false;
	3426	+ if (vicap_mode->rdbk_mode == RKISP_VICAP_ONLINE) {
	3427	+ if (!hw->is_single)
	3428	+ return -EINVAL;
	3429	+ /* switch to online mode for single sensor */
	3430	+ switch (rd_mode) {
	3431	+ case HDR_RDBK_FRAME3:
	3432	+ isp_dev->rd_mode = HDR_LINEX3_DDR;
	3433	+ break;
	3434	+ case HDR_RDBK_FRAME2:
	3435	+ isp_dev->rd_mode = HDR_LINEX2_DDR;
	3436	+ break;
	3437	+ default:
	3438	+ isp_dev->rd_mode = HDR_NORMAL;
	3439	+ }
	3440	+ } else if (vicap_mode->rdbk_mode == RKISP_VICAP_RDBK_AUTO \|\|
	3441	+ vicap_mode->rdbk_mode == RKISP_VICAP_RDBK_AUTO_ONE_FRAME) {
	3442	+ /* switch to readback mode */
	3443	+ switch (rd_mode) {
	3444	+ case HDR_LINEX3_DDR:
	3445	+ isp_dev->rd_mode = HDR_RDBK_FRAME3;
	3446	+ break;
	3447	+ case HDR_LINEX2_DDR:
	3448	+ isp_dev->rd_mode = HDR_RDBK_FRAME2;
	3449	+ break;
	3450	+ default:
	3451	+ isp_dev->rd_mode = HDR_RDBK_FRAME1;
	3452	+ }
	3453	+ if (vicap_mode->rdbk_mode == RKISP_VICAP_RDBK_AUTO_ONE_FRAME)
	3454	+ isp_dev->is_suspend_one_frame = true;
	3455	+ } else {
	3456	+ return -EINVAL;
	3457	+ }
	3458	+ isp_dev->hdr.op_mode = isp_dev->rd_mode;
	3459	+ if (rd_mode != isp_dev->rd_mode && hw->cur_dev_id == isp_dev->dev_id) {
	3460	+ rkisp_unite_write(isp_dev, CSI2RX_CTRL0,
	3461	+ SW_IBUF_OP_MODE(isp_dev->rd_mode), true);
	3462	+ if (IS_HDR_RDBK(isp_dev->rd_mode))
	3463	+ rkisp_unite_set_bits(isp_dev, CTRL_SWS_CFG, 0,
	3464	+ SW_MPIP_DROP_FRM_DIS, true);
	3465	+ else
	3466	+ rkisp_unite_clear_bits(isp_dev, CTRL_SWS_CFG,
	3467	+ SW_MPIP_DROP_FRM_DIS, true);
	3468	+ }
	3469	+ return 0;
	3470	+}
	3471	+
2481	3472	static long rkisp_ioctl(struct v4l2_subdev sd, unsigned int cmd, void arg)
2482	3473	{
2483	3474	struct rkisp_device *isp_dev = sd_to_isp_dev(sd);
2484	3475	struct rkisp_thunderboot_resmem *resmem;
	3476	+ struct rkisp32_thunderboot_resmem_head *tb_head_v32;
2485	3477	struct rkisp_thunderboot_resmem_head *head;
2486	3478	struct rkisp_thunderboot_shmem *shmem;
2487	3479	struct isp2x_buf_idxfd *idxfd;
	3480	+ struct rkisp_rx_buf *dbufs;
2488	3481	void *resmem_va;
2489	3482	long ret = 0;
2490	3483
2491		- if (!arg && cmd != RKISP_CMD_FREE_SHARED_BUF)
	3484	+ if (!arg &&
	3485	+ (cmd != RKISP_CMD_FREE_SHARED_BUF &&
	3486	+ cmd != RKISP_CMD_MULTI_DEV_FORCE_ENUM))
2492	3487	return -EINVAL;
2493	3488
2494	3489	switch (cmd) {
2495	3490	case RKISP_CMD_TRIGGER_READ_BACK:
2496	3491	rkisp_rdbk_trigger_event(isp_dev, T_CMD_QUEUE, arg);
2497	3492	break;
	3493	+ case RKISP_CMD_GET_ISP_INFO:
	3494	+ rkisp_get_info(isp_dev, arg);
	3495	+ break;
	3496	+ case RKISP_CMD_GET_TB_HEAD_V32:
	3497	+ if (isp_dev->tb_head.complete != RKISP_TB_OK) {
	3498	+ ret = -EINVAL;
	3499	+ break;
	3500	+ }
	3501	+ tb_head_v32 = arg;
	3502	+ memcpy(tb_head_v32, &isp_dev->tb_head,
	3503	+ sizeof(struct rkisp_thunderboot_resmem_head));
	3504	+ memcpy(&tb_head_v32->cfg, isp_dev->params_vdev.isp32_params,
	3505	+ sizeof(struct isp32_isp_params_cfg));
	3506	+ break;
2498	3507	case RKISP_CMD_GET_SHARED_BUF:
	3508	+ if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
	3509	+ ret = -ENOIOCTLCMD;
	3510	+ break;
	3511	+ }
2499	3512	resmem = (struct rkisp_thunderboot_resmem *)arg;
2500	3513	resmem->resmem_padr = isp_dev->resmem_pa;
2501	3514	resmem->resmem_size = isp_dev->resmem_size;
..	..	@@ -2525,6 +3538,10 @@
2525	3538	}
2526	3539	break;
2527	3540	case RKISP_CMD_FREE_SHARED_BUF:
	3541	+ if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
	3542	+ ret = -ENOIOCTLCMD;
	3543	+ break;
	3544	+ }
2528	3545	if (isp_dev->resmem_pa && isp_dev->resmem_size) {
2529	3546	dma_unmap_single(isp_dev->dev, isp_dev->resmem_pa,
2530	3547	sizeof(struct rkisp_thunderboot_resmem_head),
..	..	@@ -2543,15 +3560,48 @@
2543	3560	break;
2544	3561	case RKISP_CMD_SET_LDCHBUF_SIZE:
2545	3562	case RKISP_CMD_SET_MESHBUF_SIZE:
2546		- rkisp_params_set_meshbuf_size(&isp_dev->params_vdev, arg);
	3563	+ ret = rkisp_params_set_meshbuf_size(&isp_dev->params_vdev, arg);
2547	3564	break;
2548	3565	case RKISP_CMD_GET_SHM_BUFFD:
	3566	+ if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
	3567	+ ret = -ENOIOCTLCMD;
	3568	+ break;
	3569	+ }
2549	3570	shmem = (struct rkisp_thunderboot_shmem *)arg;
2550	3571	ret = rkisp_tb_shm_ioctl(shmem);
2551	3572	break;
2552	3573	case RKISP_CMD_GET_FBCBUF_FD:
2553	3574	idxfd = (struct isp2x_buf_idxfd *)arg;
2554	3575	ret = rkisp_bridge_get_fbcbuf_fd(isp_dev, idxfd);
	3576	+ break;
	3577	+ case RKISP_CMD_INFO2DDR:
	3578	+ ret = rkisp_params_info2ddr_cfg(&isp_dev->params_vdev, arg);
	3579	+ break;
	3580	+ case RKISP_CMD_MESHBUF_FREE:
	3581	+ rkisp_params_meshbuf_free(&isp_dev->params_vdev, (u64 )arg);
	3582	+ break;
	3583	+ case RKISP_VICAP_CMD_RX_BUFFER_FREE:
	3584	+ dbufs = (struct rkisp_rx_buf *)arg;
	3585	+ rkisp_rx_buf_free(isp_dev, dbufs);
	3586	+ break;
	3587	+ case RKISP_CMD_MULTI_DEV_FORCE_ENUM:
	3588	+ if (isp_dev->hw_dev->is_runing) {
	3589	+ ret = -EINVAL;
	3590	+ } else {
	3591	+ isp_dev->hw_dev->is_single = true;
	3592	+ isp_dev->hw_dev->is_multi_overflow = false;
	3593	+ rkisp_hw_enum_isp_size(isp_dev->hw_dev);
	3594	+ }
	3595	+ break;
	3596	+ case RKISP_VICAP_CMD_SET_STREAM:
	3597	+ ret = rkisp_reset_handle(isp_dev);
	3598	+ if (!ret) {
	3599	+ if (isp_dev->hw_dev->monitor.state & ISP_CIF_RESET)
	3600	+ isp_dev->hw_dev->monitor.state &= ~ISP_CIF_RESET;
	3601	+ }
	3602	+ break;
	3603	+ case RKISP_VICAP_CMD_MODE:
	3604	+ ret = rkisp_set_work_mode_by_vicap(isp_dev, arg);
2555	3605	break;
2556	3606	default:
2557	3607	ret = -ENOIOCTLCMD;
..	..	@@ -2573,7 +3623,9 @@
2573	3623	struct rkisp_meshbuf_size meshsize;
2574	3624	struct rkisp_thunderboot_shmem shmem;
2575	3625	struct isp2x_buf_idxfd idxfd;
	3626	+ struct rkisp_info2ddr info2ddr;
2576	3627	long ret = 0;
	3628	+ u64 module_id;
2577	3629
2578	3630	if (!up && cmd != RKISP_CMD_FREE_SHARED_BUF)
2579	3631	return -EINVAL;
..	..	@@ -2585,11 +3637,19 @@
2585	3637	ret = rkisp_ioctl(sd, cmd, &trigger);
2586	3638	break;
2587	3639	case RKISP_CMD_GET_SHARED_BUF:
	3640	+ if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
	3641	+ ret = -ENOIOCTLCMD;
	3642	+ break;
	3643	+ }
2588	3644	ret = rkisp_ioctl(sd, cmd, &resmem);
2589	3645	if (!ret && copy_to_user(up, &resmem, sizeof(resmem)))
2590	3646	ret = -EFAULT;
2591	3647	break;
2592	3648	case RKISP_CMD_FREE_SHARED_BUF:
	3649	+ if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
	3650	+ ret = -ENOIOCTLCMD;
	3651	+ break;
	3652	+ }
2593	3653	ret = rkisp_ioctl(sd, cmd, NULL);
2594	3654	break;
2595	3655	case RKISP_CMD_GET_LDCHBUF_INFO:
..	..	@@ -2603,7 +3663,7 @@
2603	3663	ret = rkisp_ioctl(sd, cmd, &ldchsize);
2604	3664	break;
2605	3665	case RKISP_CMD_GET_MESHBUF_INFO:
2606		- if (copy_from_user(&meshsize, up, sizeof(meshsize)))
	3666	+ if (copy_from_user(&meshbuf, up, sizeof(meshbuf)))
2607	3667	return -EFAULT;
2608	3668	ret = rkisp_ioctl(sd, cmd, &meshbuf);
2609	3669	if (!ret && copy_to_user(up, &meshbuf, sizeof(meshbuf)))
..	..	@@ -2615,6 +3675,10 @@
2615	3675	ret = rkisp_ioctl(sd, cmd, &meshsize);
2616	3676	break;
2617	3677	case RKISP_CMD_GET_SHM_BUFFD:
	3678	+ if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
	3679	+ ret = -ENOIOCTLCMD;
	3680	+ break;
	3681	+ }
2618	3682	if (copy_from_user(&shmem, up, sizeof(shmem)))
2619	3683	return -EFAULT;
2620	3684	ret = rkisp_ioctl(sd, cmd, &shmem);
..	..	@@ -2625,6 +3689,24 @@
2625	3689	ret = rkisp_ioctl(sd, cmd, &idxfd);
2626	3690	if (!ret && copy_to_user(up, &idxfd, sizeof(idxfd)))
2627	3691	ret = -EFAULT;
	3692	+ break;
	3693	+ case RKISP_CMD_INFO2DDR:
	3694	+ if (copy_from_user(&info2ddr, up, sizeof(info2ddr)))
	3695	+ return -EFAULT;
	3696	+ ret = rkisp_ioctl(sd, cmd, &info2ddr);
	3697	+ if (!ret && copy_to_user(up, &info2ddr, sizeof(info2ddr)))
	3698	+ ret = -EFAULT;
	3699	+ break;
	3700	+ case RKISP_CMD_MESHBUF_FREE:
	3701	+ if (copy_from_user(&module_id, up, sizeof(module_id)))
	3702	+ return -EFAULT;
	3703	+ ret = rkisp_ioctl(sd, cmd, &module_id);
	3704	+ break;
	3705	+ case RKISP_CMD_MULTI_DEV_FORCE_ENUM:
	3706	+ ret = rkisp_ioctl(sd, cmd, NULL);
	3707	+ break;
	3708	+ case RKISP_VICAP_CMD_SET_STREAM:
	3709	+ ret = rkisp_ioctl(sd, cmd, NULL);
2628	3710	break;
2629	3711	default:
2630	3712	ret = -ENOIOCTLCMD;
..	..	@@ -2652,6 +3734,7 @@
2652	3734
2653	3735	static const struct v4l2_subdev_video_ops rkisp_isp_sd_video_ops = {
2654	3736	.s_stream = rkisp_isp_sd_s_stream,
	3737	+ .s_rx_buffer = rkisp_sd_s_rx_buffer,
2655	3738	};
2656	3739
2657	3740	static const struct v4l2_subdev_core_ops rkisp_isp_core_ops = {
..	..	@@ -2678,7 +3761,7 @@
2678	3761	struct ispsd_in_fmt *in_fmt = &isp_sd->in_fmt;
2679	3762	struct ispsd_out_fmt *out_fmt = &isp_sd->out_fmt;
2680	3763
2681		- *in_fmt = rkisp_isp_input_formats[0];
	3764	+ *in_fmt = rkisp_isp_input_formats[8];
2682	3765	in_frm->width = RKISP_DEFAULT_WIDTH;
2683	3766	in_frm->height = RKISP_DEFAULT_HEIGHT;
2684	3767	in_frm->code = in_fmt->mbus_code;
..	..	@@ -2702,6 +3785,8 @@
2702	3785	struct v4l2_subdev *sd = &isp_sdev->sd;
2703	3786	int ret;
2704	3787
	3788	+ mutex_init(&isp_dev->buf_lock);
	3789	+ spin_lock_init(&isp_dev->cmsk_lock);
2705	3790	spin_lock_init(&isp_dev->rdbk_lock);
2706	3791	ret = kfifo_alloc(&isp_dev->rdbk_kfifo,
2707	3792	16 * sizeof(struct isp2x_csi_trigger), GFP_KERNEL);
..	..	@@ -2739,8 +3824,10 @@
2739	3824	rkisp_isp_sd_init_default_fmt(isp_sdev);
2740	3825	isp_dev->hdr.sensor = NULL;
2741	3826	isp_dev->isp_state = ISP_STOP;
2742		-
	3827	+ atomic_set(&isp_sdev->frm_sync_seq, 0);
2743	3828	rkisp_monitor_init(isp_dev);
	3829	+ INIT_WORK(&isp_dev->rdbk_work, rkisp_rdbk_work);
	3830	+ init_completion(&isp_dev->pm_cmpl);
2744	3831	return 0;
2745	3832	err_cleanup_media_entity:
2746	3833	media_entity_cleanup(&sd->entity);
..	..	@@ -2780,56 +3867,120 @@
2780	3867	(cond) ? 0 : -ETIMEDOUT; \
2781	3868	})
2782	3869
	3870	+void rkisp_save_tb_info(struct rkisp_device *isp_dev)
	3871	+{
	3872	+ struct rkisp_isp_params_vdev *params_vdev = &isp_dev->params_vdev;
	3873	+ void *resmem_va = phys_to_virt(isp_dev->resmem_pa);
	3874	+ struct rkisp_thunderboot_resmem_head *head = resmem_va;
	3875	+ int size = 0, offset = 0;
	3876	+ void *param = NULL;
	3877	+
	3878	+ switch (isp_dev->isp_ver) {
	3879	+ case ISP_V32:
	3880	+ size = sizeof(struct rkisp32_thunderboot_resmem_head);
	3881	+ offset = size * isp_dev->dev_id;
	3882	+ break;
	3883	+ default:
	3884	+ break;
	3885	+ }
	3886	+
	3887	+ if (size && size < isp_dev->resmem_size) {
	3888	+ dma_sync_single_for_cpu(isp_dev->dev, isp_dev->resmem_addr + offset,
	3889	+ size, DMA_FROM_DEVICE);
	3890	+ if (isp_dev->is_rtt_first)
	3891	+ params_vdev->is_first_cfg = true;
	3892	+ if (isp_dev->isp_ver == ISP_V32) {
	3893	+ struct rkisp32_thunderboot_resmem_head *tmp = resmem_va + offset;
	3894	+
	3895	+ param = &tmp->cfg;
	3896	+ head = &tmp->head;
	3897	+ v4l2_info(&isp_dev->v4l2_dev,
	3898	+ "tb param module en:0x%llx upd:0x%llx cfg upd:0x%llx\n",
	3899	+ tmp->cfg.module_en_update,
	3900	+ tmp->cfg.module_ens,
	3901	+ tmp->cfg.module_cfg_update);
	3902	+ }
	3903	+ if (param && (isp_dev->isp_state & ISP_STOP))
	3904	+ params_vdev->ops->save_first_param(params_vdev, param);
	3905	+ } else if (size > isp_dev->resmem_size) {
	3906	+ v4l2_err(&isp_dev->v4l2_dev,
	3907	+ "resmem size:%zu no enough for head:%d\n",
	3908	+ isp_dev->resmem_size, size);
	3909	+ head->complete = RKISP_TB_NG;
	3910	+ }
	3911	+ memcpy(&isp_dev->tb_head, head, sizeof(*head));
	3912	+}
	3913	+
2783	3914	#ifdef CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP
2784	3915	void rkisp_chk_tb_over(struct rkisp_device *isp_dev)
2785	3916	{
	3917	+ struct rkisp_isp_params_vdev *params_vdev = &isp_dev->params_vdev;
	3918	+ struct rkisp_hw_dev *hw = isp_dev->hw_dev;
2786	3919	struct rkisp_thunderboot_resmem_head *head;
2787	3920	enum rkisp_tb_state tb_state;
2788	3921	void *resmem_va;
2789	3922
2790		- if (!isp_dev->hw_dev->is_thunderboot)
	3923	+ if (!isp_dev->is_thunderboot)
2791	3924	return;
2792	3925
2793		- if (!atomic_read(&isp_dev->hw_dev->tb_ref)) {
2794		- rkisp_tb_set_state(RKISP_TB_NG);
2795		- rkisp_tb_unprotect_clk();
2796		- rkisp_register_irq(isp_dev->hw_dev);
2797		- isp_dev->hw_dev->is_thunderboot = false;
2798		- return;
2799		- }
	3926	+ if (isp_dev->isp_ver == ISP_V32 && params_vdev->is_first_cfg)
	3927	+ goto end;
2800	3928
2801	3929	resmem_va = phys_to_virt(isp_dev->resmem_pa);
2802	3930	head = (struct rkisp_thunderboot_resmem_head *)resmem_va;
2803		- if (isp_dev->is_thunderboot) {
2804		- shm_head_poll_timeout(isp_dev, !!head->enable, 2000, 200 * USEC_PER_MSEC);
2805		- shm_head_poll_timeout(isp_dev, !!head->complete, 5000, 600 * USEC_PER_MSEC);
2806		- if (head->complete != RKISP_TB_OK)
2807		- v4l2_info(&isp_dev->v4l2_dev,
2808		- "wait thunderboot over timeout\n");
	3931	+ dma_sync_single_for_cpu(isp_dev->dev, isp_dev->resmem_addr,
	3932	+ sizeof(struct rkisp_thunderboot_resmem_head),
	3933	+ DMA_FROM_DEVICE);
2809	3934
2810		- v4l2_info(&isp_dev->v4l2_dev,
2811		- "thunderboot info: %d, %d, %d, %d, %d, %d, 0x%x\n",
2812		- head->enable,
2813		- head->complete,
2814		- head->frm_total,
2815		- head->hdr_mode,
2816		- head->width,
2817		- head->height,
2818		- head->bus_fmt);
	3935	+ shm_head_poll_timeout(isp_dev, !!head->complete, 5000, 400 * USEC_PER_MSEC);
	3936	+ if (head->complete != RKISP_TB_OK) {
	3937	+ v4l2_err(&isp_dev->v4l2_dev, "wait thunderboot over timeout\n");
	3938	+ } else {
	3939	+ int i, timeout = 50;
2819	3940
2820		- tb_state = RKISP_TB_OK;
2821		- if (head->complete != RKISP_TB_OK) {
2822		- head->frm_total = 0;
2823		- tb_state = RKISP_TB_NG;
	3941	+ /* wait for all isp dev to register */
	3942	+ if (head->camera_num > 1) {
	3943	+ while (timeout--) {
	3944	+ if (hw->dev_num >= head->camera_num &&
	3945	+ hw->isp[hw->dev_num - 1]->is_probe_end)
	3946	+ break;
	3947	+ usleep_range(200, 210);
	3948	+ }
	3949	+ if (head->camera_num > hw->dev_num) {
	3950	+ v4l2_err(&isp_dev->v4l2_dev,
	3951	+ "thunderboot invalid camera num:%d, dev num:%d\n",
	3952	+ head->camera_num, hw->dev_num);
	3953	+ goto end;
	3954	+ }
2824	3955	}
	3956	+ for (i = 0; i < head->camera_num; i++)
	3957	+ rkisp_save_tb_info(hw->isp[i]);
	3958	+ }
	3959	+end:
	3960	+ head = &isp_dev->tb_head;
	3961	+ v4l2_info(&isp_dev->v4l2_dev,
	3962	+ "tb info en:%d comp:%d cnt:%d w:%d h:%d cam:%d idx:%d\n",
	3963	+ head->enable,
	3964	+ head->complete,
	3965	+ head->frm_total,
	3966	+ head->width,
	3967	+ head->height,
	3968	+ head->camera_num,
	3969	+ head->camera_index);
	3970	+
	3971	+ tb_state = RKISP_TB_OK;
	3972	+ if (head->complete != RKISP_TB_OK) {
	3973	+ head->frm_total = 0;
	3974	+ tb_state = RKISP_TB_NG;
	3975	+ }
	3976	+
	3977	+ if (hw->is_thunderboot) {
	3978	+ rkisp_register_irq(hw);
2825	3979	rkisp_tb_set_state(tb_state);
2826	3980	rkisp_tb_unprotect_clk();
2827		- rkisp_register_irq(isp_dev->hw_dev);
2828		- pm_runtime_put(isp_dev->hw_dev->dev);
2829		- isp_dev->hw_dev->is_thunderboot = false;
2830		- isp_dev->is_thunderboot = false;
2831		- atomic_dec(&isp_dev->hw_dev->tb_ref);
	3981	+ hw->is_thunderboot = false;
2832	3982	}
	3983	+ isp_dev->is_thunderboot = false;
2833	3984	}
2834	3985	#endif
2835	3986
..	..	@@ -2937,7 +4088,9 @@
2937	4088	unsigned int isp3a_mis,
2938	4089	struct rkisp_device *dev)
2939	4090	{
2940		- void __iomem *base = dev->base_addr;
	4091	+ struct rkisp_hw_dev *hw = dev->hw_dev;
	4092	+ void __iomem *base = hw->unite != ISP_UNITE_TWO ?
	4093	+ hw->base_addr : hw->base_next_addr;
2941	4094	unsigned int isp_mis_tmp = 0;
2942	4095	unsigned int isp_err = 0;
2943	4096	u32 si3a_isr_mask = ISP2X_SIAWB_DONE \| ISP2X_SIAF_FIN \|
..	..	@@ -2947,7 +4100,7 @@
2947	4100	ISP2X_3A_RAWHIST_BIG \| ISP2X_3A_RAWHIST_CH0 \|
2948	4101	ISP2X_3A_RAWHIST_CH1 \| ISP2X_3A_RAWHIST_CH2 \|
2949	4102	ISP2X_3A_RAWAF_SUM \| ISP2X_3A_RAWAF_LUM \|
2950		- ISP2X_3A_RAWAF \| ISP2X_3A_RAWAWB;
	4103	+ ISP2X_3A_RAWAWB;
2951	4104	bool sof_event_later = false;
2952	4105
2953	4106	/*
..	..	@@ -2957,40 +4110,51 @@
2957	4110	if (isp3a_mis & ISP2X_3A_RAWAE_BIG && dev->params_vdev.rdbk_times > 0)
2958	4111	writel(BIT(31), base + RAWAE_BIG1_BASE + RAWAE_BIG_CTRL);
2959	4112
	4113	+ if (hw->unite == ISP_UNITE_TWO) {
	4114	+ u32 val = rkisp_read(dev, ISP3X_ISP_RIS, true);
	4115	+
	4116	+ if (val) {
	4117	+ rkisp_write(dev, ISP3X_ISP_ICR, val, true);
	4118	+ v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
	4119	+ "left isp isr:0x%x\n", val);
	4120	+ if (isp_mis & CIF_ISP_FRAME && !(val & CIF_ISP_FRAME)) {
	4121	+ /* wait isp0 frame end */
	4122	+ int timeout = read_poll_timeout_atomic(rkisp_read,
	4123	+ val, val & CIF_ISP_FRAME, 20, 20 * 50, true, dev, ISP3X_ISP_RIS, true);
	4124	+
	4125	+ if (val)
	4126	+ rkisp_write(dev, ISP3X_ISP_ICR, val, true);
	4127	+ if (timeout)
	4128	+ dev_err(dev->dev, "wait isp end timeout\n");
	4129	+ }
	4130	+ }
	4131	+ }
2960	4132	v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
2961	4133	"isp isr:0x%x, 0x%x\n", isp_mis, isp3a_mis);
2962	4134	dev->isp_isr_cnt++;
2963	4135	/* start edge of v_sync */
2964	4136	if (isp_mis & CIF_ISP_V_START) {
2965		- if (dev->isp_state & ISP_FRAME_END) {
2966		- u64 tmp = dev->isp_sdev.dbg.interval +
2967		- dev->isp_sdev.dbg.timestamp;
2968		-
2969		- dev->isp_sdev.dbg.timestamp = ktime_get_ns();
2970		- /* v-blank: frame_end - frame_start */
2971		- dev->isp_sdev.dbg.delay = dev->isp_sdev.dbg.timestamp - tmp;
2972		- }
2973		- rkisp_set_state(&dev->isp_state, ISP_FRAME_VS);
2974	4137	if (dev->hw_dev->monitor.is_en) {
2975	4138	rkisp_set_state(&dev->hw_dev->monitor.state, ISP_FRAME_VS);
2976	4139	if (!completion_done(&dev->hw_dev->monitor.cmpl))
2977	4140	complete(&dev->hw_dev->monitor.cmpl);
2978	4141	}
2979		- /* last vsync to config next buf */
2980		- if (!dev->filt_state[RDBK_F_VS])
2981		- rkisp_bridge_update_mi(dev, isp_mis);
2982		- else
2983		- dev->filt_state[RDBK_F_VS]--;
	4142	+
2984	4143	if (IS_HDR_RDBK(dev->hdr.op_mode)) {
2985		- /* read 3d lut at isp readback */
2986		- if (!dev->hw_dev->is_single)
2987		- rkisp_write(dev, ISP_3DLUT_UPDATE, 0, true);
	4144	+ /* disabled frame end to read 3dlut for multi sensor
	4145	+ * 3dlut will update at isp readback
	4146	+ */
	4147	+ if (!dev->hw_dev->is_single) {
	4148	+ writel(0, hw->base_addr + ISP_3DLUT_UPDATE);
	4149	+ if (hw->unite == ISP_UNITE_TWO)
	4150	+ writel(0, hw->base_next_addr + ISP_3DLUT_UPDATE);
	4151	+ }
2988	4152	rkisp_stats_rdbk_enable(&dev->stats_vdev, true);
2989	4153	goto vs_skip;
2990	4154	}
2991	4155	if (dev->cap_dev.stream[RKISP_STREAM_SP].interlaced) {
2992	4156	/* 0 = ODD 1 = EVEN */
2993		- if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2) {
	4157	+ if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
2994	4158	void __iomem *addr = NULL;
2995	4159
2996	4160	if (dev->isp_ver == ISP_V10 \|\|
..	..	@@ -3012,8 +4176,9 @@
3012	4176	if (isp_mis & CIF_ISP_FRAME)
3013	4177	sof_event_later = true;
3014	4178	if (dev->vs_irq < 0 && !sof_event_later) {
3015		- dev->isp_sdev.frm_timestamp = ktime_get_ns();
	4179	+ dev->isp_sdev.frm_timestamp = rkisp_time_get_ns(dev);
3016	4180	rkisp_isp_queue_event_sof(&dev->isp_sdev);
	4181	+ rkisp_stream_frame_start(dev, isp_mis);
3017	4182	}
3018	4183	vs_skip:
3019	4184	writel(CIF_ISP_V_START, base + CIF_ISP_ICR);
..	..	@@ -3057,6 +4222,16 @@
3057	4222	}
3058	4223	}
3059	4224
	4225	+ if (isp3a_mis & ISP2X_3A_RAWAF) {
	4226	+ writel(ISP3X_3A_RAWAF, base + ISP3X_ISP_3A_ICR);
	4227	+ /* 3a irq will with lsc_lut_err irq if isp version below isp32 */
	4228	+ if (isp_mis & ISP2X_LSC_LUT_ERR)
	4229	+ isp_mis &= ~ISP2X_LSC_LUT_ERR;
	4230	+ if (dev->rawaf_irq_cnt == 0)
	4231	+ rkisp_stream_buf_done_early(dev);
	4232	+ dev->rawaf_irq_cnt++;
	4233	+ }
	4234	+
3060	4235	if (isp_mis & ISP2X_LSC_LUT_ERR) {
3061	4236	writel(ISP2X_LSC_LUT_ERR, base + CIF_ISP_ICR);
3062	4237
..	..	@@ -3068,21 +4243,22 @@
3068	4243
3069	4244	/* sampled input frame is complete */
3070	4245	if (isp_mis & CIF_ISP_FRAME_IN) {
	4246	+ dev->isp_sdev.dbg.interval =
	4247	+ rkisp_time_get_ns(dev) - dev->isp_sdev.dbg.timestamp;
3071	4248	rkisp_set_state(&dev->isp_state, ISP_FRAME_IN);
3072	4249	writel(CIF_ISP_FRAME_IN, base + CIF_ISP_ICR);
3073	4250	isp_mis_tmp = readl(base + CIF_ISP_MIS);
3074	4251	if (isp_mis_tmp & CIF_ISP_FRAME_IN)
3075	4252	v4l2_err(&dev->v4l2_dev, "isp icr frame_in err: 0x%x\n",
3076	4253	isp_mis_tmp);
3077		-
3078		- dev->isp_err_cnt = 0;
3079		- dev->isp_state &= ~ISP_ERROR;
3080	4254	}
3081	4255
3082	4256	/* frame was completely put out */
3083	4257	if (isp_mis & CIF_ISP_FRAME) {
3084		- dev->isp_sdev.dbg.interval =
3085		- ktime_get_ns() - dev->isp_sdev.dbg.timestamp;
	4258	+ dev->rawaf_irq_cnt = 0;
	4259	+ if (!dev->is_pre_on \|\| !IS_HDR_RDBK(dev->rd_mode))
	4260	+ dev->isp_sdev.dbg.interval =
	4261	+ rkisp_time_get_ns(dev) - dev->isp_sdev.dbg.timestamp;
3086	4262	/* Clear Frame In (ISP) */
3087	4263	rkisp_set_state(&dev->isp_state, ISP_FRAME_END);
3088	4264	writel(CIF_ISP_FRAME, base + CIF_ISP_ICR);
..	..	@@ -3092,6 +4268,25 @@
3092	4268	"isp icr frame end err: 0x%x\n", isp_mis_tmp);
3093	4269	rkisp_dmarx_get_frame(dev, &dev->isp_sdev.dbg.id, NULL, NULL, true);
3094	4270	rkisp_isp_read_add_fifo_data(dev);
	4271	+
	4272	+ dev->isp_err_cnt = 0;
	4273	+ dev->isp_state &= ~ISP_ERROR;
	4274	+ }
	4275	+
	4276	+ if (isp_mis & CIF_ISP_V_START) {
	4277	+ if (dev->isp_state & ISP_FRAME_END) {
	4278	+ u64 tmp = dev->isp_sdev.dbg.interval +
	4279	+ dev->isp_sdev.dbg.timestamp;
	4280	+
	4281	+ dev->isp_sdev.dbg.timestamp = rkisp_time_get_ns(dev);
	4282	+ /* v-blank: frame(N)start - frame(N-1)end */
	4283	+ dev->isp_sdev.dbg.delay = dev->isp_sdev.dbg.timestamp - tmp;
	4284	+ }
	4285	+ rkisp_set_state(&dev->isp_state, ISP_FRAME_VS);
	4286	+ if (dev->procfs.is_fs_wait) {
	4287	+ dev->procfs.is_fs_wait = false;
	4288	+ wake_up(&dev->procfs.fs_wait);
	4289	+ }
3095	4290	}
3096	4291
3097	4292	if ((isp_mis & (CIF_ISP_FRAME \| si3a_isr_mask)) \|\|
..	..	@@ -3108,6 +4303,21 @@
3108	4303
3109	4304	if ((isp_mis & CIF_ISP_FRAME) && dev->stats_vdev.rdbk_mode)
3110	4305	rkisp_stats_rdbk_enable(&dev->stats_vdev, false);
	4306	+
	4307	+ if (!IS_HDR_RDBK(dev->hdr.op_mode))
	4308	+ rkisp_config_cmsk(dev);
	4309	+ }
	4310	+
	4311	+ if (isp_mis & CIF_ISP_FRAME) {
	4312	+ if (dev->hw_dev->isp_ver == ISP_V32) {
	4313	+ struct rkisp_stream *s = &dev->cap_dev.stream[RKISP_STREAM_LUMA];
	4314	+
	4315	+ s->ops->frame_end(s, FRAME_IRQ);
	4316	+ }
	4317	+ if (dev->procfs.is_fe_wait) {
	4318	+ dev->procfs.is_fe_wait = false;
	4319	+ wake_up(&dev->procfs.fe_wait);
	4320	+ }
3111	4321	}
3112	4322
3113	4323	/*
..	..	@@ -3115,16 +4325,30 @@
3115	4325	* lot of register writes. Do those only one per frame.
3116	4326	* Do the updates in the order of the processing flow.
3117	4327	*/
3118		- rkisp_params_isr(&dev->params_vdev, isp_mis);
	4328	+ if (isp_mis & (CIF_ISP_V_START \| CIF_ISP_FRAME))
	4329	+ rkisp_params_isr(&dev->params_vdev, isp_mis);
3119	4330
3120	4331	/* cur frame end and next frame start irq togeter */
3121	4332	if (dev->vs_irq < 0 && sof_event_later) {
3122		- dev->isp_sdev.frm_timestamp = ktime_get_ns();
	4333	+ dev->isp_sdev.frm_timestamp = rkisp_time_get_ns(dev);
3123	4334	rkisp_isp_queue_event_sof(&dev->isp_sdev);
	4335	+ rkisp_stream_frame_start(dev, isp_mis);
3124	4336	}
3125	4337
3126		- if (isp_mis & CIF_ISP_FRAME_IN)
3127		- rkisp_check_idle(dev, ISP_FRAME_IN);
	4338	+ if (isp_mis & ISP3X_OUT_FRM_QUARTER) {
	4339	+ writel(ISP3X_OUT_FRM_QUARTER, base + CIF_ISP_ICR);
	4340	+ rkisp_dvbm_event(dev, ISP3X_OUT_FRM_QUARTER);
	4341	+ }
	4342	+ if (isp_mis & ISP3X_OUT_FRM_HALF) {
	4343	+ writel(ISP3X_OUT_FRM_HALF, base + CIF_ISP_ICR);
	4344	+ rkisp_dvbm_event(dev, ISP3X_OUT_FRM_HALF);
	4345	+ rkisp_stream_buf_done_early(dev);
	4346	+ }
	4347	+ if (isp_mis & ISP3X_OUT_FRM_END) {
	4348	+ writel(ISP3X_OUT_FRM_END, base + CIF_ISP_ICR);
	4349	+ rkisp_dvbm_event(dev, ISP3X_OUT_FRM_END);
	4350	+ }
	4351	+
3128	4352	if (isp_mis & CIF_ISP_FRAME)
3129	4353	rkisp_check_idle(dev, ISP_FRAME_END);
3130	4354	}