hc
2024-05-10 cde9070d9970eef1f7ec2360586c802a16230ad8
kernel/drivers/gpu/drm/nouveau/include/nvif/class.h
....@@ -1,4 +1,4 @@
1
-/* SPDX-License-Identifier: GPL-2.0 */
1
+/* SPDX-License-Identifier: MIT */
22 #ifndef __NVIF_CLASS_H__
33 #define __NVIF_CLASS_H__
44
....@@ -54,6 +54,9 @@
5454
5555 #define VOLTA_USERMODE_A 0x0000c361
5656
57
+#define MAXWELL_FAULT_BUFFER_A /* clb069.h */ 0x0000b069
58
+#define VOLTA_FAULT_BUFFER_A /* clb069.h */ 0x0000c369
59
+
5760 #define NV03_CHANNEL_DMA /* cl506b.h */ 0x0000006b
5861 #define NV10_CHANNEL_DMA /* cl506b.h */ 0x0000006e
5962 #define NV17_CHANNEL_DMA /* cl506b.h */ 0x0000176e
....@@ -68,7 +71,8 @@
6871 #define KEPLER_CHANNEL_GPFIFO_B /* cla06f.h */ 0x0000a16f
6972 #define MAXWELL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000b06f
7073 #define PASCAL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000c06f
71
-#define VOLTA_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000c36f
74
+#define VOLTA_CHANNEL_GPFIFO_A /* clc36f.h */ 0x0000c36f
75
+#define TURING_CHANNEL_GPFIFO_A /* clc36f.h */ 0x0000c46f
7276
7377 #define NV50_DISP /* cl5070.h */ 0x00005070
7478 #define G82_DISP /* cl5070.h */ 0x00008270
....@@ -83,6 +87,9 @@
8387 #define GP100_DISP /* cl5070.h */ 0x00009770
8488 #define GP102_DISP /* cl5070.h */ 0x00009870
8589 #define GV100_DISP /* cl5070.h */ 0x0000c370
90
+#define TU102_DISP /* cl5070.h */ 0x0000c570
91
+
92
+#define GV100_DISP_CAPS 0x0000c373
8693
8794 #define NV31_MPEG 0x00003174
8895 #define G82_MPEG 0x00008274
....@@ -95,6 +102,7 @@
95102 #define GF110_DISP_CURSOR /* cl507a.h */ 0x0000907a
96103 #define GK104_DISP_CURSOR /* cl507a.h */ 0x0000917a
97104 #define GV100_DISP_CURSOR /* cl507a.h */ 0x0000c37a
105
+#define TU102_DISP_CURSOR /* cl507a.h */ 0x0000c57a
98106
99107 #define NV50_DISP_OVERLAY /* cl507b.h */ 0x0000507b
100108 #define G82_DISP_OVERLAY /* cl507b.h */ 0x0000827b
....@@ -103,6 +111,7 @@
103111 #define GK104_DISP_OVERLAY /* cl507b.h */ 0x0000917b
104112
105113 #define GV100_DISP_WINDOW_IMM_CHANNEL_DMA /* clc37b.h */ 0x0000c37b
114
+#define TU102_DISP_WINDOW_IMM_CHANNEL_DMA /* clc37b.h */ 0x0000c57b
106115
107116 #define NV50_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000507c
108117 #define G82_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000827c
....@@ -125,6 +134,7 @@
125134 #define GP100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000977d
126135 #define GP102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000987d
127136 #define GV100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000c37d
137
+#define TU102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000c57d
128138
129139 #define NV50_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000507e
130140 #define G82_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000827e
....@@ -134,6 +144,7 @@
134144 #define GK104_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000917e
135145
136146 #define GV100_DISP_WINDOW_CHANNEL_DMA /* clc37e.h */ 0x0000c37e
147
+#define TU102_DISP_WINDOW_CHANNEL_DMA /* clc37e.h */ 0x0000c57e
137148
138149 #define NV50_TESLA 0x00005097
139150 #define G82_TESLA 0x00008297
....@@ -156,6 +167,8 @@
156167 #define PASCAL_B /* cl9097.h */ 0x0000c197
157168
158169 #define VOLTA_A /* cl9097.h */ 0x0000c397
170
+
171
+#define TURING_A /* cl9097.h */ 0x0000c597
159172
160173 #define NV74_BSP 0x000074b0
161174
....@@ -183,6 +196,7 @@
183196 #define PASCAL_DMA_COPY_A 0x0000c0b5
184197 #define PASCAL_DMA_COPY_B 0x0000c1b5
185198 #define VOLTA_DMA_COPY_A 0x0000c3b5
199
+#define TURING_DMA_COPY_A 0x0000c5b5
186200
187201 #define FERMI_DECOMPRESS 0x000090b8
188202
....@@ -197,6 +211,7 @@
197211 #define PASCAL_COMPUTE_A 0x0000c0c0
198212 #define PASCAL_COMPUTE_B 0x0000c1c0
199213 #define VOLTA_COMPUTE_A 0x0000c3c0
214
+#define TURING_COMPUTE_A 0x0000c5c0
200215
201216 #define NV74_CIPHER 0x000074c1
202217 #endif