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2024-05-10 cde9070d9970eef1f7ec2360586c802a16230ad8 
 kernel/drivers/gpu/drm/meson/meson_vclk.c
....@@ -1,25 +1,14 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (C) 2016 BayLibre, SAS
34  * Author: Neil Armstrong <narmstrong@baylibre.com>
45  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5
- *
6
- * This program is free software; you can redistribute it and/or
7
- * modify it under the terms of the GNU General Public License as
8
- * published by the Free Software Foundation; either version 2 of the
9
- * License, or (at your option) any later version.
10
- *
11
- * This program is distributed in the hope that it will be useful, but
12
- * WITHOUT ANY WARRANTY; without even the implied warranty of
13
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
- * General Public License for more details.
15
- *
16
- * You should have received a copy of the GNU General Public License
17
- * along with this program; if not, see <http://www.gnu.org/licenses/>.
186  */
197 
20
-#include <linux/kernel.h>
21
-#include <linux/module.h>
22
-#include <drm/drmP.h>
8
+#include <linux/export.h>
9
+
10
+#include <drm/drm_print.h>
11
+
2312 #include "meson_drv.h"
2413 #include "meson_vclk.h"
2514 
....@@ -108,14 +97,20 @@
10897 #define HHI_VDAC_CNTL1		0x2F8 /* 0xbe offset in data sheet */
10998 
11099 #define HHI_HDMI_PLL_CNTL	0x320 /* 0xc8 offset in data sheet */
100
+#define HHI_HDMI_PLL_CNTL_EN	BIT(30)
111101 #define HHI_HDMI_PLL_CNTL2	0x324 /* 0xc9 offset in data sheet */
112102 #define HHI_HDMI_PLL_CNTL3	0x328 /* 0xca offset in data sheet */
113103 #define HHI_HDMI_PLL_CNTL4	0x32C /* 0xcb offset in data sheet */
114104 #define HHI_HDMI_PLL_CNTL5	0x330 /* 0xcc offset in data sheet */
115105 #define HHI_HDMI_PLL_CNTL6	0x334 /* 0xcd offset in data sheet */
106
+#define HHI_HDMI_PLL_CNTL7	0x338 /* 0xce offset in data sheet */
116107 
117108 #define HDMI_PLL_RESET		BIT(28)
109
+#define HDMI_PLL_RESET_G12A	BIT(29)
118110 #define HDMI_PLL_LOCK		BIT(31)
111
+#define HDMI_PLL_LOCK_G12A	(3 << 30)
112
+
113
+#define FREQ_1000_1001(_freq)	DIV_ROUND_CLOSEST(_freq * 1000, 1001)
119114 
120115 /* VID PLL Dividers */
121116 enum {
....@@ -247,7 +242,7 @@
247242 	unsigned int val;
248243 
249244 	/* Setup PLL to output 1.485GHz */
250
-	if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
245
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
251246 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800023d);
252247 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00404e00);
253248 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
....@@ -255,8 +250,12 @@
255250 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
256251 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
257252 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4800023d);
258
-	} else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
259
-		   meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
253
+
254
+		/* Poll for lock bit */
255
+		regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
256
+					 (val & HDMI_PLL_LOCK), 10, 0);
257
+	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
258
+		   meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
260259 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000027b);
261260 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb300);
262261 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0xa6212844);
....@@ -269,11 +268,26 @@
269268 					HDMI_PLL_RESET, HDMI_PLL_RESET);
270269 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
271270 					HDMI_PLL_RESET, 0);
272
-	}
273271 
274
-	/* Poll for lock bit */
275
-	regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
276
-				 (val & HDMI_PLL_LOCK), 10, 0);
272
+		/* Poll for lock bit */
273
+		regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
274
+					 (val & HDMI_PLL_LOCK), 10, 0);
275
+	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
276
+		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7);
277
+		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00010000);
278
+		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000);
279
+		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x6a28dc00);
280
+		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x65771290);
281
+		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000);
282
+		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x56540000);
283
+		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x3a0504f7);
284
+		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7);
285
+
286
+		/* Poll for lock bit */
287
+		regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
288
+			((val & HDMI_PLL_LOCK_G12A) == HDMI_PLL_LOCK_G12A),
289
+			10, 0);
290
+	}
277291 
278292 	/* Disable VCLK2 */
279293 	regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
....@@ -286,8 +300,13 @@
286300 				VCLK2_DIV_MASK, (55 - 1));
287301 
288302 	/* select vid_pll for vclk2 */
289
-	regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
290
-				VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT));
303
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
304
+		regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
305
+					VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
306
+	else
307
+		regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
308
+					VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT));
309
+
291310 	/* enable vclk2 gate */
292311 	regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
293312 
....@@ -323,7 +342,7 @@
323342 enum {
324343 /* PLL	O1 O2 O3 VP DV     EN TX */
325344 /* 4320 /4 /4 /1 /5 /1  => /2 /2 */
326
-	MESON_VCLK_HDMI_ENCI_54000 = 1,
345
+	MESON_VCLK_HDMI_ENCI_54000 = 0,
327346 /* 4320 /4 /4 /1 /5 /1  => /1 /2 */
328347 	MESON_VCLK_HDMI_DDR_54000,
329348 /* 2970 /4 /1 /1 /5 /1  => /1 /2 */
....@@ -335,11 +354,17 @@
335354 /* 2970 /1 /1 /1 /5 /2  => /1 /1 */
336355 	MESON_VCLK_HDMI_297000,
337356 /* 5940 /1 /1 /2 /5 /1  => /1 /1 */
338
-	MESON_VCLK_HDMI_594000
357
+	MESON_VCLK_HDMI_594000,
358
+/* 2970 /1 /1 /1 /5 /1  => /1 /2 */
359
+	MESON_VCLK_HDMI_594000_YUV420,
339360 };
340361 
341362 struct meson_vclk_params {
342
-	unsigned int pll_base_freq;
363
+	unsigned int pll_freq;
364
+	unsigned int phy_freq;
365
+	unsigned int vclk_freq;
366
+	unsigned int venc_freq;
367
+	unsigned int pixel_freq;
343368 	unsigned int pll_od1;
344369 	unsigned int pll_od2;
345370 	unsigned int pll_od3;
....@@ -347,7 +372,11 @@
347372 	unsigned int vclk_div;
348373 } params[] = {
349374 	[MESON_VCLK_HDMI_ENCI_54000] = {
350
-		.pll_base_freq = 4320000,
375
+		.pll_freq = 4320000,
376
+		.phy_freq = 270000,
377
+		.vclk_freq = 54000,
378
+		.venc_freq = 54000,
379
+		.pixel_freq = 54000,
351380 		.pll_od1 = 4,
352381 		.pll_od2 = 4,
353382 		.pll_od3 = 1,
....@@ -355,7 +384,11 @@
355384 		.vclk_div = 1,
356385 	},
357386 	[MESON_VCLK_HDMI_DDR_54000] = {
358
-		.pll_base_freq = 4320000,
387
+		.pll_freq = 4320000,
388
+		.phy_freq = 270000,
389
+		.vclk_freq = 54000,
390
+		.venc_freq = 54000,
391
+		.pixel_freq = 27000,
359392 		.pll_od1 = 4,
360393 		.pll_od2 = 4,
361394 		.pll_od3 = 1,
....@@ -363,7 +396,11 @@
363396 		.vclk_div = 1,
364397 	},
365398 	[MESON_VCLK_HDMI_DDR_148500] = {
366
-		.pll_base_freq = 2970000,
399
+		.pll_freq = 2970000,
400
+		.phy_freq = 742500,
401
+		.vclk_freq = 148500,
402
+		.venc_freq = 148500,
403
+		.pixel_freq = 74250,
367404 		.pll_od1 = 4,
368405 		.pll_od2 = 1,
369406 		.pll_od3 = 1,
....@@ -371,7 +408,11 @@
371408 		.vclk_div = 1,
372409 	},
373410 	[MESON_VCLK_HDMI_74250] = {
374
-		.pll_base_freq = 2970000,
411
+		.pll_freq = 2970000,
412
+		.phy_freq = 742500,
413
+		.vclk_freq = 74250,
414
+		.venc_freq = 74250,
415
+		.pixel_freq = 74250,
375416 		.pll_od1 = 2,
376417 		.pll_od2 = 2,
377418 		.pll_od3 = 2,
....@@ -379,7 +420,11 @@
379420 		.vclk_div = 1,
380421 	},
381422 	[MESON_VCLK_HDMI_148500] = {
382
-		.pll_base_freq = 2970000,
423
+		.pll_freq = 2970000,
424
+		.phy_freq = 1485000,
425
+		.vclk_freq = 148500,
426
+		.venc_freq = 148500,
427
+		.pixel_freq = 148500,
383428 		.pll_od1 = 1,
384429 		.pll_od2 = 2,
385430 		.pll_od3 = 2,
....@@ -387,21 +432,42 @@
387432 		.vclk_div = 1,
388433 	},
389434 	[MESON_VCLK_HDMI_297000] = {
390
-		.pll_base_freq = 2970000,
391
-		.pll_od1 = 1,
435
+		.pll_freq = 5940000,
436
+		.phy_freq = 2970000,
437
+		.venc_freq = 297000,
438
+		.vclk_freq = 297000,
439
+		.pixel_freq = 297000,
440
+		.pll_od1 = 2,
392441 		.pll_od2 = 1,
393442 		.pll_od3 = 1,
394443 		.vid_pll_div = VID_PLL_DIV_5,
395444 		.vclk_div = 2,
396445 	},
397446 	[MESON_VCLK_HDMI_594000] = {
398
-		.pll_base_freq = 5940000,
447
+		.pll_freq = 5940000,
448
+		.phy_freq = 5940000,
449
+		.venc_freq = 594000,
450
+		.vclk_freq = 594000,
451
+		.pixel_freq = 594000,
399452 		.pll_od1 = 1,
400453 		.pll_od2 = 1,
401454 		.pll_od3 = 2,
402455 		.vid_pll_div = VID_PLL_DIV_5,
403456 		.vclk_div = 1,
404457 	},
458
+	[MESON_VCLK_HDMI_594000_YUV420] = {
459
+		.pll_freq = 5940000,
460
+		.phy_freq = 2970000,
461
+		.venc_freq = 594000,
462
+		.vclk_freq = 594000,
463
+		.pixel_freq = 297000,
464
+		.pll_od1 = 2,
465
+		.pll_od2 = 1,
466
+		.pll_od3 = 1,
467
+		.vid_pll_div = VID_PLL_DIV_5,
468
+		.vclk_div = 1,
469
+	},
470
+	{ /* sentinel */ },
405471 };
406472 
407473 static inline unsigned int pll_od_to_reg(unsigned int od)
....@@ -427,7 +493,7 @@
427493 {
428494 	unsigned int val;
429495 
430
-	if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
496
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
431497 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000200 | m);
432498 		if (frac)
433499 			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2,
....@@ -442,13 +508,13 @@
442508 
443509 		/* Enable and unreset */
444510 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
445
-				   0x7 << 28, 0x4 << 28);
511
+				   0x7 << 28, HHI_HDMI_PLL_CNTL_EN);
446512 
447513 		/* Poll for lock bit */
448514 		regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
449515 					 val, (val & HDMI_PLL_LOCK), 10, 0);
450
-	} else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
451
-		   meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
516
+	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
517
+		   meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
452518 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000200 | m);
453519 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac);
454520 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
....@@ -465,32 +531,90 @@
465531 		/* Poll for lock bit */
466532 		regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
467533 				(val & HDMI_PLL_LOCK), 10, 0);
534
+	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
535
+		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x0b3a0400 | m);
536
+
537
+		/* Enable and reset */
538
+		/* TODO: add specific macro for g12a here */
539
+		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
540
+				   0x3 << 28, 0x3 << 28);
541
+
542
+		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, frac);
543
+		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000);
544
+
545
+		/* G12A HDMI PLL Needs specific parameters for 5.4GHz */
546
+		if (m >= 0xf7) {
547
+			if (frac < 0x10000) {
548
+				regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
549
+							0x6a685c00);
550
+				regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
551
+							0x11551293);
552
+			} else {
553
+				regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
554
+							0xea68dc00);
555
+				regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
556
+							0x65771290);
557
+			}
558
+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000);
559
+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x55540000);
560
+		} else {
561
+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0a691c00);
562
+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x33771290);
563
+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39270000);
564
+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x50540000);
565
+		}
566
+
567
+		do {
568
+			/* Reset PLL */
569
+			regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
570
+					HDMI_PLL_RESET_G12A, HDMI_PLL_RESET_G12A);
571
+
572
+			/* UN-Reset PLL */
573
+			regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
574
+					HDMI_PLL_RESET_G12A, 0);
575
+
576
+			/* Poll for lock bits */
577
+			if (!regmap_read_poll_timeout(priv->hhi,
578
+						      HHI_HDMI_PLL_CNTL, val,
579
+						      ((val & HDMI_PLL_LOCK_G12A)
580
+						        == HDMI_PLL_LOCK_G12A),
581
+						      10, 100))
582
+				break;
583
+		} while(1);
468584 	}
469585 
470
-	if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
586
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
471587 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
472588 				3 << 16, pll_od_to_reg(od1) << 16);
473
-	else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
474
-			meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
589
+	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
590
+		 meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
475591 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
476592 				3 << 21, pll_od_to_reg(od1) << 21);
593
+	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
594
+		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
595
+				3 << 16, pll_od_to_reg(od1) << 16);
477596 
478
-	if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
597
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
479598 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
480599 				3 << 22, pll_od_to_reg(od2) << 22);
481
-	else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
482
-			meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
600
+	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
601
+		 meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
483602 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
484603 				3 << 23, pll_od_to_reg(od2) << 23);
604
+	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
605
+		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
606
+				3 << 18, pll_od_to_reg(od2) << 18);
485607 
486
-	if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
608
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
487609 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
488610 				3 << 18, pll_od_to_reg(od3) << 18);
489
-	else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
490
-			meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
611
+	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
612
+		 meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
491613 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
492614 				3 << 19, pll_od_to_reg(od3) << 19);
493
-
615
+	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
616
+		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
617
+				3 << 20, pll_od_to_reg(od3) << 20);
494618 }
495619 
496620 #define XTAL_FREQ 24000
....@@ -499,7 +623,7 @@
499623 					 unsigned int pll_freq)
500624 {
501625 	/* The GXBB PLL has a /2 pre-multiplier */
502
-	if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
626
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
503627 		pll_freq /= 2;
504628 
505629 	return pll_freq / XTAL_FREQ;
....@@ -507,6 +631,7 @@
507631 
508632 #define HDMI_FRAC_MAX_GXBB	4096
509633 #define HDMI_FRAC_MAX_GXL	1024
634
+#define HDMI_FRAC_MAX_G12A	131072
510635 
511636 static unsigned int meson_hdmi_pll_get_frac(struct meson_drm *priv,
512637 					    unsigned int m,
....@@ -518,10 +643,13 @@
518643 	unsigned int frac;
519644 
520645 	/* The GXBB PLL has a /2 pre-multiplier and a larger FRAC width */
521
-	if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
646
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
522647 		frac_max = HDMI_FRAC_MAX_GXBB;
523648 		parent_freq *= 2;
524649 	}
650
+
651
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
652
+		frac_max = HDMI_FRAC_MAX_G12A;
525653 
526654 	/* We can have a perfect match !*/
527655 	if (pll_freq / m == parent_freq &&
....@@ -541,18 +669,24 @@
541669 					   unsigned int m,
542670 					   unsigned int frac)
543671 {
544
-	if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
672
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
545673 		/* Empiric supported min/max dividers */
546674 		if (m < 53 || m > 123)
547675 			return false;
548676 		if (frac >= HDMI_FRAC_MAX_GXBB)
549677 			return false;
550
-	} else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
551
-		   meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
678
+	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
679
+		   meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
552680 		/* Empiric supported min/max dividers */
553681 		if (m < 106 || m > 247)
554682 			return false;
555683 		if (frac >= HDMI_FRAC_MAX_GXL)
684
+			return false;
685
+	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
686
+		/* Empiric supported min/max dividers */
687
+		if (m < 106 || m > 247)
688
+			return false;
689
+		if (frac >= HDMI_FRAC_MAX_G12A)
556690 			return false;
557691 	}
558692 
....@@ -591,6 +725,13 @@
591725 	/* In DMT mode, path after PLL is always /10 */
592726 	freq *= 10;
593727 
728
+	/* Check against soc revision/package limits */
729
+	if (priv->limits) {
730
+		if (priv->limits->max_hdmi_phy_freq &&
731
+		    freq > priv->limits->max_hdmi_phy_freq)
732
+			return MODE_CLOCK_HIGH;
733
+	}
734
+
594735 	if (meson_hdmi_pll_find_params(priv, freq, &m, &frac, &od))
595736 		return MODE_OK;
596737 
....@@ -605,6 +746,7 @@
605746 	unsigned int od, m, frac, od1, od2, od3;
606747 
607748 	if (meson_hdmi_pll_find_params(priv, pll_freq, &m, &frac, &od)) {
749
+		/* OD2 goes to the PHY, and needs to be *10, so keep OD3=1 */
608750 		od3 = 1;
609751 		if (od < 4) {
610752 			od1 = 2;
....@@ -626,12 +768,51 @@
626768 		  pll_freq);
627769 }
628770 
771
+enum drm_mode_status
772
+meson_vclk_vic_supported_freq(struct meson_drm *priv, unsigned int phy_freq,
773
+			      unsigned int vclk_freq)
774
+{
775
+	int i;
776
+
777
+	DRM_DEBUG_DRIVER("phy_freq = %d vclk_freq = %d\n",
778
+			 phy_freq, vclk_freq);
779
+
780
+	/* Check against soc revision/package limits */
781
+	if (priv->limits) {
782
+		if (priv->limits->max_hdmi_phy_freq &&
783
+		    phy_freq > priv->limits->max_hdmi_phy_freq)
784
+			return MODE_CLOCK_HIGH;
785
+	}
786
+
787
+	for (i = 0 ; params[i].pixel_freq ; ++i) {
788
+		DRM_DEBUG_DRIVER("i = %d pixel_freq = %d alt = %d\n",
789
+				 i, params[i].pixel_freq,
790
+				 FREQ_1000_1001(params[i].pixel_freq));
791
+		DRM_DEBUG_DRIVER("i = %d phy_freq = %d alt = %d\n",
792
+				 i, params[i].phy_freq,
793
+				 FREQ_1000_1001(params[i].phy_freq/10)*10);
794
+		/* Match strict frequency */
795
+		if (phy_freq == params[i].phy_freq &&
796
+		    vclk_freq == params[i].vclk_freq)
797
+			return MODE_OK;
798
+		/* Match 1000/1001 variant */
799
+		if (phy_freq == (FREQ_1000_1001(params[i].phy_freq/10)*10) &&
800
+		    vclk_freq == FREQ_1000_1001(params[i].vclk_freq))
801
+			return MODE_OK;
802
+	}
803
+
804
+	return MODE_CLOCK_RANGE;
805
+}
806
+EXPORT_SYMBOL_GPL(meson_vclk_vic_supported_freq);
807
+
629808 static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
630809 			   unsigned int od1, unsigned int od2, unsigned int od3,
631810 			   unsigned int vid_pll_div, unsigned int vclk_div,
632811 			   unsigned int hdmi_tx_div, unsigned int venc_div,
633
-			   bool hdmi_use_enci)
812
+			   bool hdmi_use_enci, bool vic_alternate_clock)
634813 {
814
+	unsigned int m = 0, frac = 0;
815
+
635816 	/* Set HDMI-TX sys clock */
636817 	regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
637818 			   CTS_HDMI_SYS_SEL_MASK, 0);
....@@ -643,37 +824,58 @@
643824 	/* Set HDMI PLL rate */
644825 	if (!od1 && !od2 && !od3) {
645826 		meson_hdmi_pll_generic_set(priv, pll_base_freq);
646
-	} else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
827
+	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
647828 		switch (pll_base_freq) {
648829 		case 2970000:
649
-			meson_hdmi_pll_set_params(priv, 0x3d, 0xe00,
650
-						  od1, od2, od3);
830
+			m = 0x3d;
831
+			frac = vic_alternate_clock ? 0xd02 : 0xe00;
651832 			break;
652833 		case 4320000:
653
-			meson_hdmi_pll_set_params(priv, 0x5a, 0,
654
-						  od1, od2, od3);
834
+			m = vic_alternate_clock ? 0x59 : 0x5a;
835
+			frac = vic_alternate_clock ? 0xe8f : 0;
655836 			break;
656837 		case 5940000:
657
-			meson_hdmi_pll_set_params(priv, 0x7b, 0xc00,
658
-						  od1, od2, od3);
838
+			m = 0x7b;
839
+			frac = vic_alternate_clock ? 0xa05 : 0xc00;
659840 			break;
660841 		}
661
-	} else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
662
-		   meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
842
+
843
+		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
844
+	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
845
+		   meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
663846 		switch (pll_base_freq) {
664847 		case 2970000:
665
-			meson_hdmi_pll_set_params(priv, 0x7b, 0x300,
666
-						  od1, od2, od3);
848
+			m = 0x7b;
849
+			frac = vic_alternate_clock ? 0x281 : 0x300;
667850 			break;
668851 		case 4320000:
669
-			meson_hdmi_pll_set_params(priv, 0xb4, 0,
670
-						  od1, od2, od3);
852
+			m = vic_alternate_clock ? 0xb3 : 0xb4;
853
+			frac = vic_alternate_clock ? 0x347 : 0;
671854 			break;
672855 		case 5940000:
673
-			meson_hdmi_pll_set_params(priv, 0xf7, 0x200,
674
-						  od1, od2, od3);
856
+			m = 0xf7;
857
+			frac = vic_alternate_clock ? 0x102 : 0x200;
675858 			break;
676859 		}
860
+
861
+		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
862
+	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
863
+		switch (pll_base_freq) {
864
+		case 2970000:
865
+			m = 0x7b;
866
+			frac = vic_alternate_clock ? 0x140b4 : 0x18000;
867
+			break;
868
+		case 4320000:
869
+			m = vic_alternate_clock ? 0xb3 : 0xb4;
870
+			frac = vic_alternate_clock ? 0x1a3ee : 0;
871
+			break;
872
+		case 5940000:
873
+			m = 0xf7;
874
+			frac = vic_alternate_clock ? 0x8148 : 0x10000;
875
+			break;
876
+		}
877
+
878
+		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
677879 	}
678880 
679881 	/* Setup vid_pll divider */
....@@ -823,9 +1025,11 @@
8231025 }
8241026 
8251027 void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
826
-		      unsigned int vclk_freq, unsigned int venc_freq,
827
-		      unsigned int dac_freq, bool hdmi_use_enci)
1028
+		      unsigned int phy_freq, unsigned int vclk_freq,
1029
+		      unsigned int venc_freq, unsigned int dac_freq,
1030
+		      bool hdmi_use_enci)
8281031 {
1032
+	bool vic_alternate_clock = false;
8291033 	unsigned int freq;
8301034 	unsigned int hdmi_tx_div;
8311035 	unsigned int venc_div;
....@@ -834,7 +1038,8 @@
8341038 		meson_venci_cvbs_clock_config(priv);
8351039 		return;
8361040 	} else if (target == MESON_VCLK_TARGET_DMT) {
837
-		/* The DMT clock path is fixed after the PLL:
1041
+		/*
1042
+		 * The DMT clock path is fixed after the PLL:
8381043 		 * - automatic PLL freq + OD management
8391044 		 * - vid_pll_div = VID_PLL_DIV_5
8401045 		 * - vclk_div = 2
....@@ -842,8 +1047,8 @@
8421047 		 * - venc_div = 1
8431048 		 * - encp encoder
8441049 		 */
845
-		meson_vclk_set(priv, vclk_freq * 10, 0, 0, 0,
846
-			       VID_PLL_DIV_5, 2, 1, 1, false);
1050
+		meson_vclk_set(priv, phy_freq, 0, 0, 0,
1051
+			       VID_PLL_DIV_5, 2, 1, 1, false, false);
8471052 		return;
8481053 	}
8491054 
....@@ -863,38 +1068,44 @@
8631068 		return;
8641069 	}
8651070 
866
-	switch (vclk_freq) {
867
-	case 54000:
868
-		if (hdmi_use_enci)
869
-			freq = MESON_VCLK_HDMI_ENCI_54000;
870
-		else
871
-			freq = MESON_VCLK_HDMI_DDR_54000;
872
-		break;
873
-	case 74250:
874
-		freq = MESON_VCLK_HDMI_74250;
875
-		break;
876
-	case 148500:
877
-		if (dac_freq != 148500)
878
-			freq = MESON_VCLK_HDMI_DDR_148500;
879
-		else
880
-			freq = MESON_VCLK_HDMI_148500;
881
-		break;
882
-	case 297000:
883
-		freq = MESON_VCLK_HDMI_297000;
884
-		break;
885
-	case 594000:
886
-		freq = MESON_VCLK_HDMI_594000;
887
-		break;
888
-	default:
889
-		pr_err("Fatal Error, invalid HDMI vclk freq %d\n",
890
-		       vclk_freq);
1071
+	for (freq = 0 ; params[freq].pixel_freq ; ++freq) {
1072
+		if ((phy_freq == params[freq].phy_freq ||
1073
+		     phy_freq == FREQ_1000_1001(params[freq].phy_freq/10)*10) &&
1074
+		    (vclk_freq == params[freq].vclk_freq ||
1075
+		     vclk_freq == FREQ_1000_1001(params[freq].vclk_freq))) {
1076
+			if (vclk_freq != params[freq].vclk_freq)
1077
+				vic_alternate_clock = true;
1078
+			else
1079
+				vic_alternate_clock = false;
1080
+
1081
+			if (freq == MESON_VCLK_HDMI_ENCI_54000 &&
1082
+			    !hdmi_use_enci)
1083
+				continue;
1084
+
1085
+			if (freq == MESON_VCLK_HDMI_DDR_54000 &&
1086
+			    hdmi_use_enci)
1087
+				continue;
1088
+
1089
+			if (freq == MESON_VCLK_HDMI_DDR_148500 &&
1090
+			    dac_freq == vclk_freq)
1091
+				continue;
1092
+
1093
+			if (freq == MESON_VCLK_HDMI_148500 &&
1094
+			    dac_freq != vclk_freq)
1095
+				continue;
1096
+			break;
1097
+		}
1098
+	}
1099
+
1100
+	if (!params[freq].pixel_freq) {
1101
+		pr_err("Fatal Error, invalid HDMI vclk freq %d\n", vclk_freq);
8911102 		return;
8921103 	}
8931104 
894
-	meson_vclk_set(priv, params[freq].pll_base_freq,
1105
+	meson_vclk_set(priv, params[freq].pll_freq,
8951106 		       params[freq].pll_od1, params[freq].pll_od2,
8961107 		       params[freq].pll_od3, params[freq].vid_pll_div,
8971108 		       params[freq].vclk_div, hdmi_tx_div, venc_div,
898
-		       hdmi_use_enci);
1109
+		       hdmi_use_enci, vic_alternate_clock);
8991110 }
9001111 EXPORT_SYMBOL_GPL(meson_vclk_setup);