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2024-05-10 cde9070d9970eef1f7ec2360586c802a16230ad8 
 kernel/drivers/gpu/drm/amd/include/atomfirmware.h
....@@ -177,9 +177,10 @@
177177   VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A,
178178 };
179179 
180
-enum atom_dgpu_vram_type{
180
+enum atom_dgpu_vram_type {
181181   ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50,
182
-  ATOM_DGPU_VRAM_TYPE_HBM   = 0x60,
182
+  ATOM_DGPU_VRAM_TYPE_HBM2  = 0x60,
183
+  ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70,
183184 };
184185 
185186 enum atom_dp_vs_preemph_def{
....@@ -491,9 +492,13 @@
491492 /* Total 32bit cap indication */
492493 enum atombios_firmware_capability
493494 {
494
-  ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
495
-  ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION  = 0x00000002,
496
-  ATOM_FIRMWARE_CAP_WMI_SUPPORT  = 0x00000040,
495
+	ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
496
+	ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION  = 0x00000002,
497
+	ATOM_FIRMWARE_CAP_WMI_SUPPORT  = 0x00000040,
498
+	ATOM_FIRMWARE_CAP_HWEMU_ENABLE  = 0x00000080,
499
+	ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100,
500
+	ATOM_FIRMWARE_CAP_SRAM_ECC      = 0x00000200,
501
+	ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING  = 0x00000400,
497502 };
498503 
499504 enum atom_cooling_solution_id{
....@@ -526,6 +531,71 @@
526531   uint16_t bootup_mvpp_mv;
527532   uint32_t zfbstartaddrin16mb;
528533   uint32_t reserved2[3];
534
+};
535
+
536
+struct atom_firmware_info_v3_3
537
+{
538
+  struct atom_common_table_header table_header;
539
+  uint32_t firmware_revision;
540
+  uint32_t bootup_sclk_in10khz;
541
+  uint32_t bootup_mclk_in10khz;
542
+  uint32_t firmware_capability;             // enum atombios_firmware_capability
543
+  uint32_t main_call_parser_entry;          /* direct address of main parser call in VBIOS binary. */
544
+  uint32_t bios_scratch_reg_startaddr;      // 1st bios scratch register dword address
545
+  uint16_t bootup_vddc_mv;
546
+  uint16_t bootup_vddci_mv;
547
+  uint16_t bootup_mvddc_mv;
548
+  uint16_t bootup_vddgfx_mv;
549
+  uint8_t  mem_module_id;
550
+  uint8_t  coolingsolution_id;              /*0: Air cooling; 1: Liquid cooling ... */
551
+  uint8_t  reserved1[2];
552
+  uint32_t mc_baseaddr_high;
553
+  uint32_t mc_baseaddr_low;
554
+  uint8_t  board_i2c_feature_id;            // enum of atom_board_i2c_feature_id_def
555
+  uint8_t  board_i2c_feature_gpio_id;       // i2c id find in gpio_lut data table gpio_id
556
+  uint8_t  board_i2c_feature_slave_addr;
557
+  uint8_t  reserved3;
558
+  uint16_t bootup_mvddq_mv;
559
+  uint16_t bootup_mvpp_mv;
560
+  uint32_t zfbstartaddrin16mb;
561
+  uint32_t pplib_pptable_id;                // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
562
+  uint32_t reserved2[2];
563
+};
564
+
565
+struct atom_firmware_info_v3_4 {
566
+	struct atom_common_table_header table_header;
567
+	uint32_t firmware_revision;
568
+	uint32_t bootup_sclk_in10khz;
569
+	uint32_t bootup_mclk_in10khz;
570
+	uint32_t firmware_capability;             // enum atombios_firmware_capability
571
+	uint32_t main_call_parser_entry;          /* direct address of main parser call in VBIOS binary. */
572
+	uint32_t bios_scratch_reg_startaddr;      // 1st bios scratch register dword address
573
+	uint16_t bootup_vddc_mv;
574
+	uint16_t bootup_vddci_mv;
575
+	uint16_t bootup_mvddc_mv;
576
+	uint16_t bootup_vddgfx_mv;
577
+	uint8_t  mem_module_id;
578
+	uint8_t  coolingsolution_id;              /*0: Air cooling; 1: Liquid cooling ... */
579
+	uint8_t  reserved1[2];
580
+	uint32_t mc_baseaddr_high;
581
+	uint32_t mc_baseaddr_low;
582
+	uint8_t  board_i2c_feature_id;            // enum of atom_board_i2c_feature_id_def
583
+	uint8_t  board_i2c_feature_gpio_id;       // i2c id find in gpio_lut data table gpio_id
584
+	uint8_t  board_i2c_feature_slave_addr;
585
+	uint8_t  reserved3;
586
+	uint16_t bootup_mvddq_mv;
587
+	uint16_t bootup_mvpp_mv;
588
+	uint32_t zfbstartaddrin16mb;
589
+	uint32_t pplib_pptable_id;                // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
590
+	uint32_t mvdd_ratio;                      // mvdd_raio = (real mvdd in power rail)*1000/(mvdd_output_from_svi2)
591
+	uint16_t hw_bootup_vddgfx_mv;             // hw default vddgfx voltage level decide by board strap
592
+	uint16_t hw_bootup_vddc_mv;               // hw default vddc voltage level decide by board strap
593
+	uint16_t hw_bootup_mvddc_mv;              // hw default mvddc voltage level decide by board strap
594
+	uint16_t hw_bootup_vddci_mv;              // hw default vddci voltage level decide by board strap
595
+	uint32_t maco_pwrlimit_mw;                // bomaco mode power limit in unit of m-watt
596
+	uint32_t usb_pwrlimit_mw;                 // power limit when USB is enable in unit of m-watt
597
+	uint32_t fw_reserved_size_in_kb;          // VBIOS reserved extra fw size in unit of kb.
598
+	uint32_t reserved[5];
529599 };
530600 
531601 /* 
....@@ -686,6 +756,7 @@
686756   ATOM_ENCODER_CAP_RECORD_HBR2_EN               =0x02,         // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 
687757   ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN          =0x04,         // HDMI2.0 6Gbps enable or not. 
688758   ATOM_ENCODER_CAP_RECORD_HBR3_EN               =0x08,         // DP1.3 HBR3 is supported by board. 
759
+  ATOM_ENCODER_CAP_RECORD_USB_C_TYPE            =0x100,        // the DP connector is a USB-C type.
689760 };
690761 
691762 struct  atom_encoder_caps_record
....@@ -870,7 +941,6 @@
870941   uint8_t  reserved3[8];
871942 };
872943 
873
-
874944 struct atom_display_controller_info_v4_2
875945 {
876946   struct  atom_common_table_header  table_header;
....@@ -905,6 +975,59 @@
905975   uint8_t  reserved3[8];
906976 };
907977 
978
+struct atom_display_controller_info_v4_4 {
979
+	struct atom_common_table_header table_header;
980
+	uint32_t display_caps;
981
+	uint32_t bootup_dispclk_10khz;
982
+	uint16_t dce_refclk_10khz;
983
+	uint16_t i2c_engine_refclk_10khz;
984
+	uint16_t dvi_ss_percentage;	 // in unit of 0.001%
985
+	uint16_t dvi_ss_rate_10hz;
986
+	uint16_t hdmi_ss_percentage;	 // in unit of 0.001%
987
+	uint16_t hdmi_ss_rate_10hz;
988
+	uint16_t dp_ss_percentage;	 // in unit of 0.001%
989
+	uint16_t dp_ss_rate_10hz;
990
+	uint8_t dvi_ss_mode;		 // enum of atom_spread_spectrum_mode
991
+	uint8_t hdmi_ss_mode;		 // enum of atom_spread_spectrum_mode
992
+	uint8_t dp_ss_mode;		 // enum of atom_spread_spectrum_mode
993
+	uint8_t ss_reserved;
994
+	uint8_t dfp_hardcode_mode_num;	 // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
995
+	uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
996
+	uint8_t vga_hardcode_mode_num;	 // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
997
+	uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
998
+	uint16_t dpphy_refclk_10khz;
999
+	uint16_t hw_chip_id;
1000
+	uint8_t dcnip_min_ver;
1001
+	uint8_t dcnip_max_ver;
1002
+	uint8_t max_disp_pipe_num;
1003
+	uint8_t max_vbios_active_disp_pipum;
1004
+	uint8_t max_ppll_num;
1005
+	uint8_t max_disp_phy_num;
1006
+	uint8_t max_aux_pairs;
1007
+	uint8_t remotedisplayconfig;
1008
+	uint32_t dispclk_pll_vco_freq;
1009
+	uint32_t dp_ref_clk_freq;
1010
+	uint32_t max_mclk_chg_lat;	 // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us)
1011
+	uint32_t max_sr_exit_lat;	 // Worst case memory self refresh exit time, units of 100ns of ns (0.1us)
1012
+	uint32_t max_sr_enter_exit_lat;	 // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us)
1013
+	uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx
1014
+	uint16_t dc_golden_table_ver;
1015
+	uint32_t reserved3[3];
1016
+};
1017
+
1018
+struct atom_dc_golden_table_v1
1019
+{
1020
+	uint32_t aux_dphy_rx_control0_val;
1021
+	uint32_t aux_dphy_tx_control_val;
1022
+	uint32_t aux_dphy_rx_control1_val;
1023
+	uint32_t dc_gpio_aux_ctrl_0_val;
1024
+	uint32_t dc_gpio_aux_ctrl_1_val;
1025
+	uint32_t dc_gpio_aux_ctrl_2_val;
1026
+	uint32_t dc_gpio_aux_ctrl_3_val;
1027
+	uint32_t dc_gpio_aux_ctrl_4_val;
1028
+	uint32_t dc_gpio_aux_ctrl_5_val;
1029
+	uint32_t reserved[23];
1030
+};
9081031 
9091032 enum dce_info_caps_def
9101033 {
....@@ -937,11 +1060,13 @@
9371060 };
9381061 
9391062 //usCaps
940
-enum ext_display_path_cap_def
941
-{
942
-  EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE               =0x0001,
943
-  EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN             =0x0002,
944
-  EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK              =0x007C,           
1063
+enum ext_display_path_cap_def {
1064
+	EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE =           0x0001,
1065
+	EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN =         0x0002,
1066
+	EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK =          0x007C,
1067
+	EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 =      (0x01 << 2), //PI redriver chip
1068
+	EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x02 << 2), //TI retimer chip
1069
+	EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 =    (0x03 << 2)  //Parade DP->HDMI recoverter chip
9451070 };
9461071 
9471072 struct atom_external_display_connection_info
....@@ -1043,6 +1168,35 @@
10431168   uint8_t margin_deemph_lane0__deemph_sel_val;         
10441169 };
10451170 
1171
+struct atom_DCN_dpphy_dvihdmi_tuningset
1172
+{
1173
+  uint32_t max_symclk_in10khz;
1174
+  uint8_t  encoder_mode;           //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1175
+  uint8_t  phy_sel;                //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 
1176
+  uint8_t  tx_eq_main;             // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1177
+  uint8_t  tx_eq_pre;              // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1178
+  uint8_t  tx_eq_post;             // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1179
+  uint8_t  reserved1;
1180
+  uint8_t  tx_vboost_lvl;          // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1181
+  uint8_t  reserved2;
1182
+};
1183
+
1184
+struct atom_DCN_dpphy_dp_setting{
1185
+  uint8_t dp_vs_pemph_level;       //enum of atom_dp_vs_preemph_def
1186
+  uint8_t tx_eq_main;             // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1187
+  uint8_t tx_eq_pre;              // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1188
+  uint8_t tx_eq_post;             // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1189
+  uint8_t tx_vboost_lvl;          // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1190
+};
1191
+
1192
+struct atom_DCN_dpphy_dp_tuningset{
1193
+  uint8_t phy_sel;                 // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 
1194
+  uint8_t version;
1195
+  uint16_t table_size;             // size of atom_14nm_dpphy_dp_setting
1196
+  uint16_t reserved;
1197
+  struct atom_DCN_dpphy_dp_setting dptunings[10];
1198
+};
1199
+
10461200 struct atom_i2c_reg_info {
10471201   uint8_t ucI2cRegIndex;
10481202   uint8_t ucI2cRegVal;
....@@ -1105,6 +1259,55 @@
11051259   uint32_t  reserved[66];
11061260 };
11071261 
1262
+struct atom_integrated_system_info_v1_12
1263
+{
1264
+  struct  atom_common_table_header  table_header;
1265
+  uint32_t  vbios_misc;                       //enum of atom_system_vbiosmisc_def
1266
+  uint32_t  gpucapinfo;                       //enum of atom_system_gpucapinf_def   
1267
+  uint32_t  system_config;                    
1268
+  uint32_t  cpucapinfo;
1269
+  uint16_t  gpuclk_ss_percentage;             //unit of 0.001%,   1000 mean 1% 
1270
+  uint16_t  gpuclk_ss_type;
1271
+  uint16_t  lvds_ss_percentage;               //unit of 0.001%,   1000 mean 1%
1272
+  uint16_t  lvds_ss_rate_10hz;
1273
+  uint16_t  hdmi_ss_percentage;               //unit of 0.001%,   1000 mean 1%
1274
+  uint16_t  hdmi_ss_rate_10hz;
1275
+  uint16_t  dvi_ss_percentage;                //unit of 0.001%,   1000 mean 1%
1276
+  uint16_t  dvi_ss_rate_10hz;
1277
+  uint16_t  dpphy_override;                   // bit vector, enum of atom_sysinfo_dpphy_override_def
1278
+  uint16_t  lvds_misc;                        // enum of atom_sys_info_lvds_misc_def
1279
+  uint16_t  backlight_pwm_hz;                 // pwm frequency in hz
1280
+  uint8_t   memorytype;                       // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1281
+  uint8_t   umachannelnumber;                 // number of memory channels
1282
+  uint8_t   pwr_on_digon_to_de;               // all pwr sequence numbers below are in uint of 4ms //
1283
+  uint8_t   pwr_on_de_to_vary_bl;
1284
+  uint8_t   pwr_down_vary_bloff_to_de;
1285
+  uint8_t   pwr_down_de_to_digoff;
1286
+  uint8_t   pwr_off_delay;
1287
+  uint8_t   pwr_on_vary_bl_to_blon;
1288
+  uint8_t   pwr_down_bloff_to_vary_bloff;
1289
+  uint8_t   min_allowed_bl_level;
1290
+  uint8_t   htc_hyst_limit;
1291
+  uint8_t   htc_tmp_limit;
1292
+  uint8_t   reserved1;
1293
+  uint8_t   reserved2;
1294
+  struct atom_external_display_connection_info extdispconninfo;
1295
+  struct atom_DCN_dpphy_dvihdmi_tuningset  TMDS_tuningset;
1296
+  struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK5_tuningset;
1297
+  struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK8_tuningset;
1298
+  struct atom_DCN_dpphy_dp_tuningset rbr_tuningset;        // rbr 1.62G dp tuning set
1299
+  struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset;   // HBR3 dp tuning set  
1300
+  struct atom_camera_data  camera_info;
1301
+  struct atom_hdmi_retimer_redriver_set dp0_retimer_set;   //for DP0
1302
+  struct atom_hdmi_retimer_redriver_set dp1_retimer_set;   //for DP1
1303
+  struct atom_hdmi_retimer_redriver_set dp2_retimer_set;   //for DP2
1304
+  struct atom_hdmi_retimer_redriver_set dp3_retimer_set;   //for DP3
1305
+  struct atom_DCN_dpphy_dp_tuningset hbr_tuningset;    //hbr 2.7G dp tuning set
1306
+  struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset;   //hbr2 5.4G dp turnig set
1307
+  struct atom_DCN_dpphy_dp_tuningset edp_tunings;       //edp tuning set  
1308
+  struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK6_tuningset;
1309
+  uint32_t  reserved[63];
1310
+};
11081311 
11091312 // system_config
11101313 enum atom_system_vbiosmisc_def{
....@@ -1226,16 +1429,17 @@
12261429   uint32_t rm21_sram_vmin_value;
12271430 };
12281431 
1229
-struct  atom_gfx_info_v2_4 {
1432
+struct  atom_gfx_info_v2_4
1433
+{
12301434   struct  atom_common_table_header  table_header;
12311435   uint8_t gfxip_min_ver;
12321436   uint8_t gfxip_max_ver;
1233
-  uint8_t gc_num_se;
1234
-  uint8_t max_tile_pipes;
1235
-  uint8_t gc_num_cu_per_sh;
1236
-  uint8_t gc_num_sh_per_se;
1237
-  uint8_t gc_num_rb_per_se;
1238
-  uint8_t gc_num_tccs;
1437
+  uint8_t max_shader_engines;
1438
+  uint8_t reserved;
1439
+  uint8_t max_cu_per_sh;
1440
+  uint8_t max_sh_per_se;
1441
+  uint8_t max_backends_per_se;
1442
+  uint8_t max_texture_channel_caches;
12391443   uint32_t regaddr_cp_dma_src_addr;
12401444   uint32_t regaddr_cp_dma_src_addr_hi;
12411445   uint32_t regaddr_cp_dma_dst_addr;
....@@ -1325,7 +1529,7 @@
13251529   struct   atom_common_table_header  table_header;
13261530   uint8_t  smuip_min_ver;
13271531   uint8_t  smuip_max_ver;
1328
-  uint8_t  smu_rsd1;
1532
+  uint8_t  waflclk_ss_mode;
13291533   uint8_t  gpuclk_ss_mode;
13301534   uint16_t sclk_ss_percentage;
13311535   uint16_t sclk_ss_rate_10hz;
....@@ -1355,7 +1559,10 @@
13551559   uint32_t syspll3_1_vco_freq_10khz;
13561560   uint32_t bootup_fclk_10khz;
13571561   uint32_t bootup_waflclk_10khz;
1358
-  uint32_t reserved[3];
1562
+  uint32_t smu_info_caps;
1563
+  uint16_t waflclk_ss_percentage;    // in unit of 0.001%
1564
+  uint16_t smuinitoffset;
1565
+  uint32_t reserved;
13591566 };
13601567 
13611568 /*
....@@ -1444,6 +1651,622 @@
14441651 	uint8_t padding_vr2[3];
14451652 
14461653 	uint32_t boardreserved[9];
1654
+};
1655
+
1656
+/*
1657
+ ***************************************************************************
1658
+   Data Table smc_dpm_info  structure
1659
+ ***************************************************************************
1660
+ */
1661
+struct atom_smc_dpm_info_v4_3
1662
+{
1663
+  struct   atom_common_table_header  table_header;
1664
+  uint8_t  liquid1_i2c_address;
1665
+  uint8_t  liquid2_i2c_address;
1666
+  uint8_t  vr_i2c_address;
1667
+  uint8_t  plx_i2c_address;
1668
+
1669
+  uint8_t  liquid_i2c_linescl;
1670
+  uint8_t  liquid_i2c_linesda;
1671
+  uint8_t  vr_i2c_linescl;
1672
+  uint8_t  vr_i2c_linesda;
1673
+
1674
+  uint8_t  plx_i2c_linescl;
1675
+  uint8_t  plx_i2c_linesda;
1676
+  uint8_t  vrsensorpresent;
1677
+  uint8_t  liquidsensorpresent;
1678
+
1679
+  uint16_t maxvoltagestepgfx;
1680
+  uint16_t maxvoltagestepsoc;
1681
+
1682
+  uint8_t  vddgfxvrmapping;
1683
+  uint8_t  vddsocvrmapping;
1684
+  uint8_t  vddmem0vrmapping;
1685
+  uint8_t  vddmem1vrmapping;
1686
+
1687
+  uint8_t  gfxulvphasesheddingmask;
1688
+  uint8_t  soculvphasesheddingmask;
1689
+  uint8_t  externalsensorpresent;
1690
+  uint8_t  padding8_v;
1691
+
1692
+  uint16_t gfxmaxcurrent;
1693
+  uint8_t  gfxoffset;
1694
+  uint8_t  padding_telemetrygfx;
1695
+
1696
+  uint16_t socmaxcurrent;
1697
+  uint8_t  socoffset;
1698
+  uint8_t  padding_telemetrysoc;
1699
+
1700
+  uint16_t mem0maxcurrent;
1701
+  uint8_t  mem0offset;
1702
+  uint8_t  padding_telemetrymem0;
1703
+
1704
+  uint16_t mem1maxcurrent;
1705
+  uint8_t  mem1offset;
1706
+  uint8_t  padding_telemetrymem1;
1707
+
1708
+  uint8_t  acdcgpio;
1709
+  uint8_t  acdcpolarity;
1710
+  uint8_t  vr0hotgpio;
1711
+  uint8_t  vr0hotpolarity;
1712
+
1713
+  uint8_t  vr1hotgpio;
1714
+  uint8_t  vr1hotpolarity;
1715
+  uint8_t  padding1;
1716
+  uint8_t  padding2;
1717
+
1718
+  uint8_t  ledpin0;
1719
+  uint8_t  ledpin1;
1720
+  uint8_t  ledpin2;
1721
+  uint8_t  padding8_4;
1722
+
1723
+  uint8_t  pllgfxclkspreadenabled;
1724
+  uint8_t  pllgfxclkspreadpercent;
1725
+  uint16_t pllgfxclkspreadfreq;
1726
+
1727
+  uint8_t uclkspreadenabled;
1728
+  uint8_t uclkspreadpercent;
1729
+  uint16_t uclkspreadfreq;
1730
+
1731
+  uint8_t fclkspreadenabled;
1732
+  uint8_t fclkspreadpercent;
1733
+  uint16_t fclkspreadfreq;
1734
+
1735
+  uint8_t fllgfxclkspreadenabled;
1736
+  uint8_t fllgfxclkspreadpercent;
1737
+  uint16_t fllgfxclkspreadfreq;
1738
+
1739
+  uint32_t boardreserved[10];
1740
+};
1741
+
1742
+struct smudpm_i2ccontrollerconfig_t {
1743
+  uint32_t  enabled;
1744
+  uint32_t  slaveaddress;
1745
+  uint32_t  controllerport;
1746
+  uint32_t  controllername;
1747
+  uint32_t  thermalthrottler;
1748
+  uint32_t  i2cprotocol;
1749
+  uint32_t  i2cspeed;
1750
+};
1751
+
1752
+struct atom_smc_dpm_info_v4_4
1753
+{
1754
+  struct   atom_common_table_header  table_header;
1755
+  uint32_t  i2c_padding[3];
1756
+
1757
+  uint16_t maxvoltagestepgfx;
1758
+  uint16_t maxvoltagestepsoc;
1759
+
1760
+  uint8_t  vddgfxvrmapping;
1761
+  uint8_t  vddsocvrmapping;
1762
+  uint8_t  vddmem0vrmapping;
1763
+  uint8_t  vddmem1vrmapping;
1764
+
1765
+  uint8_t  gfxulvphasesheddingmask;
1766
+  uint8_t  soculvphasesheddingmask;
1767
+  uint8_t  externalsensorpresent;
1768
+  uint8_t  padding8_v;
1769
+
1770
+  uint16_t gfxmaxcurrent;
1771
+  uint8_t  gfxoffset;
1772
+  uint8_t  padding_telemetrygfx;
1773
+
1774
+  uint16_t socmaxcurrent;
1775
+  uint8_t  socoffset;
1776
+  uint8_t  padding_telemetrysoc;
1777
+
1778
+  uint16_t mem0maxcurrent;
1779
+  uint8_t  mem0offset;
1780
+  uint8_t  padding_telemetrymem0;
1781
+
1782
+  uint16_t mem1maxcurrent;
1783
+  uint8_t  mem1offset;
1784
+  uint8_t  padding_telemetrymem1;
1785
+
1786
+
1787
+  uint8_t  acdcgpio;
1788
+  uint8_t  acdcpolarity;
1789
+  uint8_t  vr0hotgpio;
1790
+  uint8_t  vr0hotpolarity;
1791
+
1792
+  uint8_t  vr1hotgpio;
1793
+  uint8_t  vr1hotpolarity;
1794
+  uint8_t  padding1;
1795
+  uint8_t  padding2;
1796
+
1797
+
1798
+  uint8_t  ledpin0;
1799
+  uint8_t  ledpin1;
1800
+  uint8_t  ledpin2;
1801
+  uint8_t  padding8_4;
1802
+
1803
+
1804
+  uint8_t  pllgfxclkspreadenabled;
1805
+  uint8_t  pllgfxclkspreadpercent;
1806
+  uint16_t pllgfxclkspreadfreq;
1807
+
1808
+
1809
+  uint8_t  uclkspreadenabled;
1810
+  uint8_t  uclkspreadpercent;
1811
+  uint16_t uclkspreadfreq;
1812
+
1813
+
1814
+  uint8_t  fclkspreadenabled;
1815
+  uint8_t  fclkspreadpercent;
1816
+  uint16_t fclkspreadfreq;
1817
+
1818
+
1819
+  uint8_t  fllgfxclkspreadenabled;
1820
+  uint8_t  fllgfxclkspreadpercent;
1821
+  uint16_t fllgfxclkspreadfreq;
1822
+
1823
+
1824
+  struct smudpm_i2ccontrollerconfig_t  i2ccontrollers[7];
1825
+
1826
+
1827
+  uint32_t boardreserved[10];
1828
+};
1829
+
1830
+enum smudpm_v4_5_i2ccontrollername_e{
1831
+    SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0,
1832
+    SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC,
1833
+    SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI,
1834
+    SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD,
1835
+    SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0,
1836
+    SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1,
1837
+    SMC_V4_5_I2C_CONTROLLER_NAME_PLX,
1838
+    SMC_V4_5_I2C_CONTROLLER_NAME_SPARE,
1839
+    SMC_V4_5_I2C_CONTROLLER_NAME_COUNT,
1840
+};
1841
+
1842
+enum smudpm_v4_5_i2ccontrollerthrottler_e{
1843
+    SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
1844
+    SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX,
1845
+    SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC,
1846
+    SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI,
1847
+    SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD,
1848
+    SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0,
1849
+    SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1,
1850
+    SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX,
1851
+    SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT,
1852
+};
1853
+
1854
+enum smudpm_v4_5_i2ccontrollerprotocol_e{
1855
+    SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0,
1856
+    SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1,
1857
+    SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0,
1858
+    SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1,
1859
+    SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0,
1860
+    SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1,
1861
+    SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT,
1862
+};
1863
+
1864
+struct smudpm_i2c_controller_config_v2
1865
+{
1866
+    uint8_t   Enabled;
1867
+    uint8_t   Speed;
1868
+    uint8_t   Padding[2];
1869
+    uint32_t  SlaveAddress;
1870
+    uint8_t   ControllerPort;
1871
+    uint8_t   ControllerName;
1872
+    uint8_t   ThermalThrotter;
1873
+    uint8_t   I2cProtocol;
1874
+};
1875
+
1876
+struct atom_smc_dpm_info_v4_5
1877
+{
1878
+  struct   atom_common_table_header  table_header;
1879
+    // SECTION: BOARD PARAMETERS
1880
+    // I2C Control
1881
+  struct smudpm_i2c_controller_config_v2  I2cControllers[8];
1882
+
1883
+  // SVI2 Board Parameters
1884
+  uint16_t     MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
1885
+  uint16_t     MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
1886
+
1887
+  uint8_t      VddGfxVrMapping;   // Use VR_MAPPING* bitfields
1888
+  uint8_t      VddSocVrMapping;   // Use VR_MAPPING* bitfields
1889
+  uint8_t      VddMem0VrMapping;  // Use VR_MAPPING* bitfields
1890
+  uint8_t      VddMem1VrMapping;  // Use VR_MAPPING* bitfields
1891
+
1892
+  uint8_t      GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
1893
+  uint8_t      SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
1894
+  uint8_t      ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
1895
+  uint8_t      Padding8_V;
1896
+
1897
+  // Telemetry Settings
1898
+  uint16_t     GfxMaxCurrent;   // in Amps
1899
+  uint8_t      GfxOffset;       // in Amps
1900
+  uint8_t      Padding_TelemetryGfx;
1901
+  uint16_t     SocMaxCurrent;   // in Amps
1902
+  uint8_t      SocOffset;       // in Amps
1903
+  uint8_t      Padding_TelemetrySoc;
1904
+
1905
+  uint16_t     Mem0MaxCurrent;   // in Amps
1906
+  uint8_t      Mem0Offset;       // in Amps
1907
+  uint8_t      Padding_TelemetryMem0;
1908
+
1909
+  uint16_t     Mem1MaxCurrent;   // in Amps
1910
+  uint8_t      Mem1Offset;       // in Amps
1911
+  uint8_t      Padding_TelemetryMem1;
1912
+
1913
+  // GPIO Settings
1914
+  uint8_t      AcDcGpio;        // GPIO pin configured for AC/DC switching
1915
+  uint8_t      AcDcPolarity;    // GPIO polarity for AC/DC switching
1916
+  uint8_t      VR0HotGpio;      // GPIO pin configured for VR0 HOT event
1917
+  uint8_t      VR0HotPolarity;  // GPIO polarity for VR0 HOT event
1918
+
1919
+  uint8_t      VR1HotGpio;      // GPIO pin configured for VR1 HOT event 
1920
+  uint8_t      VR1HotPolarity;  // GPIO polarity for VR1 HOT event 
1921
+  uint8_t      GthrGpio;        // GPIO pin configured for GTHR Event
1922
+  uint8_t      GthrPolarity;    // replace GPIO polarity for GTHR
1923
+
1924
+  // LED Display Settings
1925
+  uint8_t      LedPin0;         // GPIO number for LedPin[0]
1926
+  uint8_t      LedPin1;         // GPIO number for LedPin[1]
1927
+  uint8_t      LedPin2;         // GPIO number for LedPin[2]
1928
+  uint8_t      padding8_4;
1929
+
1930
+  // GFXCLK PLL Spread Spectrum
1931
+  uint8_t      PllGfxclkSpreadEnabled;   // on or off
1932
+  uint8_t      PllGfxclkSpreadPercent;   // Q4.4
1933
+  uint16_t     PllGfxclkSpreadFreq;      // kHz
1934
+
1935
+  // GFXCLK DFLL Spread Spectrum
1936
+  uint8_t      DfllGfxclkSpreadEnabled;   // on or off
1937
+  uint8_t      DfllGfxclkSpreadPercent;   // Q4.4
1938
+  uint16_t     DfllGfxclkSpreadFreq;      // kHz
1939
+
1940
+  // UCLK Spread Spectrum
1941
+  uint8_t      UclkSpreadEnabled;   // on or off
1942
+  uint8_t      UclkSpreadPercent;   // Q4.4
1943
+  uint16_t     UclkSpreadFreq;      // kHz
1944
+
1945
+  // SOCCLK Spread Spectrum
1946
+  uint8_t      SoclkSpreadEnabled;   // on or off
1947
+  uint8_t      SocclkSpreadPercent;   // Q4.4
1948
+  uint16_t     SocclkSpreadFreq;      // kHz
1949
+
1950
+  // Total board power
1951
+  uint16_t     TotalBoardPower;     //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
1952
+  uint16_t     BoardPadding; 
1953
+
1954
+  // Mvdd Svi2 Div Ratio Setting
1955
+  uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
1956
+  
1957
+  uint32_t     BoardReserved[9];
1958
+
1959
+};
1960
+
1961
+struct atom_smc_dpm_info_v4_6
1962
+{
1963
+  struct   atom_common_table_header  table_header;
1964
+  // section: board parameters
1965
+  uint32_t     i2c_padding[3];   // old i2c control are moved to new area
1966
+
1967
+  uint16_t     maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
1968
+  uint16_t     maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
1969
+
1970
+  uint8_t      vddgfxvrmapping;     // use vr_mapping* bitfields
1971
+  uint8_t      vddsocvrmapping;     // use vr_mapping* bitfields
1972
+  uint8_t      vddmemvrmapping;     // use vr_mapping* bitfields
1973
+  uint8_t      boardvrmapping;      // use vr_mapping* bitfields
1974
+
1975
+  uint8_t      gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode
1976
+  uint8_t      externalsensorpresent; // external rdi connected to tmon (aka temp in)
1977
+  uint8_t      padding8_v[2];
1978
+
1979
+  // telemetry settings
1980
+  uint16_t     gfxmaxcurrent;   // in amps
1981
+  uint8_t      gfxoffset;       // in amps
1982
+  uint8_t      padding_telemetrygfx;
1983
+
1984
+  uint16_t     socmaxcurrent;   // in amps
1985
+  uint8_t      socoffset;       // in amps
1986
+  uint8_t      padding_telemetrysoc;
1987
+
1988
+  uint16_t     memmaxcurrent;   // in amps
1989
+  uint8_t      memoffset;       // in amps
1990
+  uint8_t      padding_telemetrymem;
1991
+
1992
+  uint16_t     boardmaxcurrent;   // in amps
1993
+  uint8_t      boardoffset;       // in amps
1994
+  uint8_t      padding_telemetryboardinput;
1995
+
1996
+  // gpio settings
1997
+  uint8_t      vr0hotgpio;      // gpio pin configured for vr0 hot event
1998
+  uint8_t      vr0hotpolarity;  // gpio polarity for vr0 hot event
1999
+  uint8_t      vr1hotgpio;      // gpio pin configured for vr1 hot event
2000
+  uint8_t      vr1hotpolarity;  // gpio polarity for vr1 hot event
2001
+
2002
+ // gfxclk pll spread spectrum
2003
+  uint8_t	   pllgfxclkspreadenabled;	// on or off
2004
+  uint8_t	   pllgfxclkspreadpercent;	// q4.4
2005
+  uint16_t	   pllgfxclkspreadfreq;		// khz
2006
+
2007
+ // uclk spread spectrum
2008
+  uint8_t	   uclkspreadenabled;   // on or off
2009
+  uint8_t	   uclkspreadpercent;   // q4.4
2010
+  uint16_t	   uclkspreadfreq;	   // khz
2011
+
2012
+ // fclk spread spectrum
2013
+  uint8_t	   fclkspreadenabled;   // on or off
2014
+  uint8_t	   fclkspreadpercent;   // q4.4
2015
+  uint16_t	   fclkspreadfreq;	   // khz
2016
+
2017
+
2018
+  // gfxclk fll spread spectrum
2019
+  uint8_t      fllgfxclkspreadenabled;   // on or off
2020
+  uint8_t      fllgfxclkspreadpercent;   // q4.4
2021
+  uint16_t     fllgfxclkspreadfreq;      // khz
2022
+
2023
+  // i2c controller structure
2024
+  struct smudpm_i2c_controller_config_v2 i2ccontrollers[8];
2025
+
2026
+  // memory section
2027
+  uint32_t	 memorychannelenabled; // for dram use only, max 32 channels enabled bit mask.
2028
+
2029
+  uint8_t 	 drambitwidth; // for dram use only.  see dram bit width type defines
2030
+  uint8_t 	 paddingmem[3];
2031
+
2032
+	// total board power
2033
+  uint16_t	 totalboardpower;	  //only needed for tcp estimated case, where tcp = tgp+total board power
2034
+  uint16_t	 boardpadding;
2035
+
2036
+	// section: xgmi training
2037
+  uint8_t 	 xgmilinkspeed[4];
2038
+  uint8_t 	 xgmilinkwidth[4];
2039
+
2040
+  uint16_t	 xgmifclkfreq[4];
2041
+  uint16_t	 xgmisocvoltage[4];
2042
+
2043
+  // reserved
2044
+  uint32_t   boardreserved[10];
2045
+};
2046
+
2047
+struct atom_smc_dpm_info_v4_7
2048
+{
2049
+  struct   atom_common_table_header  table_header;
2050
+    // SECTION: BOARD PARAMETERS
2051
+    // I2C Control
2052
+  struct smudpm_i2c_controller_config_v2  I2cControllers[8];
2053
+
2054
+  // SVI2 Board Parameters
2055
+  uint16_t     MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2056
+  uint16_t     MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2057
+
2058
+  uint8_t      VddGfxVrMapping;   // Use VR_MAPPING* bitfields
2059
+  uint8_t      VddSocVrMapping;   // Use VR_MAPPING* bitfields
2060
+  uint8_t      VddMem0VrMapping;  // Use VR_MAPPING* bitfields
2061
+  uint8_t      VddMem1VrMapping;  // Use VR_MAPPING* bitfields
2062
+
2063
+  uint8_t      GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2064
+  uint8_t      SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2065
+  uint8_t      ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2066
+  uint8_t      Padding8_V;
2067
+
2068
+  // Telemetry Settings
2069
+  uint16_t     GfxMaxCurrent;   // in Amps
2070
+  uint8_t      GfxOffset;       // in Amps
2071
+  uint8_t      Padding_TelemetryGfx;
2072
+  uint16_t     SocMaxCurrent;   // in Amps
2073
+  uint8_t      SocOffset;       // in Amps
2074
+  uint8_t      Padding_TelemetrySoc;
2075
+
2076
+  uint16_t     Mem0MaxCurrent;   // in Amps
2077
+  uint8_t      Mem0Offset;       // in Amps
2078
+  uint8_t      Padding_TelemetryMem0;
2079
+
2080
+  uint16_t     Mem1MaxCurrent;   // in Amps
2081
+  uint8_t      Mem1Offset;       // in Amps
2082
+  uint8_t      Padding_TelemetryMem1;
2083
+
2084
+  // GPIO Settings
2085
+  uint8_t      AcDcGpio;        // GPIO pin configured for AC/DC switching
2086
+  uint8_t      AcDcPolarity;    // GPIO polarity for AC/DC switching
2087
+  uint8_t      VR0HotGpio;      // GPIO pin configured for VR0 HOT event
2088
+  uint8_t      VR0HotPolarity;  // GPIO polarity for VR0 HOT event
2089
+
2090
+  uint8_t      VR1HotGpio;      // GPIO pin configured for VR1 HOT event
2091
+  uint8_t      VR1HotPolarity;  // GPIO polarity for VR1 HOT event
2092
+  uint8_t      GthrGpio;        // GPIO pin configured for GTHR Event
2093
+  uint8_t      GthrPolarity;    // replace GPIO polarity for GTHR
2094
+
2095
+  // LED Display Settings
2096
+  uint8_t      LedPin0;         // GPIO number for LedPin[0]
2097
+  uint8_t      LedPin1;         // GPIO number for LedPin[1]
2098
+  uint8_t      LedPin2;         // GPIO number for LedPin[2]
2099
+  uint8_t      padding8_4;
2100
+
2101
+  // GFXCLK PLL Spread Spectrum
2102
+  uint8_t      PllGfxclkSpreadEnabled;   // on or off
2103
+  uint8_t      PllGfxclkSpreadPercent;   // Q4.4
2104
+  uint16_t     PllGfxclkSpreadFreq;      // kHz
2105
+
2106
+  // GFXCLK DFLL Spread Spectrum
2107
+  uint8_t      DfllGfxclkSpreadEnabled;   // on or off
2108
+  uint8_t      DfllGfxclkSpreadPercent;   // Q4.4
2109
+  uint16_t     DfllGfxclkSpreadFreq;      // kHz
2110
+
2111
+  // UCLK Spread Spectrum
2112
+  uint8_t      UclkSpreadEnabled;   // on or off
2113
+  uint8_t      UclkSpreadPercent;   // Q4.4
2114
+  uint16_t     UclkSpreadFreq;      // kHz
2115
+
2116
+  // SOCCLK Spread Spectrum
2117
+  uint8_t      SoclkSpreadEnabled;   // on or off
2118
+  uint8_t      SocclkSpreadPercent;   // Q4.4
2119
+  uint16_t     SocclkSpreadFreq;      // kHz
2120
+
2121
+  // Total board power
2122
+  uint16_t     TotalBoardPower;     //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
2123
+  uint16_t     BoardPadding;
2124
+
2125
+  // Mvdd Svi2 Div Ratio Setting
2126
+  uint32_t     MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
2127
+
2128
+  // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
2129
+  uint8_t      GpioI2cScl;          // Serial Clock
2130
+  uint8_t      GpioI2cSda;          // Serial Data
2131
+  uint16_t     GpioPadding;
2132
+
2133
+  // Additional LED Display Settings
2134
+  uint8_t      LedPin3;         // GPIO number for LedPin[3] - PCIE GEN Speed
2135
+  uint8_t      LedPin4;         // GPIO number for LedPin[4] - PMFW Error Status
2136
+  uint16_t     LedEnableMask;
2137
+
2138
+  // Power Limit Scalars
2139
+  uint8_t      PowerLimitScalar[4];    //[PPT_THROTTLER_COUNT]
2140
+
2141
+  uint8_t      MvddUlvPhaseSheddingMask;
2142
+  uint8_t      VddciUlvPhaseSheddingMask;
2143
+  uint8_t      Padding8_Psi1;
2144
+  uint8_t      Padding8_Psi2;
2145
+
2146
+  uint32_t     BoardReserved[5];
2147
+};
2148
+
2149
+struct smudpm_i2c_controller_config_v3
2150
+{
2151
+  uint8_t   Enabled;
2152
+  uint8_t   Speed;
2153
+  uint8_t   SlaveAddress;
2154
+  uint8_t   ControllerPort;
2155
+  uint8_t   ControllerName;
2156
+  uint8_t   ThermalThrotter;
2157
+  uint8_t   I2cProtocol;
2158
+  uint8_t   PaddingConfig;
2159
+};
2160
+
2161
+struct atom_smc_dpm_info_v4_9
2162
+{
2163
+  struct   atom_common_table_header  table_header;
2164
+
2165
+  //SECTION: Gaming Clocks
2166
+  //uint32_t     GamingClk[6];
2167
+
2168
+  // SECTION: I2C Control
2169
+  struct smudpm_i2c_controller_config_v3  I2cControllers[16];     
2170
+
2171
+  uint8_t      GpioScl;  // GPIO Number for SCL Line, used only for CKSVII2C1
2172
+  uint8_t      GpioSda;  // GPIO Number for SDA Line, used only for CKSVII2C1
2173
+  uint8_t      FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off
2174
+  uint8_t      I2cSpare;
2175
+
2176
+  // SECTION: SVI2 Board Parameters
2177
+  uint8_t      VddGfxVrMapping;   // Use VR_MAPPING* bitfields
2178
+  uint8_t      VddSocVrMapping;   // Use VR_MAPPING* bitfields
2179
+  uint8_t      VddMem0VrMapping;  // Use VR_MAPPING* bitfields
2180
+  uint8_t      VddMem1VrMapping;  // Use VR_MAPPING* bitfields
2181
+
2182
+  uint8_t      GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2183
+  uint8_t      SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2184
+  uint8_t      VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2185
+  uint8_t      MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2186
+
2187
+  // SECTION: Telemetry Settings
2188
+  uint16_t     GfxMaxCurrent;   // in Amps
2189
+  uint8_t      GfxOffset;       // in Amps
2190
+  uint8_t      Padding_TelemetryGfx;
2191
+
2192
+  uint16_t     SocMaxCurrent;   // in Amps
2193
+  uint8_t      SocOffset;       // in Amps
2194
+  uint8_t      Padding_TelemetrySoc;
2195
+
2196
+  uint16_t     Mem0MaxCurrent;   // in Amps
2197
+  uint8_t      Mem0Offset;       // in Amps
2198
+  uint8_t      Padding_TelemetryMem0;
2199
+  
2200
+  uint16_t     Mem1MaxCurrent;   // in Amps
2201
+  uint8_t      Mem1Offset;       // in Amps
2202
+  uint8_t      Padding_TelemetryMem1;
2203
+
2204
+  uint32_t     MvddRatio; // This is used for MVDD  Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)
2205
+  
2206
+  // SECTION: GPIO Settings
2207
+  uint8_t      AcDcGpio;        // GPIO pin configured for AC/DC switching
2208
+  uint8_t      AcDcPolarity;    // GPIO polarity for AC/DC switching
2209
+  uint8_t      VR0HotGpio;      // GPIO pin configured for VR0 HOT event
2210
+  uint8_t      VR0HotPolarity;  // GPIO polarity for VR0 HOT event
2211
+
2212
+  uint8_t      VR1HotGpio;      // GPIO pin configured for VR1 HOT event 
2213
+  uint8_t      VR1HotPolarity;  // GPIO polarity for VR1 HOT event 
2214
+  uint8_t      GthrGpio;        // GPIO pin configured for GTHR Event
2215
+  uint8_t      GthrPolarity;    // replace GPIO polarity for GTHR
2216
+
2217
+  // LED Display Settings
2218
+  uint8_t      LedPin0;         // GPIO number for LedPin[0]
2219
+  uint8_t      LedPin1;         // GPIO number for LedPin[1]
2220
+  uint8_t      LedPin2;         // GPIO number for LedPin[2]
2221
+  uint8_t      LedEnableMask;
2222
+
2223
+  uint8_t      LedPcie;        // GPIO number for PCIE results
2224
+  uint8_t      LedError;       // GPIO number for Error Cases
2225
+  uint8_t      LedSpare1[2];
2226
+
2227
+  // SECTION: Clock Spread Spectrum
2228
+  
2229
+  // GFXCLK PLL Spread Spectrum
2230
+  uint8_t      PllGfxclkSpreadEnabled;   // on or off
2231
+  uint8_t      PllGfxclkSpreadPercent;   // Q4.4
2232
+  uint16_t     PllGfxclkSpreadFreq;      // kHz
2233
+
2234
+  // GFXCLK DFLL Spread Spectrum
2235
+  uint8_t      DfllGfxclkSpreadEnabled;   // on or off
2236
+  uint8_t      DfllGfxclkSpreadPercent;   // Q4.4
2237
+  uint16_t     DfllGfxclkSpreadFreq;      // kHz
2238
+  
2239
+  // UCLK Spread Spectrum
2240
+  uint8_t      UclkSpreadEnabled;   // on or off
2241
+  uint8_t      UclkSpreadPercent;   // Q4.4
2242
+  uint16_t     UclkSpreadFreq;      // kHz
2243
+
2244
+  // FCLK Spread Spectrum
2245
+  uint8_t      FclkSpreadEnabled;   // on or off
2246
+  uint8_t      FclkSpreadPercent;   // Q4.4
2247
+  uint16_t     FclkSpreadFreq;      // kHz
2248
+  
2249
+  // Section: Memory Config
2250
+  uint32_t     MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 
2251
+  
2252
+  uint8_t      DramBitWidth; // For DRAM use only.  See Dram Bit width type defines
2253
+  uint8_t      PaddingMem1[3];
2254
+
2255
+  // Section: Total Board Power
2256
+  uint16_t     TotalBoardPower;     //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
2257
+  uint16_t     BoardPowerPadding; 
2258
+  
2259
+  // SECTION: XGMI Training
2260
+  uint8_t      XgmiLinkSpeed   [4];
2261
+  uint8_t      XgmiLinkWidth   [4];
2262
+
2263
+  uint16_t     XgmiFclkFreq    [4];
2264
+  uint16_t     XgmiSocVoltage  [4];
2265
+
2266
+  // SECTION: Board Reserved
2267
+
2268
+  uint32_t     BoardReserved[16];
2269
+
14472270 };
14482271 
14492272 /* 
....@@ -1603,20 +2426,69 @@
16032426   uint32_t mem_refclk_10khz;
16042427 };
16052428 
2429
+// umc_info.umc_config
2430
+enum atom_umc_config_def {
2431
+  UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE  =   0x00000001,
2432
+  UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE      =   0x00000002,
2433
+  UMC_CONFIG__ENABLE_HBM_LANE_REPAIR      =   0x00000004,
2434
+  UMC_CONFIG__ENABLE_BANK_HARVESTING      =   0x00000008,
2435
+  UMC_CONFIG__ENABLE_PHY_REINIT           =   0x00000010,
2436
+  UMC_CONFIG__DISABLE_UCODE_CHKSTATUS     =   0x00000020,
2437
+};
2438
+
2439
+struct atom_umc_info_v3_2
2440
+{
2441
+  struct  atom_common_table_header  table_header;
2442
+  uint32_t ucode_version;
2443
+  uint32_t ucode_rom_startaddr;
2444
+  uint32_t ucode_length;
2445
+  uint16_t umc_reg_init_offset;
2446
+  uint16_t customer_ucode_name_offset;
2447
+  uint16_t mclk_ss_percentage;
2448
+  uint16_t mclk_ss_rate_10hz;
2449
+  uint8_t umcip_min_ver;
2450
+  uint8_t umcip_max_ver;
2451
+  uint8_t vram_type;              //enum of atom_dgpu_vram_type
2452
+  uint8_t umc_config;
2453
+  uint32_t mem_refclk_10khz;
2454
+  uint32_t pstate_uclk_10khz[4];
2455
+  uint16_t umcgoldenoffset;
2456
+  uint16_t densitygoldenoffset;
2457
+};
2458
+
2459
+struct atom_umc_info_v3_3
2460
+{
2461
+  struct  atom_common_table_header  table_header;
2462
+  uint32_t ucode_reserved;
2463
+  uint32_t ucode_rom_startaddr;
2464
+  uint32_t ucode_length;
2465
+  uint16_t umc_reg_init_offset;
2466
+  uint16_t customer_ucode_name_offset;
2467
+  uint16_t mclk_ss_percentage;
2468
+  uint16_t mclk_ss_rate_10hz;
2469
+  uint8_t umcip_min_ver;
2470
+  uint8_t umcip_max_ver;
2471
+  uint8_t vram_type;              //enum of atom_dgpu_vram_type
2472
+  uint8_t umc_config;
2473
+  uint32_t mem_refclk_10khz;
2474
+  uint32_t pstate_uclk_10khz[4];
2475
+  uint16_t umcgoldenoffset;
2476
+  uint16_t densitygoldenoffset;
2477
+  uint32_t reserved[4];
2478
+};
16062479 
16072480 /* 
16082481   ***************************************************************************
16092482     Data Table vram_info  structure
16102483   ***************************************************************************
16112484 */
1612
-struct atom_vram_module_v9
1613
-{
2485
+struct atom_vram_module_v9 {
16142486   // Design Specific Values
16152487   uint32_t  memory_size;                   // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
1616
-  uint32_t  channel_enable;                // for 32 channel ASIC usage
1617
-  uint32_t  umcch_addrcfg;
1618
-  uint32_t  umcch_addrsel;
1619
-  uint32_t  umcch_colsel;
2488
+  uint32_t  channel_enable;                // bit vector, each bit indicate specific channel enable or not
2489
+  uint32_t  max_mem_clk;                   // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
2490
+  uint16_t  reserved[3];
2491
+  uint16_t  mem_voltage;                   // mem_voltage
16202492   uint16_t  vram_module_size;              // Size of atom_vram_module_v9
16212493   uint8_t   ext_memory_id;                 // Current memory module ID
16222494   uint8_t   memory_type;                   // enum of atom_dgpu_vram_type
....@@ -1626,22 +2498,24 @@
16262498   uint8_t   tunningset_id;                 // MC phy registers set per. 
16272499   uint8_t   vender_rev_id;                 // [7:4] Revision, [3:0] Vendor code
16282500   uint8_t   refreshrate;                   // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
1629
-  uint16_t  vram_rsd2;                     // reserved
2501
+  uint8_t   hbm_ven_rev_id;		   // hbm_ven_rev_id
2502
+  uint8_t   vram_rsd2;			   // reserved
16302503   char    dram_pnstring[20];               // part number end with '0'. 
16312504 };
16322505 
1633
-
1634
-struct atom_vram_info_header_v2_3
1635
-{
1636
-  struct   atom_common_table_header  table_header;
2506
+struct atom_vram_info_header_v2_3 {
2507
+  struct   atom_common_table_header table_header;
16372508   uint16_t mem_adjust_tbloffset;                         // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
16382509   uint16_t mem_clk_patch_tbloffset;                      // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
16392510   uint16_t mc_adjust_pertile_tbloffset;                  // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
16402511   uint16_t mc_phyinit_tbloffset;                         // offset of atom_umc_init_reg_block structure for MC phy init set
16412512   uint16_t dram_data_remap_tbloffset;                    // reserved for now
1642
-  uint16_t vram_rsd2[3];
2513
+  uint16_t tmrs_seq_offset;                              // offset of HBM tmrs
2514
+  uint16_t post_ucode_init_offset;                       // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
2515
+  uint16_t vram_rsd2;
16432516   uint8_t  vram_module_num;                              // indicate number of VRAM module
1644
-  uint8_t  vram_rsd1[2];
2517
+  uint8_t  umcip_min_ver;
2518
+  uint8_t  umcip_max_ver;
16452519   uint8_t  mc_phy_tile_num;                              // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
16462520   struct   atom_vram_module_v9  vram_module[16];         // just for allocation, real number of blocks is in ucNumOfVRAMModule;
16472521 };
....@@ -1686,6 +2560,171 @@
16862560   struct atom_umc_reg_setting_data_block umc_reg_setting_list[1];
16872561 };
16882562 
2563
+struct atom_vram_module_v10 {
2564
+  // Design Specific Values
2565
+  uint32_t  memory_size;                   // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
2566
+  uint32_t  channel_enable;                // bit vector, each bit indicate specific channel enable or not
2567
+  uint32_t  max_mem_clk;                   // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
2568
+  uint16_t  reserved[3];
2569
+  uint16_t  mem_voltage;                   // mem_voltage
2570
+  uint16_t  vram_module_size;              // Size of atom_vram_module_v9
2571
+  uint8_t   ext_memory_id;                 // Current memory module ID
2572
+  uint8_t   memory_type;                   // enum of atom_dgpu_vram_type
2573
+  uint8_t   channel_num;                   // Number of mem. channels supported in this module
2574
+  uint8_t   channel_width;                 // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2575
+  uint8_t   density;                       // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2576
+  uint8_t   tunningset_id;                 // MC phy registers set per
2577
+  uint8_t   vender_rev_id;                 // [7:4] Revision, [3:0] Vendor code
2578
+  uint8_t   refreshrate;                   // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2579
+  uint8_t   vram_flags;			   // bit0= bankgroup enable
2580
+  uint8_t   vram_rsd2;			   // reserved
2581
+  uint16_t  gddr6_mr10;                    // gddr6 mode register10 value
2582
+  uint16_t  gddr6_mr1;                     // gddr6 mode register1 value
2583
+  uint16_t  gddr6_mr2;                     // gddr6 mode register2 value
2584
+  uint16_t  gddr6_mr7;                     // gddr6 mode register7 value
2585
+  char    dram_pnstring[20];               // part number end with '0'
2586
+};
2587
+
2588
+struct atom_vram_info_header_v2_4 {
2589
+  struct   atom_common_table_header table_header;
2590
+  uint16_t mem_adjust_tbloffset;                         // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
2591
+  uint16_t mem_clk_patch_tbloffset;                      // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
2592
+  uint16_t mc_adjust_pertile_tbloffset;                  // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
2593
+  uint16_t mc_phyinit_tbloffset;                         // offset of atom_umc_init_reg_block structure for MC phy init set
2594
+  uint16_t dram_data_remap_tbloffset;                    // reserved for now
2595
+  uint16_t reserved;                                     // offset of reserved
2596
+  uint16_t post_ucode_init_offset;                       // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
2597
+  uint16_t vram_rsd2;
2598
+  uint8_t  vram_module_num;                              // indicate number of VRAM module
2599
+  uint8_t  umcip_min_ver;
2600
+  uint8_t  umcip_max_ver;
2601
+  uint8_t  mc_phy_tile_num;                              // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
2602
+  struct   atom_vram_module_v10  vram_module[16];        // just for allocation, real number of blocks is in ucNumOfVRAMModule;
2603
+};
2604
+
2605
+struct atom_vram_module_v11 {
2606
+	// Design Specific Values
2607
+	uint32_t  memory_size;                   // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
2608
+	uint32_t  channel_enable;                // bit vector, each bit indicate specific channel enable or not
2609
+	uint16_t  mem_voltage;                   // mem_voltage
2610
+	uint16_t  vram_module_size;              // Size of atom_vram_module_v9
2611
+	uint8_t   ext_memory_id;                 // Current memory module ID
2612
+	uint8_t   memory_type;                   // enum of atom_dgpu_vram_type
2613
+	uint8_t   channel_num;                   // Number of mem. channels supported in this module
2614
+	uint8_t   channel_width;                 // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2615
+	uint8_t   density;                       // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2616
+	uint8_t   tunningset_id;                 // MC phy registers set per.
2617
+	uint16_t  reserved[4];                   // reserved
2618
+	uint8_t   vender_rev_id;                 // [7:4] Revision, [3:0] Vendor code
2619
+	uint8_t   refreshrate;			 // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2620
+	uint8_t   vram_flags;			 // bit0= bankgroup enable
2621
+	uint8_t   vram_rsd2;			 // reserved
2622
+	uint16_t  gddr6_mr10;                    // gddr6 mode register10 value
2623
+	uint16_t  gddr6_mr0;                     // gddr6 mode register0 value
2624
+	uint16_t  gddr6_mr1;                     // gddr6 mode register1 value
2625
+	uint16_t  gddr6_mr2;                     // gddr6 mode register2 value
2626
+	uint16_t  gddr6_mr4;                     // gddr6 mode register4 value
2627
+	uint16_t  gddr6_mr7;                     // gddr6 mode register7 value
2628
+	uint16_t  gddr6_mr8;                     // gddr6 mode register8 value
2629
+	char    dram_pnstring[40];               // part number end with '0'.
2630
+};
2631
+
2632
+struct atom_gddr6_ac_timing_v2_5 {
2633
+	uint32_t  u32umc_id_access;
2634
+	uint8_t  RL;
2635
+	uint8_t  WL;
2636
+	uint8_t  tRAS;
2637
+	uint8_t  tRC;
2638
+
2639
+	uint16_t  tREFI;
2640
+	uint8_t  tRFC;
2641
+	uint8_t  tRFCpb;
2642
+
2643
+	uint8_t  tRREFD;
2644
+	uint8_t  tRCDRD;
2645
+	uint8_t  tRCDWR;
2646
+	uint8_t  tRP;
2647
+
2648
+	uint8_t  tRRDS;
2649
+	uint8_t  tRRDL;
2650
+	uint8_t  tWR;
2651
+	uint8_t  tWTRS;
2652
+
2653
+	uint8_t  tWTRL;
2654
+	uint8_t  tFAW;
2655
+	uint8_t  tCCDS;
2656
+	uint8_t  tCCDL;
2657
+
2658
+	uint8_t  tCRCRL;
2659
+	uint8_t  tCRCWL;
2660
+	uint8_t  tCKE;
2661
+	uint8_t  tCKSRE;
2662
+
2663
+	uint8_t  tCKSRX;
2664
+	uint8_t  tRTPS;
2665
+	uint8_t  tRTPL;
2666
+	uint8_t  tMRD;
2667
+
2668
+	uint8_t  tMOD;
2669
+	uint8_t  tXS;
2670
+	uint8_t  tXHP;
2671
+	uint8_t  tXSMRS;
2672
+
2673
+	uint32_t  tXSH;
2674
+
2675
+	uint8_t  tPD;
2676
+	uint8_t  tXP;
2677
+	uint8_t  tCPDED;
2678
+	uint8_t  tACTPDE;
2679
+
2680
+	uint8_t  tPREPDE;
2681
+	uint8_t  tREFPDE;
2682
+	uint8_t  tMRSPDEN;
2683
+	uint8_t  tRDSRE;
2684
+
2685
+	uint8_t  tWRSRE;
2686
+	uint8_t  tPPD;
2687
+	uint8_t  tCCDMW;
2688
+	uint8_t  tWTRTR;
2689
+
2690
+	uint8_t  tLTLTR;
2691
+	uint8_t  tREFTR;
2692
+	uint8_t  VNDR;
2693
+	uint8_t  reserved[9];
2694
+};
2695
+
2696
+struct atom_gddr6_bit_byte_remap {
2697
+	uint32_t dphy_byteremap;    //mmUMC_DPHY_ByteRemap
2698
+	uint32_t dphy_bitremap0;    //mmUMC_DPHY_BitRemap0
2699
+	uint32_t dphy_bitremap1;    //mmUMC_DPHY_BitRemap1
2700
+	uint32_t dphy_bitremap2;    //mmUMC_DPHY_BitRemap2
2701
+	uint32_t aphy_bitremap0;    //mmUMC_APHY_BitRemap0
2702
+	uint32_t aphy_bitremap1;    //mmUMC_APHY_BitRemap1
2703
+	uint32_t phy_dram;          //mmUMC_PHY_DRAM
2704
+};
2705
+
2706
+struct atom_gddr6_dram_data_remap {
2707
+	uint32_t table_size;
2708
+	uint8_t phyintf_ck_inverted[8];     //UMC_PHY_PHYINTF_CNTL.INV_CK
2709
+	struct atom_gddr6_bit_byte_remap bit_byte_remap[16];
2710
+};
2711
+
2712
+struct atom_vram_info_header_v2_5 {
2713
+	struct   atom_common_table_header table_header;
2714
+	uint16_t mem_adjust_tbloffset;                         // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust settings
2715
+	uint16_t gddr6_ac_timing_offset;                     // offset of atom_gddr6_ac_timing_v2_5 structure for memory clock specific UMC settings
2716
+	uint16_t mc_adjust_pertile_tbloffset;                  // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
2717
+	uint16_t mc_phyinit_tbloffset;                         // offset of atom_umc_init_reg_block structure for MC phy init set
2718
+	uint16_t dram_data_remap_tbloffset;                    // offset of atom_gddr6_dram_data_remap array to indicate DRAM data lane to GPU mapping
2719
+	uint16_t reserved;                                     // offset of reserved
2720
+	uint16_t post_ucode_init_offset;                       // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
2721
+	uint16_t strobe_mode_patch_tbloffset;                  // offset of atom_umc_init_reg_block structure for Strobe Mode memory clock specific UMC settings
2722
+	uint8_t  vram_module_num;                              // indicate number of VRAM module
2723
+	uint8_t  umcip_min_ver;
2724
+	uint8_t  umcip_max_ver;
2725
+	uint8_t  mc_phy_tile_num;                              // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
2726
+	struct   atom_vram_module_v11  vram_module[16];        // just for allocation, real number of blocks is in ucNumOfVRAMModule;
2727
+};
16892728 
16902729 /* 
16912730   ***************************************************************************