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2024-05-10 cde9070d9970eef1f7ec2360586c802a16230ad8 
 kernel/drivers/gpu/drm/amd/include/amd_shared.h
....@@ -26,7 +26,7 @@
2626 #include <drm/amd_asic_type.h>
2727 
2828 
29
-#define AMD_MAX_USEC_TIMEOUT		200000  /* 200 ms */
29
+#define AMD_MAX_USEC_TIMEOUT		1000000  /* 1000 ms */
3030 
3131 /*
3232  * Chip flags
....@@ -40,6 +40,48 @@
4040 	AMD_EXP_HW_SUPPORT = 0x00080000UL,
4141 };
4242 
43
+enum amd_apu_flags {
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+	AMD_APU_IS_RAVEN = 0x00000001UL,
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+	AMD_APU_IS_RAVEN2 = 0x00000002UL,
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+	AMD_APU_IS_PICASSO = 0x00000004UL,
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+	AMD_APU_IS_RENOIR = 0x00000008UL,
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+	AMD_APU_IS_GREEN_SARDINE = 0x00000010UL,
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+};
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+
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+/**
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+* DOC: IP Blocks
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+*
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+* GPUs are composed of IP (intellectual property) blocks. These
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+* IP blocks provide various functionalities: display, graphics,
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+* video decode, etc. The IP blocks that comprise a particular GPU
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+* are listed in the GPU's respective SoC file. amdgpu_device.c
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+* acquires the list of IP blocks for the GPU in use on initialization.
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+* It can then operate on this list to perform standard driver operations
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+* such as: init, fini, suspend, resume, etc.
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+* 
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+*
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+* IP block implementations are named using the following convention:
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+* <functionality>_v<version> (E.g.: gfx_v6_0).
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+*/
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+
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+/**
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+* enum amd_ip_block_type - Used to classify IP blocks by functionality.
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+*
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+* @AMD_IP_BLOCK_TYPE_COMMON: GPU Family
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+* @AMD_IP_BLOCK_TYPE_GMC: Graphics Memory Controller
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+* @AMD_IP_BLOCK_TYPE_IH: Interrupt Handler
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+* @AMD_IP_BLOCK_TYPE_SMC: System Management Controller
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+* @AMD_IP_BLOCK_TYPE_PSP: Platform Security Processor
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+* @AMD_IP_BLOCK_TYPE_DCE: Display and Compositing Engine
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+* @AMD_IP_BLOCK_TYPE_GFX: Graphics and Compute Engine
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+* @AMD_IP_BLOCK_TYPE_SDMA: System DMA Engine
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+* @AMD_IP_BLOCK_TYPE_UVD: Unified Video Decoder
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+* @AMD_IP_BLOCK_TYPE_VCE: Video Compression Engine
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+* @AMD_IP_BLOCK_TYPE_ACP: Audio Co-Processor
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+* @AMD_IP_BLOCK_TYPE_VCN: Video Core/Codec Next
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+* @AMD_IP_BLOCK_TYPE_MES: Micro-Engine Scheduler
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+* @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine
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+*/
4385 enum amd_ip_block_type {
4486 	AMD_IP_BLOCK_TYPE_COMMON,
4587 	AMD_IP_BLOCK_TYPE_GMC,
....@@ -52,7 +94,9 @@
5294 	AMD_IP_BLOCK_TYPE_UVD,
5395 	AMD_IP_BLOCK_TYPE_VCE,
5496 	AMD_IP_BLOCK_TYPE_ACP,
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-	AMD_IP_BLOCK_TYPE_VCN
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+	AMD_IP_BLOCK_TYPE_VCN,
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+	AMD_IP_BLOCK_TYPE_MES,
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+	AMD_IP_BLOCK_TYPE_JPEG
56100 };
57101 
58102 enum amd_clockgating_state {
....@@ -93,6 +137,12 @@
93137 #define AMD_CG_SUPPORT_DRM_MGCG			(1 << 22)
94138 #define AMD_CG_SUPPORT_DF_MGCG			(1 << 23)
95139 #define AMD_CG_SUPPORT_VCN_MGCG			(1 << 24)
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+#define AMD_CG_SUPPORT_HDP_DS			(1 << 25)
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+#define AMD_CG_SUPPORT_HDP_SD			(1 << 26)
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+#define AMD_CG_SUPPORT_IH_CG			(1 << 27)
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+#define AMD_CG_SUPPORT_ATHUB_LS			(1 << 28)
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+#define AMD_CG_SUPPORT_ATHUB_MGCG		(1 << 29)
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+#define AMD_CG_SUPPORT_JPEG_MGCG		(1 << 30)
96146 /* PG flags */
97147 #define AMD_PG_SUPPORT_GFX_PG			(1 << 0)
98148 #define AMD_PG_SUPPORT_GFX_SMG			(1 << 1)
....@@ -109,7 +159,38 @@
109159 #define AMD_PG_SUPPORT_GFX_PIPELINE		(1 << 12)
110160 #define AMD_PG_SUPPORT_MMHUB			(1 << 13)
111161 #define AMD_PG_SUPPORT_VCN			(1 << 14)
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+#define AMD_PG_SUPPORT_VCN_DPG			(1 << 15)
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+#define AMD_PG_SUPPORT_ATHUB			(1 << 16)
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+#define AMD_PG_SUPPORT_JPEG			(1 << 17)
112165 
166
+/**
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+ * enum PP_FEATURE_MASK - Used to mask power play features.
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+ *
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+ * @PP_SCLK_DPM_MASK: Dynamic adjustment of the system (graphics) clock.
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+ * @PP_MCLK_DPM_MASK: Dynamic adjustment of the memory clock.
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+ * @PP_PCIE_DPM_MASK: Dynamic adjustment of PCIE clocks and lanes.
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+ * @PP_SCLK_DEEP_SLEEP_MASK: System (graphics) clock deep sleep.
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+ * @PP_POWER_CONTAINMENT_MASK: Power containment.
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+ * @PP_UVD_HANDSHAKE_MASK: Unified video decoder handshake.
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+ * @PP_SMC_VOLTAGE_CONTROL_MASK: Dynamic voltage control.
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+ * @PP_VBI_TIME_SUPPORT_MASK: Vertical blank interval support.
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+ * @PP_ULV_MASK: Ultra low voltage.
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+ * @PP_ENABLE_GFX_CG_THRU_SMU: SMU control of GFX engine clockgating.
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+ * @PP_CLOCK_STRETCH_MASK: Clock stretching.
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+ * @PP_OD_FUZZY_FAN_CONTROL_MASK: Overdrive fuzzy fan control.
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+ * @PP_SOCCLK_DPM_MASK: Dynamic adjustment of the SoC clock.
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+ * @PP_DCEFCLK_DPM_MASK: Dynamic adjustment of the Display Controller Engine Fabric clock.
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+ * @PP_OVERDRIVE_MASK: Over- and under-clocking support.
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+ * @PP_GFXOFF_MASK: Dynamic graphics engine power control.
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+ * @PP_ACG_MASK: Adaptive clock generator.
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+ * @PP_STUTTER_MODE: Stutter mode.
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+ * @PP_AVFS_MASK: Adaptive voltage and frequency scaling.
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+ *
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+ * To override these settings on boot, append amdgpu.ppfeaturemask=<mask> to
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+ * the kernel's command line parameters. This is usually done through a system's
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+ * boot loader (E.g. GRUB). If manually loading the driver, pass
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+ * ppfeaturemask=<mask> as a modprobe parameter.
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+ */
113194 enum PP_FEATURE_MASK {
114195 	PP_SCLK_DPM_MASK = 0x1,
115196 	PP_MCLK_DPM_MASK = 0x2,
....@@ -129,57 +210,78 @@
129210 	PP_GFXOFF_MASK = 0x8000,
130211 	PP_ACG_MASK = 0x10000,
131212 	PP_STUTTER_MODE = 0x20000,
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+	PP_AVFS_MASK = 0x40000,
132214 };
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+
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+enum DC_FEATURE_MASK {
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+	DC_FBC_MASK = 0x1,
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+	DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2,
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+	DC_DISABLE_FRACTIONAL_PWM_MASK = 0x4,
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+	DC_PSR_MASK = 0x8,
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+};
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+
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+enum DC_DEBUG_MASK {
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+	DC_DISABLE_PIPE_SPLIT = 0x1,
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+	DC_DISABLE_STUTTER = 0x2,
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+	DC_DISABLE_DSC = 0x4,
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+	DC_DISABLE_CLOCK_GATING = 0x8
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+};
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+
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+enum amd_dpm_forced_level;
133231 
134232 /**
135233  * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks
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+ * @name: Name of IP block
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+ * @early_init: sets up early driver state (pre sw_init),
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+ *              does not configure hw - Optional
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+ * @late_init: sets up late driver/hw state (post hw_init) - Optional
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+ * @sw_init: sets up driver state, does not configure hw
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+ * @sw_fini: tears down driver state, does not configure hw
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+ * @hw_init: sets up the hw state
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+ * @hw_fini: tears down the hw state
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+ * @late_fini: final cleanup
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+ * @suspend: handles IP specific hw/sw changes for suspend
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+ * @resume: handles IP specific hw/sw changes for resume
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+ * @is_idle: returns current IP block idle status
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+ * @wait_for_idle: poll for idle
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+ * @check_soft_reset: check soft reset the IP block
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+ * @pre_soft_reset: pre soft reset the IP block
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+ * @soft_reset: soft reset the IP block
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+ * @post_soft_reset: post soft reset the IP block
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+ * @set_clockgating_state: enable/disable cg for the IP block
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+ * @set_powergating_state: enable/disable pg for the IP block
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+ * @get_clockgating_state: get current clockgating status
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+ * @enable_umd_pstate: enable UMD powerstate
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+ *
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+ * These hooks provide an interface for controlling the operational state
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+ * of IP blocks. After acquiring a list of IP blocks for the GPU in use,
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+ * the driver can make chip-wide state changes by walking this list and
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+ * making calls to hooks from each IP block. This list is ordered to ensure
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+ * that the driver initializes the IP blocks in a safe sequence.
136261  */
137262 struct amd_ip_funcs {
138
-	/** @name: Name of IP block */
139263 	char *name;
140
-	/**
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-	 * @early_init:
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-	 *
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-	 * sets up early driver state (pre sw_init),
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-	 * does not configure hw - Optional
145
-	 */
146264 	int (*early_init)(void *handle);
147
-	/** @late_init: sets up late driver/hw state (post hw_init) - Optional */
148265 	int (*late_init)(void *handle);
149
-	/** @sw_init: sets up driver state, does not configure hw */
150266 	int (*sw_init)(void *handle);
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-	/** @sw_fini: tears down driver state, does not configure hw */
152267 	int (*sw_fini)(void *handle);
153
-	/** @hw_init: sets up the hw state */
154268 	int (*hw_init)(void *handle);
155
-	/** @hw_fini: tears down the hw state */
156269 	int (*hw_fini)(void *handle);
157
-	/** @late_fini: final cleanup */
158270 	void (*late_fini)(void *handle);
159
-	/** @suspend: handles IP specific hw/sw changes for suspend */
160271 	int (*suspend)(void *handle);
161
-	/** @resume: handles IP specific hw/sw changes for resume */
162272 	int (*resume)(void *handle);
163
-	/** @is_idle: returns current IP block idle status */
164273 	bool (*is_idle)(void *handle);
165
-	/** @wait_for_idle: poll for idle */
166274 	int (*wait_for_idle)(void *handle);
167
-	/** @check_soft_reset: check soft reset the IP block */
168275 	bool (*check_soft_reset)(void *handle);
169
-	/** @pre_soft_reset: pre soft reset the IP block */
170276 	int (*pre_soft_reset)(void *handle);
171
-	/** @soft_reset: soft reset the IP block */
172277 	int (*soft_reset)(void *handle);
173
-	/** @post_soft_reset: post soft reset the IP block */
174278 	int (*post_soft_reset)(void *handle);
175
-	/** @set_clockgating_state: enable/disable cg for the IP block */
176279 	int (*set_clockgating_state)(void *handle,
177280 				     enum amd_clockgating_state state);
178
-	/** @set_powergating_state: enable/disable pg for the IP block */
179281 	int (*set_powergating_state)(void *handle,
180282 				     enum amd_powergating_state state);
181
-	/** @get_clockgating_state: get current clockgating status */
182283 	void (*get_clockgating_state)(void *handle, u32 *flags);
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+	int (*enable_umd_pstate)(void *handle, enum amd_dpm_forced_level *level);
183285 };
184286 
185287