forked from ~ljy/RK356X_SDK_RELEASE

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2024-05-10 cde9070d9970eef1f7ec2360586c802a16230ad8 
 kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
....@@ -34,6 +34,7 @@
3434 #define HUBP_REG_LIST_DCN(id)\
3535 	SRI(DCHUBP_CNTL, HUBP, id),\
3636 	SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
37
+	SRI(HUBPREQ_DEBUG, HUBP, id),\
3738 	SRI(DCSURF_ADDR_CONFIG, HUBP, id),\
3839 	SRI(DCSURF_TILING_CONFIG, HUBP, id),\
3940 	SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\
....@@ -46,6 +47,8 @@
4647 	SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \
4748 	SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \
4849 	SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \
50
+	SRI(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id), \
51
+	SRI(DCSURF_SEC_VIEWPORT_START_C, HUBP, id), \
4952 	SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
5053 	SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\
5154 	SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
....@@ -56,8 +59,12 @@
5659 	SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
5760 	SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
5861 	SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
62
+	SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
63
+	SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
5964 	SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
6065 	SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
66
+	SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
67
+	SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
6168 	SRI(DCSURF_SURFACE_INUSE, HUBPREQ, id),\
6269 	SRI(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),\
6370 	SRI(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),\
....@@ -124,8 +131,6 @@
124131 	SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\
125132 	SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\
126133 	SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\
127
-	SR(DCHUBBUB_SDPIF_FB_BASE),\
128
-	SR(DCHUBBUB_SDPIF_FB_OFFSET),\
129134 	SRI(CURSOR_SETTINS, HUBPREQ, id), \
130135 	SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
131136 	SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
....@@ -138,6 +143,7 @@
138143 #define HUBP_COMMON_REG_VARIABLE_LIST \
139144 	uint32_t DCHUBP_CNTL; \
140145 	uint32_t HUBPREQ_DEBUG_DB; \
146
+	uint32_t HUBPREQ_DEBUG; \
141147 	uint32_t DCSURF_ADDR_CONFIG; \
142148 	uint32_t DCSURF_TILING_CONFIG; \
143149 	uint32_t DCSURF_SURFACE_PITCH; \
....@@ -150,6 +156,8 @@
150156 	uint32_t DCSURF_SEC_VIEWPORT_START; \
151157 	uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C; \
152158 	uint32_t DCSURF_PRI_VIEWPORT_START_C; \
159
+	uint32_t DCSURF_SEC_VIEWPORT_DIMENSION_C; \
160
+	uint32_t DCSURF_SEC_VIEWPORT_START_C; \
153161 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; \
154162 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; \
155163 	uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH; \
....@@ -160,8 +168,12 @@
160168 	uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS; \
161169 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; \
162170 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; \
171
+	uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C; \
172
+	uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_C; \
163173 	uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C; \
164174 	uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C; \
175
+	uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C; \
176
+	uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_C; \
165177 	uint32_t DCSURF_SURFACE_INUSE; \
166178 	uint32_t DCSURF_SURFACE_INUSE_HIGH; \
167179 	uint32_t DCSURF_SURFACE_INUSE_C; \
....@@ -224,14 +236,6 @@
224236 	uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB; \
225237 	uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR; \
226238 	uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR; \
227
-	uint32_t DCHUBBUB_SDPIF_FB_BASE; \
228
-	uint32_t DCHUBBUB_SDPIF_FB_OFFSET; \
229
-	uint32_t DCN_VM_FB_LOCATION_TOP; \
230
-	uint32_t DCN_VM_FB_LOCATION_BASE; \
231
-	uint32_t DCN_VM_FB_OFFSET; \
232
-	uint32_t DCN_VM_AGP_BASE; \
233
-	uint32_t DCN_VM_AGP_BOT; \
234
-	uint32_t DCN_VM_AGP_TOP; \
235239 	uint32_t CURSOR_SETTINS; \
236240 	uint32_t CURSOR_SETTINGS; \
237241 	uint32_t CURSOR_SURFACE_ADDRESS_HIGH; \
....@@ -247,10 +251,12 @@
247251 	.field_name = reg_name ## __ ## field_name ## post_fix
248252 
249253 /* Mask/shift struct generation macro for all ASICs (including those with reduced functionality) */
250
-#define HUBP_MASK_SH_LIST_DCN(mask_sh)\
254
+/*1.x, 2.x, and 3.x*/
255
+#define HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh)\
251256 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
252257 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
253258 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
259
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\
254260 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
255261 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
256262 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\
....@@ -262,7 +268,6 @@
262268 	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
263269 	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
264270 	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
265
-	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
266271 	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
267272 	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
268273 	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
....@@ -270,6 +275,8 @@
270275 	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\
271276 	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
272277 	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
278
+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, mask_sh),\
279
+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, mask_sh),\
273280 	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\
274281 	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\
275282 	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\
....@@ -284,6 +291,10 @@
284291 	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\
285292 	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\
286293 	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\
294
+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_WIDTH_C, mask_sh),\
295
+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_HEIGHT_C, mask_sh),\
296
+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_X_START_C, mask_sh),\
297
+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_Y_START_C, mask_sh),\
287298 	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
288299 	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
289300 	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
....@@ -294,8 +305,12 @@
294305 	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\
295306 	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
296307 	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
308
+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, SECONDARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
309
+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C, SECONDARY_SURFACE_ADDRESS_C, mask_sh),\
297310 	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
298311 	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
312
+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, SECONDARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
313
+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, SECONDARY_META_SURFACE_ADDRESS_C, mask_sh),\
299314 	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\
300315 	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\
301316 	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\
....@@ -328,7 +343,6 @@
328343 	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\
329344 	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\
330345 	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\
331
-	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
332346 	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\
333347 	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\
334348 	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\
....@@ -336,7 +350,6 @@
336350 	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\
337351 	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\
338352 	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\
339
-	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh),\
340353 	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\
341354 	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\
342355 	HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\
....@@ -369,6 +382,16 @@
369382 	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
370383 	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
371384 	HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh)
385
+/*2.x and 1.x only*/
386
+#define HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)\
387
+	HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\
388
+	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
389
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
390
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh)
391
+
392
+/*2.x and 1.x only*/
393
+#define HUBP_MASK_SH_LIST_DCN(mask_sh)\
394
+	HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)
372395 
373396 /* Mask/shift struct generation macro for ASICs with VM */
374397 #define HUBP_MASK_SH_LIST_DCN_VM(mask_sh)\
....@@ -404,8 +427,6 @@
404427 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\
405428 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\
406429 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\
407
-	HUBP_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh),\
408
-	HUBP_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\
409430 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
410431 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
411432 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\
....@@ -426,13 +447,14 @@
426447 	HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
427448 	HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)
428449 
429
-#define DCN_HUBP_REG_FIELD_LIST(type) \
450
+#define DCN_HUBP_REG_FIELD_BASE_LIST(type) \
430451 	type HUBP_BLANK_EN;\
431452 	type HUBP_DISABLE;\
432453 	type HUBP_TTU_DISABLE;\
433454 	type HUBP_NO_OUTSTANDING_REQ;\
434455 	type HUBP_VTG_SEL;\
435456 	type HUBP_UNDERFLOW_STATUS;\
457
+	type HUBP_UNDERFLOW_CLEAR;\
436458 	type NUM_PIPES;\
437459 	type NUM_BANKS;\
438460 	type PIPE_INTERLEAVE;\
....@@ -451,6 +473,8 @@
451473 	type H_MIRROR_EN;\
452474 	type SURFACE_PIXEL_FORMAT;\
453475 	type SURFACE_FLIP_TYPE;\
476
+	type SURFACE_FLIP_MODE_FOR_STEREOSYNC;\
477
+	type SURFACE_FLIP_IN_STEREOSYNC;\
454478 	type SURFACE_UPDATE_LOCK;\
455479 	type SURFACE_FLIP_PENDING;\
456480 	type PRI_VIEWPORT_WIDTH; \
....@@ -465,6 +489,10 @@
465489 	type PRI_VIEWPORT_HEIGHT_C; \
466490 	type PRI_VIEWPORT_X_START_C; \
467491 	type PRI_VIEWPORT_Y_START_C; \
492
+	type SEC_VIEWPORT_WIDTH_C; \
493
+	type SEC_VIEWPORT_HEIGHT_C; \
494
+	type SEC_VIEWPORT_X_START_C; \
495
+	type SEC_VIEWPORT_Y_START_C; \
468496 	type PRIMARY_SURFACE_ADDRESS_HIGH;\
469497 	type PRIMARY_SURFACE_ADDRESS;\
470498 	type SECONDARY_SURFACE_ADDRESS_HIGH;\
....@@ -475,8 +503,12 @@
475503 	type SECONDARY_META_SURFACE_ADDRESS;\
476504 	type PRIMARY_SURFACE_ADDRESS_HIGH_C;\
477505 	type PRIMARY_SURFACE_ADDRESS_C;\
506
+	type SECONDARY_SURFACE_ADDRESS_HIGH_C;\
507
+	type SECONDARY_SURFACE_ADDRESS_C;\
478508 	type PRIMARY_META_SURFACE_ADDRESS_HIGH_C;\
479509 	type PRIMARY_META_SURFACE_ADDRESS_C;\
510
+	type SECONDARY_META_SURFACE_ADDRESS_HIGH_C;\
511
+	type SECONDARY_META_SURFACE_ADDRESS_C;\
480512 	type SURFACE_INUSE_ADDRESS;\
481513 	type SURFACE_INUSE_ADDRESS_HIGH;\
482514 	type SURFACE_INUSE_ADDRESS_C;\
....@@ -577,18 +609,9 @@
577609 	type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;\
578610 	type MC_VM_SYSTEM_APERTURE_LOW_ADDR;\
579611 	type MC_VM_SYSTEM_APERTURE_HIGH_ADDR;\
580
-	type SDPIF_FB_TOP;\
581
-	type SDPIF_FB_BASE;\
582
-	type SDPIF_FB_OFFSET;\
583
-	type SDPIF_AGP_BASE;\
584
-	type SDPIF_AGP_BOT;\
585
-	type SDPIF_AGP_TOP;\
586
-	type FB_TOP;\
587
-	type FB_BASE;\
588
-	type FB_OFFSET;\
589
-	type AGP_BASE;\
590
-	type AGP_BOT;\
591
-	type AGP_TOP;\
612
+	type DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\
613
+	type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\
614
+	type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\
592615 	/* todo:  get these from GVM instead of reading registers ourselves */\
593616 	type PAGE_DIRECTORY_ENTRY_HI32;\
594617 	type PAGE_DIRECTORY_ENTRY_LO32;\
....@@ -617,6 +640,10 @@
617640 	type CURSOR_DST_X_OFFSET; \
618641 	type OUTPUT_FP
619642 
643
+#define DCN_HUBP_REG_FIELD_LIST(type) \
644
+	DCN_HUBP_REG_FIELD_BASE_LIST(type);\
645
+	type ALPHA_PLANE_EN
646
+
620647 struct dcn_mi_registers {
621648 	HUBP_COMMON_REG_VARIABLE_LIST;
622649 };
....@@ -635,6 +662,7 @@
635662 	struct _vcs_dpi_display_rq_regs_st rq_regs;
636663 	uint32_t pixel_format;
637664 	uint32_t inuse_addr_hi;
665
+	uint32_t inuse_addr_lo;
638666 	uint32_t viewport_width;
639667 	uint32_t viewport_height;
640668 	uint32_t rotation_angle;
....@@ -642,6 +670,7 @@
642670 	uint32_t sw_mode;
643671 	uint32_t dcc_en;
644672 	uint32_t blank_en;
673
+	uint32_t clock_en;
645674 	uint32_t underflow_status;
646675 	uint32_t ttu_disable;
647676 	uint32_t min_ttu_vblank;
....@@ -661,10 +690,11 @@
661690 	struct hubp *hubp,
662691 	enum surface_pixel_format format,
663692 	union dc_tiling_info *tiling_info,
664
-	union plane_size *plane_size,
693
+	struct plane_size *plane_size,
665694 	enum dc_rotation_angle rotation,
666695 	struct dc_plane_dcc_param *dcc,
667
-	bool horizontal_mirror);
696
+	bool horizontal_mirror,
697
+	unsigned int compat_level);
668698 
669699 void hubp1_program_deadline(
670700 		struct hubp *hubp,
....@@ -682,7 +712,7 @@
682712 void hubp1_program_size(
683713 	struct hubp *hubp,
684714 	enum surface_pixel_format format,
685
-	const union plane_size *plane_size,
715
+	const struct plane_size *plane_size,
686716 	struct dc_plane_dcc_param *dcc);
687717 
688718 void hubp1_program_rotation(
....@@ -697,7 +727,7 @@
697727 
698728 void hubp1_dcc_control(struct hubp *hubp,
699729 		bool enable,
700
-		bool independent_64b_blks);
730
+		enum hubp_ind_block_size independent_64b_blks);
701731 
702732 bool hubp1_program_surface_flip_and_addr(
703733 	struct hubp *hubp,
....@@ -733,8 +763,14 @@
733763 	const struct dcn_mi_mask *hubp_mask);
734764 
735765 void hubp1_read_state(struct hubp *hubp);
766
+void hubp1_clear_underflow(struct hubp *hubp);
736767 
737768 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch);
738769 
770
+void hubp1_vready_workaround(struct hubp *hubp,
771
+		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
772
+
773
+void hubp1_init(struct hubp *hubp);
774
+void hubp1_read_state_common(struct hubp *hubp);
739775 
740776 #endif