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hc
2024-05-10 cde9070d9970eef1f7ec2360586c802a16230ad8 
 kernel/drivers/edac/pnd2_edac.c
....@@ -1,16 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Driver for Pondicherry2 memory controller.
34  *
45  * Copyright (c) 2016, Intel Corporation.
5
- *
6
- * This program is free software; you can redistribute it and/or modify it
7
- * under the terms and conditions of the GNU General Public License,
8
- * version 2, as published by the Free Software Foundation.
9
- *
10
- * This program is distributed in the hope it will be useful, but WITHOUT
11
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
- * more details.
146  *
157  * [Derived from sb_edac.c]
168  *
....@@ -206,7 +198,7 @@
206198 	switch (sz) {
207199 	case 8:
208200 		ret = _apl_rd_reg(port, off + 4, op, (u32 *)(data + 4));
209
-		/* fall through */
201
+		fallthrough;
210202 	case 4:
211203 		ret |= _apl_rd_reg(port, off, op, (u32 *)data);
212204 		pnd2_printk(KERN_DEBUG, "%s=%x%08x ret=%d\n", name,
....@@ -1163,7 +1155,7 @@
11631155 	u32 optypenum = GET_BITFIELD(m->status, 4, 6);
11641156 	int rc;
11651157 
1166
-	tp_event = uc_err ? (ripv ? HW_EVENT_ERR_FATAL : HW_EVENT_ERR_UNCORRECTED) :
1158
+	tp_event = uc_err ? (ripv ? HW_EVENT_ERR_UNCORRECTED : HW_EVENT_ERR_FATAL) :
11671159 						 HW_EVENT_ERR_CORRECTED;
11681160 
11691161 	/*
....@@ -1239,7 +1231,7 @@
12391231 		if (!(chan_mask & BIT(i)))
12401232 			continue;
12411233 
1242
-		dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, i, 0, 0);
1234
+		dimm = edac_get_dimm(mci, i, 0, 0);
12431235 		if (!dimm) {
12441236 			edac_dbg(0, "No allocated DIMM for channel %d\n", i);
12451237 			continue;
....@@ -1319,7 +1311,7 @@
13191311 			if (!ranks_of_dimm[j])
13201312 				continue;
13211313 
1322
-			dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, i, j, 0);
1314
+			dimm = edac_get_dimm(mci, i, j, 0);
13231315 			if (!dimm) {
13241316 				edac_dbg(0, "No allocated DIMM for channel %d DIMM %d\n", i, j);
13251317 				continue;
....@@ -1404,11 +1396,8 @@
14041396 	struct dram_addr daddr;
14051397 	char *type;
14061398 
1407
-	if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
1408
-		return NOTIFY_DONE;
1409
-
14101399 	mci = pnd2_mci;
1411
-	if (!mci)
1400
+	if (!mci || (mce->kflags & MCE_HANDLED_CEC))
14121401 		return NOTIFY_DONE;
14131402 
14141403 	/*
....@@ -1437,11 +1426,13 @@
14371426 	pnd2_mce_output_error(mci, mce, &daddr);
14381427 
14391428 	/* Advice mcelog that the error were handled */
1440
-	return NOTIFY_STOP;
1429
+	mce->kflags |= MCE_HANDLED_EDAC;
1430
+	return NOTIFY_OK;
14411431 }
14421432 
14431433 static struct notifier_block pnd2_mce_dec = {
14441434 	.notifier_call	= pnd2_mce_check_error,
1435
+	.priority	= MCE_PRIO_EDAC,
14451436 };
14461437 
14471438 #ifdef CONFIG_EDAC_DEBUG
....@@ -1545,8 +1536,8 @@
15451536 };
15461537 
15471538 static const struct x86_cpu_id pnd2_cpuids[] = {
1548
-	{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT, 0, (kernel_ulong_t)&apl_ops },
1549
-	{ X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT_X, 0, (kernel_ulong_t)&dnv_ops },
1539
+	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT,	&apl_ops),
1540
+	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D,	&dnv_ops),
15501541 	{ }
15511542 };
15521543 MODULE_DEVICE_TABLE(x86cpu, pnd2_cpuids);
....@@ -1563,6 +1554,9 @@
15631554 	if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
15641555 		return -EBUSY;
15651556 
1557
+	if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
1558
+		return -ENODEV;
1559
+
15661560 	id = x86_match_cpu(pnd2_cpuids);
15671561 	if (!id)
15681562 		return -ENODEV;