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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * Copyright (c) 2016 Chen-Yu Tsai |
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3 | 4 | * |
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4 | 5 | * Chen-Yu Tsai <wens@csie.org> |
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5 | 6 | * |
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6 | 7 | * Based on ccu-sun8i-h3.c by Maxime Ripard. |
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7 | | - * |
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8 | | - * This software is licensed under the terms of the GNU General Public |
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9 | | - * License version 2, as published by the Free Software Foundation, and |
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10 | | - * may be copied, distributed, and modified under those terms. |
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11 | | - * |
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12 | | - * This program is distributed in the hope that it will be useful, |
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13 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 | | - * GNU General Public License for more details. |
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16 | 8 | */ |
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17 | 9 | |
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18 | 10 | #include <linux/clk-provider.h> |
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| 11 | +#include <linux/io.h> |
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19 | 12 | #include <linux/of_address.h> |
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20 | 13 | |
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21 | 14 | #include "ccu_common.h" |
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.. | .. |
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962 | 955 | &out_c_clk.common, |
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963 | 956 | }; |
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964 | 957 | |
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| 958 | +static const struct clk_hw *clk_parent_pll_audio[] = { |
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| 959 | + &pll_audio_base_clk.common.hw |
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| 960 | +}; |
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| 961 | + |
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965 | 962 | /* We hardcode the divider to 1 for now */ |
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966 | | -static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", |
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967 | | - "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); |
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968 | | -static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", |
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969 | | - "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); |
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970 | | -static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", |
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971 | | - "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); |
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972 | | -static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", |
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973 | | - "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); |
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974 | | -static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x", |
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975 | | - "pll-periph", 1, 2, 0); |
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976 | | -static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x", |
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977 | | - "pll-video0", 1, 2, CLK_SET_RATE_PARENT); |
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978 | | -static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x", |
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979 | | - "pll-video1", 1, 2, CLK_SET_RATE_PARENT); |
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| 963 | +static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio", |
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| 964 | + clk_parent_pll_audio, |
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| 965 | + 1, 1, CLK_SET_RATE_PARENT); |
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| 966 | +static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x", |
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| 967 | + clk_parent_pll_audio, |
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| 968 | + 2, 1, CLK_SET_RATE_PARENT); |
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| 969 | +static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x", |
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| 970 | + clk_parent_pll_audio, |
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| 971 | + 1, 1, CLK_SET_RATE_PARENT); |
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| 972 | +static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x", |
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| 973 | + clk_parent_pll_audio, |
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| 974 | + 1, 2, CLK_SET_RATE_PARENT); |
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| 975 | +static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x", |
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| 976 | + &pll_periph_clk.common.hw, |
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| 977 | + 1, 2, 0); |
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| 978 | +static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x", |
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| 979 | + &pll_video0_clk.common.hw, |
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| 980 | + 1, 2, CLK_SET_RATE_PARENT); |
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| 981 | +static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x", |
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| 982 | + &pll_video1_clk.common.hw, |
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| 983 | + 1, 2, CLK_SET_RATE_PARENT); |
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980 | 984 | |
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981 | 985 | static struct clk_hw_onecell_data sun6i_a31_hw_clks = { |
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982 | 986 | .hws = { |
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