rtl88x2CE_WiFi_linux driver

hc

2024-05-10 cde9070d9970eef1f7ec2360586c802a16230ad8

 kernel/drivers/clk/renesas/rcar-gen3-cpg.h
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@@ -1,11 +1,10 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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 /*
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  * R-Car Gen3 Clock Pulse Generator
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  *
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- * Copyright (C) 2015-2016 Glider bvba
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+ * Copyright (C) 2015-2018 Glider bvba
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+ * Copyright (C) 2018 Renesas Electronics Corp.
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  *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; version 2 of the License.
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  */
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 #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
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@@ -20,19 +19,40 @@
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 	CLK_TYPE_GEN3_PLL4,
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 	CLK_TYPE_GEN3_SD,
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 	CLK_TYPE_GEN3_R,
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-	CLK_TYPE_GEN3_PE,
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+	CLK_TYPE_GEN3_MDSEL,	/* Select parent/divider using mode pin */
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 	CLK_TYPE_GEN3_Z,
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-	CLK_TYPE_GEN3_Z2,
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+	CLK_TYPE_GEN3_OSC,	/* OSC EXTAL predivider and fixed divider */
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+	CLK_TYPE_GEN3_RCKSEL,	/* Select parent/divider using RCKCR.CKSEL */
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+	CLK_TYPE_GEN3_RPCSRC,
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+	CLK_TYPE_GEN3_RPC,
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+	CLK_TYPE_GEN3_RPCD2,
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+
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+	/* SoC specific definitions start here */
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+	CLK_TYPE_GEN3_SOC_BASE,
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 };
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 #define DEF_GEN3_SD(_name, _id, _parent, _offset)	\
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 	DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
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+#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
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+	DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL,	\
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+		 (_parent0) << 16 | (_parent1),		\
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+		 .div = (_div0) << 16 | (_div1), .offset = _md)
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+
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 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
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 		    _div_clean) \
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-	DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE,			\
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-		 (_parent_sscg) << 16 | (_parent_clean),	\
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-		 .div = (_div_sscg) << 16 | (_div_clean))
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+	DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg,	\
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+		       _parent_clean, _div_clean)
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+
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+#define DEF_GEN3_OSC(_name, _id, _parent, _div)		\
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+	DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
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+
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+#define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
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+	DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL,	\
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+		 (_parent0) << 16 | (_parent1),	.div = (_div0) << 16 | (_div1))
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+
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+#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset)	\
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+	DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
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 struct rcar_gen3_cpg_pll_config {
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 	u8 extal_div;
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@@ -40,8 +60,10 @@
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 	u8 pll1_div;
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 	u8 pll3_mult;
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 	u8 pll3_div;
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+	u8 osc_prediv;
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 };
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+#define CPG_RPCCKCR	0x238
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 #define CPG_RCKCR	0x240
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 struct clk *rcar_gen3_cpg_clk_register(struct device *dev,