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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * Dynamic DMA mapping support for AMD Hammer. |
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3 | 4 | * |
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.. | .. |
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5 | 6 | * This allows to use PCI devices that only support 32bit addresses on systems |
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6 | 7 | * with more than 4GB. |
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7 | 8 | * |
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8 | | - * See Documentation/DMA-API-HOWTO.txt for the interface specification. |
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| 9 | + * See Documentation/core-api/dma-api-howto.rst for the interface specification. |
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9 | 10 | * |
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10 | 11 | * Copyright 2002 Andi Kleen, SuSE Labs. |
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11 | | - * Subject to the GNU General Public License v2 only. |
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12 | 12 | */ |
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13 | 13 | |
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14 | 14 | #include <linux/types.h> |
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.. | .. |
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32 | 32 | #include <linux/gfp.h> |
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33 | 33 | #include <linux/atomic.h> |
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34 | 34 | #include <linux/dma-direct.h> |
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| 35 | +#include <linux/dma-map-ops.h> |
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35 | 36 | #include <asm/mtrr.h> |
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36 | | -#include <asm/pgtable.h> |
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37 | 37 | #include <asm/proto.h> |
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38 | 38 | #include <asm/iommu.h> |
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39 | 39 | #include <asm/gart.h> |
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.. | .. |
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49 | 49 | static unsigned long iommu_pages; /* .. and in pages */ |
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50 | 50 | |
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51 | 51 | static u32 *iommu_gatt_base; /* Remapping table */ |
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52 | | - |
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53 | | -static dma_addr_t bad_dma_addr; |
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54 | 52 | |
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55 | 53 | /* |
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56 | 54 | * If this is disabled the IOMMU will use an optimized flushing strategy |
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.. | .. |
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73 | 71 | #define GPTE_ENCODE(x) \ |
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74 | 72 | (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT) |
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75 | 73 | #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28)) |
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76 | | - |
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77 | | -#define EMERGENCY_PAGES 32 /* = 128KB */ |
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78 | 74 | |
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79 | 75 | #ifdef CONFIG_AGP |
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80 | 76 | #define AGPEXTERN extern |
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.. | .. |
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101 | 97 | |
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102 | 98 | base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev), |
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103 | 99 | PAGE_SIZE) >> PAGE_SHIFT; |
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104 | | - boundary_size = ALIGN((u64)dma_get_seg_boundary(dev) + 1, |
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105 | | - PAGE_SIZE) >> PAGE_SHIFT; |
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| 100 | + boundary_size = dma_get_seg_boundary_nr_pages(dev, PAGE_SHIFT); |
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106 | 101 | |
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107 | 102 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
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108 | 103 | offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit, |
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.. | .. |
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155 | 150 | |
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156 | 151 | #ifdef CONFIG_IOMMU_LEAK |
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157 | 152 | /* Debugging aid for drivers that don't free their IOMMU tables */ |
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158 | | -static int leak_trace; |
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159 | | -static int iommu_leak_pages = 20; |
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160 | | - |
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161 | 153 | static void dump_leak(void) |
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162 | 154 | { |
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163 | 155 | static int dump; |
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.. | .. |
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166 | 158 | return; |
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167 | 159 | dump = 1; |
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168 | 160 | |
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169 | | - show_stack(NULL, NULL); |
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| 161 | + show_stack(NULL, NULL, KERN_ERR); |
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170 | 162 | debug_dma_dump_mappings(NULL); |
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171 | 163 | } |
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172 | 164 | #endif |
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.. | .. |
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184 | 176 | */ |
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185 | 177 | |
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186 | 178 | dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size); |
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187 | | - |
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188 | | - if (size > PAGE_SIZE*EMERGENCY_PAGES) { |
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189 | | - if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL) |
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190 | | - panic("PCI-DMA: Memory would be corrupted\n"); |
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191 | | - if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL) |
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192 | | - panic(KERN_ERR |
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193 | | - "PCI-DMA: Random memory would be DMAed\n"); |
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194 | | - } |
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195 | 179 | #ifdef CONFIG_IOMMU_LEAK |
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196 | 180 | dump_leak(); |
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197 | 181 | #endif |
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.. | .. |
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200 | 184 | static inline int |
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201 | 185 | need_iommu(struct device *dev, unsigned long addr, size_t size) |
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202 | 186 | { |
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203 | | - return force_iommu || !dma_capable(dev, addr, size); |
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| 187 | + return force_iommu || !dma_capable(dev, addr, size, true); |
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204 | 188 | } |
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205 | 189 | |
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206 | 190 | static inline int |
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207 | 191 | nonforced_iommu(struct device *dev, unsigned long addr, size_t size) |
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208 | 192 | { |
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209 | | - return !dma_capable(dev, addr, size); |
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| 193 | + return !dma_capable(dev, addr, size, true); |
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210 | 194 | } |
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211 | 195 | |
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212 | 196 | /* Map a single continuous physical area into the IOMMU. |
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.. | .. |
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220 | 204 | int i; |
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221 | 205 | |
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222 | 206 | if (unlikely(phys_mem + size > GART_MAX_PHYS_ADDR)) |
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223 | | - return bad_dma_addr; |
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| 207 | + return DMA_MAPPING_ERROR; |
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224 | 208 | |
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225 | 209 | iommu_page = alloc_iommu(dev, npages, align_mask); |
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226 | 210 | if (iommu_page == -1) { |
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.. | .. |
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229 | 213 | if (panic_on_overflow) |
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230 | 214 | panic("dma_map_area overflow %lu bytes\n", size); |
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231 | 215 | iommu_full(dev, size, dir); |
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232 | | - return bad_dma_addr; |
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| 216 | + return DMA_MAPPING_ERROR; |
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233 | 217 | } |
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234 | 218 | |
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235 | 219 | for (i = 0; i < npages; i++) { |
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.. | .. |
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247 | 231 | { |
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248 | 232 | unsigned long bus; |
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249 | 233 | phys_addr_t paddr = page_to_phys(page) + offset; |
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250 | | - |
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251 | | - if (!dev) |
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252 | | - dev = &x86_dma_fallback_dev; |
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253 | 234 | |
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254 | 235 | if (!need_iommu(dev, paddr, size)) |
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255 | 236 | return paddr; |
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.. | .. |
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271 | 252 | int npages; |
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272 | 253 | int i; |
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273 | 254 | |
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274 | | - if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE || |
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| 255 | + if (WARN_ON_ONCE(dma_addr == DMA_MAPPING_ERROR)) |
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| 256 | + return; |
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| 257 | + |
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| 258 | + /* |
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| 259 | + * This driver will not always use a GART mapping, but might have |
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| 260 | + * created a direct mapping instead. If that is the case there is |
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| 261 | + * nothing to unmap here. |
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| 262 | + */ |
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| 263 | + if (dma_addr < iommu_bus_base || |
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275 | 264 | dma_addr >= iommu_bus_base + iommu_size) |
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276 | 265 | return; |
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277 | 266 | |
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.. | .. |
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315 | 304 | |
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316 | 305 | if (nonforced_iommu(dev, addr, s->length)) { |
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317 | 306 | addr = dma_map_area(dev, addr, s->length, dir, 0); |
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318 | | - if (addr == bad_dma_addr) { |
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| 307 | + if (addr == DMA_MAPPING_ERROR) { |
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319 | 308 | if (i > 0) |
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320 | 309 | gart_unmap_sg(dev, sg, i, dir, 0); |
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321 | 310 | nents = 0; |
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.. | .. |
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399 | 388 | if (nents == 0) |
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400 | 389 | return 0; |
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401 | 390 | |
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402 | | - if (!dev) |
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403 | | - dev = &x86_dma_fallback_dev; |
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404 | | - |
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405 | 391 | out = 0; |
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406 | 392 | start = 0; |
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407 | 393 | start_sg = sg; |
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.. | .. |
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471 | 457 | |
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472 | 458 | iommu_full(dev, pages << PAGE_SHIFT, dir); |
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473 | 459 | for_each_sg(sg, s, nents, i) |
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474 | | - s->dma_address = bad_dma_addr; |
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| 460 | + s->dma_address = DMA_MAPPING_ERROR; |
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475 | 461 | return 0; |
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476 | 462 | } |
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477 | 463 | |
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.. | .. |
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490 | 476 | *dma_addr = dma_map_area(dev, virt_to_phys(vaddr), size, |
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491 | 477 | DMA_BIDIRECTIONAL, (1UL << get_order(size)) - 1); |
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492 | 478 | flush_gart(); |
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493 | | - if (unlikely(*dma_addr == bad_dma_addr)) |
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| 479 | + if (unlikely(*dma_addr == DMA_MAPPING_ERROR)) |
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494 | 480 | goto out_free; |
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495 | 481 | return vaddr; |
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496 | 482 | out_free: |
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.. | .. |
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505 | 491 | { |
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506 | 492 | gart_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL, 0); |
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507 | 493 | dma_direct_free(dev, size, vaddr, dma_addr, attrs); |
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508 | | -} |
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509 | | - |
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510 | | -static int gart_mapping_error(struct device *dev, dma_addr_t dma_addr) |
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511 | | -{ |
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512 | | - return (dma_addr == bad_dma_addr); |
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513 | 494 | } |
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514 | 495 | |
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515 | 496 | static int no_agp; |
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.. | .. |
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528 | 509 | iommu_size -= round_up(a, PMD_PAGE_SIZE) - a; |
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529 | 510 | |
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530 | 511 | if (iommu_size < 64*1024*1024) { |
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531 | | - pr_warning( |
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532 | | - "PCI-DMA: Warning: Small IOMMU %luMB." |
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| 512 | + pr_warn("PCI-DMA: Warning: Small IOMMU %luMB." |
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533 | 513 | " Consider increasing the AGP aperture in BIOS\n", |
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534 | | - iommu_size >> 20); |
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| 514 | + iommu_size >> 20); |
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535 | 515 | } |
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536 | 516 | |
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537 | 517 | return iommu_size; |
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.. | .. |
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683 | 663 | |
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684 | 664 | nommu: |
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685 | 665 | /* Should not happen anymore */ |
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686 | | - pr_warning("PCI-DMA: More than 4GB of RAM and no IOMMU\n" |
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687 | | - "falling back to iommu=soft.\n"); |
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| 666 | + pr_warn("PCI-DMA: More than 4GB of RAM and no IOMMU - falling back to iommu=soft.\n"); |
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688 | 667 | return -1; |
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689 | 668 | } |
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690 | 669 | |
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.. | .. |
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695 | 674 | .unmap_page = gart_unmap_page, |
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696 | 675 | .alloc = gart_alloc_coherent, |
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697 | 676 | .free = gart_free_coherent, |
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698 | | - .mapping_error = gart_mapping_error, |
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| 677 | + .mmap = dma_common_mmap, |
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| 678 | + .get_sgtable = dma_common_get_sgtable, |
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699 | 679 | .dma_supported = dma_direct_supported, |
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| 680 | + .get_required_mask = dma_direct_get_required_mask, |
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| 681 | + .alloc_pages = dma_direct_alloc_pages, |
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| 682 | + .free_pages = dma_direct_free_pages, |
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700 | 683 | }; |
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701 | 684 | |
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702 | 685 | static void gart_iommu_shutdown(void) |
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.. | .. |
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730 | 713 | unsigned long aper_base, aper_size; |
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731 | 714 | unsigned long start_pfn, end_pfn; |
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732 | 715 | unsigned long scratch; |
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733 | | - long i; |
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734 | 716 | |
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735 | 717 | if (!amd_nb_has_feature(AMD_NB_GART)) |
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736 | 718 | return 0; |
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.. | .. |
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750 | 732 | !gart_iommu_aperture || |
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751 | 733 | (no_agp && init_amd_gatt(&info) < 0)) { |
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752 | 734 | if (max_pfn > MAX_DMA32_PFN) { |
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753 | | - pr_warning("More than 4GB of memory but GART IOMMU not available.\n"); |
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754 | | - pr_warning("falling back to iommu=soft.\n"); |
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| 735 | + pr_warn("More than 4GB of memory but GART IOMMU not available.\n"); |
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| 736 | + pr_warn("falling back to iommu=soft.\n"); |
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755 | 737 | } |
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756 | 738 | return 0; |
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757 | 739 | } |
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.. | .. |
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763 | 745 | |
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764 | 746 | start_pfn = PFN_DOWN(aper_base); |
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765 | 747 | if (!pfn_range_is_mapped(start_pfn, end_pfn)) |
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766 | | - init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT); |
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| 748 | + init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT, |
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| 749 | + PAGE_KERNEL); |
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767 | 750 | |
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768 | 751 | pr_info("PCI-DMA: using GART IOMMU.\n"); |
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769 | 752 | iommu_size = check_iommu_size(info.aper_base, aper_size); |
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.. | .. |
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774 | 757 | if (!iommu_gart_bitmap) |
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775 | 758 | panic("Cannot allocate iommu bitmap\n"); |
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776 | 759 | |
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777 | | -#ifdef CONFIG_IOMMU_LEAK |
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778 | | - if (leak_trace) { |
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779 | | - int ret; |
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780 | | - |
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781 | | - ret = dma_debug_resize_entries(iommu_pages); |
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782 | | - if (ret) |
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783 | | - pr_debug("PCI-DMA: Cannot trace all the entries\n"); |
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784 | | - } |
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785 | | -#endif |
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786 | | - |
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787 | | - /* |
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788 | | - * Out of IOMMU space handling. |
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789 | | - * Reserve some invalid pages at the beginning of the GART. |
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790 | | - */ |
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791 | | - bitmap_set(iommu_gart_bitmap, 0, EMERGENCY_PAGES); |
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792 | | - |
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793 | 760 | pr_info("PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n", |
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794 | 761 | iommu_size >> 20); |
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795 | 762 | |
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796 | 763 | agp_memory_reserved = iommu_size; |
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797 | 764 | iommu_start = aper_size - iommu_size; |
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798 | 765 | iommu_bus_base = info.aper_base + iommu_start; |
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799 | | - bad_dma_addr = iommu_bus_base; |
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800 | 766 | iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT); |
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801 | 767 | |
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802 | 768 | /* |
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.. | .. |
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838 | 804 | if (!scratch) |
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839 | 805 | panic("Cannot allocate iommu scratch page"); |
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840 | 806 | gart_unmapped_entry = GPTE_ENCODE(__pa(scratch)); |
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841 | | - for (i = EMERGENCY_PAGES; i < iommu_pages; i++) |
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842 | | - iommu_gatt_base[i] = gart_unmapped_entry; |
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843 | 807 | |
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844 | 808 | flush_gart(); |
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845 | 809 | dma_ops = &gart_dma_ops; |
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.. | .. |
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853 | 817 | { |
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854 | 818 | int arg; |
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855 | 819 | |
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856 | | -#ifdef CONFIG_IOMMU_LEAK |
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857 | | - if (!strncmp(p, "leak", 4)) { |
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858 | | - leak_trace = 1; |
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859 | | - p += 4; |
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860 | | - if (*p == '=') |
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861 | | - ++p; |
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862 | | - if (isdigit(*p) && get_option(&p, &arg)) |
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863 | | - iommu_leak_pages = arg; |
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864 | | - } |
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865 | | -#endif |
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866 | 820 | if (isdigit(*p) && get_option(&p, &arg)) |
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867 | 821 | iommu_size = arg; |
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868 | 822 | if (!strncmp(p, "fullflush", 9)) |
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