rtl88x2CE_WiFi_linux driver

hc

2024-05-10 cde9070d9970eef1f7ec2360586c802a16230ad8

 kernel/arch/mips/include/asm/cpu-features.h
..
..
@@ -15,6 +15,7 @@
15
15
 #include <cpu-feature-overrides.h>
16
16
 
17
17
 #define __ase(ase)			(cpu_data[0].ases & (ase))
18
+#define __isa(isa)			(cpu_data[0].isa_level & (isa))
18
19
 #define __opt(opt)			(cpu_data[0].options & (opt))
19
20
 
20
21
 /*
..
..
@@ -51,6 +52,20 @@
51
52
  */
52
53
 #define __isa_lt_and_ase(isa, ase)	((MIPS_ISA_REV < (isa)) && __ase(ase))
53
54
 #define __isa_lt_and_opt(isa, opt)	((MIPS_ISA_REV < (isa)) && __opt(opt))
55
+
56
+/*
57
+ * Similarly allow for ISA level checks that take into account knowledge of the
58
+ * ISA targeted by the kernel build, provided by MIPS_ISA_REV.
59
+ */
60
+#define __isa_ge_and_flag(isa, flag)	((MIPS_ISA_REV >= (isa)) && __isa(flag))
61
+#define __isa_ge_or_flag(isa, flag)	((MIPS_ISA_REV >= (isa)) || __isa(flag))
62
+#define __isa_lt_and_flag(isa, flag)	((MIPS_ISA_REV < (isa)) && __isa(flag))
63
+#define __isa_range(ge, lt) \
64
+	((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt)))
65
+#define __isa_range_or_flag(ge, lt, flag) \
66
+	(__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag)))
67
+#define __isa_range_and_ase(ge, lt, ase) \
68
+	(__isa_range(ge, lt) && __ase(ase))
54
69
 
55
70
 /*
56
71
  * SMP assumption: Options of CPU 0 are a superset of all processors.
..
..
@@ -111,14 +126,36 @@
111
126
 #define cpu_has_tx39_cache	__opt(MIPS_CPU_TX39_CACHE)
112
127
 #endif
113
128
 #ifndef cpu_has_octeon_cache
114
-#define cpu_has_octeon_cache	0
129
+#define cpu_has_octeon_cache						\
130
+({									\
131
+	int __res;							\
132
+									\
133
+	switch (boot_cpu_type()) {					\
134
+	case CPU_CAVIUM_OCTEON:						\
135
+	case CPU_CAVIUM_OCTEON_PLUS:					\
136
+	case CPU_CAVIUM_OCTEON2:					\
137
+	case CPU_CAVIUM_OCTEON3:					\
138
+		__res = 1;						\
139
+		break;							\
140
+									\
141
+	default:							\
142
+		__res = 0;						\
143
+	}								\
144
+									\
145
+	__res;								\
146
+})
115
147
 #endif
116
148
 /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work.  */
117
149
 #ifndef cpu_has_fpu
118
-#define cpu_has_fpu		(current_cpu_data.options & MIPS_CPU_FPU)
119
-#define raw_cpu_has_fpu		(raw_current_cpu_data.options & MIPS_CPU_FPU)
150
+# ifdef CONFIG_MIPS_FP_SUPPORT
151
+#  define cpu_has_fpu		(current_cpu_data.options & MIPS_CPU_FPU)
152
+#  define raw_cpu_has_fpu	(raw_current_cpu_data.options & MIPS_CPU_FPU)
153
+# else
154
+#  define cpu_has_fpu		0
155
+#  define raw_cpu_has_fpu	0
156
+# endif
120
157
 #else
121
-#define raw_cpu_has_fpu		cpu_has_fpu
158
+# define raw_cpu_has_fpu	cpu_has_fpu
122
159
 #endif
123
160
 #ifndef cpu_has_32fpr
124
161
 #define cpu_has_32fpr		__isa_ge_or_opt(1, MIPS_CPU_32FPR)
..
..
@@ -152,9 +189,6 @@
152
189
 #endif
153
190
 #ifndef cpu_has_llsc
154
191
 #define cpu_has_llsc		__isa_ge_or_opt(1, MIPS_CPU_LLSC)
155
-#endif
156
-#ifndef cpu_has_bp_ghist
157
-#define cpu_has_bp_ghist	__opt(MIPS_CPU_BP_GHIST)
158
192
 #endif
159
193
 #ifndef kernel_uses_llsc
160
194
 #define kernel_uses_llsc	cpu_has_llsc
..
..
@@ -195,7 +229,9 @@
195
229
 #endif
196
230
 
197
231
 #ifndef cpu_has_mmips
198
-# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
232
+# if defined(__mips_micromips)
233
+#  define cpu_has_mmips		1
234
+# elif defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
199
235
 #  define cpu_has_mmips		__opt(MIPS_CPU_MICROMIPS)
200
236
 # else
201
237
 #  define cpu_has_mmips		0
..
..
@@ -223,9 +259,6 @@
223
259
 #ifndef cpu_has_pindexed_dcache
224
260
 #define cpu_has_pindexed_dcache	(cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
225
261
 #endif
226
-#ifndef cpu_has_local_ebase
227
-#define cpu_has_local_ebase	1
228
-#endif
229
262
 
230
263
 /*
231
264
  * I-Cache snoops remote store.	 This only matters on SMP.  Some multiprocessors
..
..
@@ -246,48 +279,47 @@
246
279
 #endif
247
280
 #endif
248
281
 
249
-/* __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r */
250
-#if !((defined(cpu_has_mips32r1) && cpu_has_mips32r1) || \
251
-	  (defined(cpu_has_mips32r2) && cpu_has_mips32r2) || \
252
-	  (defined(cpu_has_mips32r6) && cpu_has_mips32r6) || \
253
-	  (defined(cpu_has_mips64r1) && cpu_has_mips64r1) || \
254
-	  (defined(cpu_has_mips64r2) && cpu_has_mips64r2) || \
255
-	  (defined(cpu_has_mips64r6) && cpu_has_mips64r6))
256
-#define CPU_NO_EFFICIENT_FFS 1
257
-#endif
258
-
259
282
 #ifndef cpu_has_mips_1
260
-# define cpu_has_mips_1		(!cpu_has_mips_r6)
283
+# define cpu_has_mips_1		(MIPS_ISA_REV < 6)
261
284
 #endif
262
285
 #ifndef cpu_has_mips_2
263
-# define cpu_has_mips_2		(cpu_data[0].isa_level & MIPS_CPU_ISA_II)
286
+# define cpu_has_mips_2		__isa_lt_and_flag(6, MIPS_CPU_ISA_II)
264
287
 #endif
265
288
 #ifndef cpu_has_mips_3
266
-# define cpu_has_mips_3		(cpu_data[0].isa_level & MIPS_CPU_ISA_III)
289
+# define cpu_has_mips_3		__isa_lt_and_flag(6, MIPS_CPU_ISA_III)
267
290
 #endif
268
291
 #ifndef cpu_has_mips_4
269
-# define cpu_has_mips_4		(cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
292
+# define cpu_has_mips_4		__isa_lt_and_flag(6, MIPS_CPU_ISA_IV)
270
293
 #endif
271
294
 #ifndef cpu_has_mips_5
272
-# define cpu_has_mips_5		(cpu_data[0].isa_level & MIPS_CPU_ISA_V)
295
+# define cpu_has_mips_5		__isa_lt_and_flag(6, MIPS_CPU_ISA_V)
273
296
 #endif
274
297
 #ifndef cpu_has_mips32r1
275
-# define cpu_has_mips32r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
298
+# define cpu_has_mips32r1	__isa_range_or_flag(1, 6, MIPS_CPU_ISA_M32R1)
276
299
 #endif
277
300
 #ifndef cpu_has_mips32r2
278
-# define cpu_has_mips32r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
301
+# define cpu_has_mips32r2	__isa_range_or_flag(2, 6, MIPS_CPU_ISA_M32R2)
302
+#endif
303
+#ifndef cpu_has_mips32r5
304
+# define cpu_has_mips32r5	__isa_range_or_flag(5, 6, MIPS_CPU_ISA_M32R5)
279
305
 #endif
280
306
 #ifndef cpu_has_mips32r6
281
-# define cpu_has_mips32r6	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
307
+# define cpu_has_mips32r6	__isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6)
282
308
 #endif
283
309
 #ifndef cpu_has_mips64r1
284
-# define cpu_has_mips64r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
310
+# define cpu_has_mips64r1	(cpu_has_64bits && \
311
+				 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1))
285
312
 #endif
286
313
 #ifndef cpu_has_mips64r2
287
-# define cpu_has_mips64r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
314
+# define cpu_has_mips64r2	(cpu_has_64bits && \
315
+				 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2))
316
+#endif
317
+#ifndef cpu_has_mips64r5
318
+# define cpu_has_mips64r5	(cpu_has_64bits && \
319
+				 __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M64R5))
288
320
 #endif
289
321
 #ifndef cpu_has_mips64r6
290
-# define cpu_has_mips64r6	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6)
322
+# define cpu_has_mips64r6	__isa_ge_and_flag(6, MIPS_CPU_ISA_M64R6)
291
323
 #endif
292
324
 
293
325
 /*
..
..
@@ -306,19 +338,25 @@
306
338
 				(cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
307
339
 #define cpu_has_mips_4_5_64_r2_r6					\
308
340
 				(cpu_has_mips_4_5 | cpu_has_mips64r1 |	\
309
-				 cpu_has_mips_r2 | cpu_has_mips_r6)
341
+				 cpu_has_mips_r2 | cpu_has_mips_r5 | \
342
+				 cpu_has_mips_r6)
310
343
 
311
-#define cpu_has_mips32	(cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
312
-#define cpu_has_mips64	(cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
344
+#define cpu_has_mips32	(cpu_has_mips32r1 | cpu_has_mips32r2 | \
345
+			 cpu_has_mips32r5 | cpu_has_mips32r6)
346
+#define cpu_has_mips64	(cpu_has_mips64r1 | cpu_has_mips64r2 | \
347
+			 cpu_has_mips64r5 | cpu_has_mips64r6)
313
348
 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
314
349
 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
350
+#define cpu_has_mips_r5	(cpu_has_mips32r5 | cpu_has_mips64r5)
315
351
 #define cpu_has_mips_r6	(cpu_has_mips32r6 | cpu_has_mips64r6)
316
352
 #define cpu_has_mips_r	(cpu_has_mips32r1 | cpu_has_mips32r2 | \
317
-			 cpu_has_mips32r6 | cpu_has_mips64r1 | \
318
-			 cpu_has_mips64r2 | cpu_has_mips64r6)
353
+			 cpu_has_mips32r5 | cpu_has_mips32r6 | \
354
+			 cpu_has_mips64r1 | cpu_has_mips64r2 | \
355
+			 cpu_has_mips64r5 | cpu_has_mips64r6)
319
356
 
320
-/* MIPSR2 and MIPSR6 have a lot of similarities */
321
-#define cpu_has_mips_r2_r6	(cpu_has_mips_r2 | cpu_has_mips_r6)
357
+/* MIPSR2 - MIPSR6 have a lot of similarities */
358
+#define cpu_has_mips_r2_r6	(cpu_has_mips_r2 | cpu_has_mips_r5 | \
359
+				 cpu_has_mips_r6)
322
360
 
323
361
 /*
324
362
  * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
..
..
@@ -332,7 +370,7 @@
332
370
 ({									\
333
371
 	int __res;							\
334
372
 									\
335
-	switch (current_cpu_type()) {					\
373
+	switch (boot_cpu_type()) {					\
336
374
 	case CPU_M14KC:							\
337
375
 	case CPU_74K:							\
338
376
 	case CPU_1074K:							\
..
..
@@ -404,7 +442,7 @@
404
442
 #endif
405
443
 
406
444
 #ifndef cpu_has_mipsmt
407
-#define cpu_has_mipsmt		__isa_lt_and_ase(6, MIPS_ASE_MIPSMT)
445
+#define cpu_has_mipsmt		__isa_range_and_ase(2, 6, MIPS_ASE_MIPSMT)
408
446
 #endif
409
447
 
410
448
 #ifndef cpu_has_vp
..
..
@@ -428,9 +466,6 @@
428
466
 # ifndef cpu_has_64bit_gp_regs
429
467
 # define cpu_has_64bit_gp_regs		0
430
468
 # endif
431
-# ifndef cpu_has_64bit_addresses
432
-# define cpu_has_64bit_addresses	0
433
-# endif
434
469
 # ifndef cpu_vmbits
435
470
 # define cpu_vmbits 31
436
471
 # endif
..
..
@@ -448,9 +483,6 @@
448
483
 # endif
449
484
 # ifndef cpu_has_64bit_gp_regs
450
485
 # define cpu_has_64bit_gp_regs		1
451
-# endif
452
-# ifndef cpu_has_64bit_addresses
453
-# define cpu_has_64bit_addresses	1
454
486
 # endif
455
487
 # ifndef cpu_vmbits
456
488
 # define cpu_vmbits cpu_data[0].vmbits
..
..
@@ -548,6 +580,18 @@
548
580
 # define cpu_has_perf		__opt(MIPS_CPU_PERF)
549
581
 #endif
550
582
 
583
+#ifndef cpu_has_mac2008_only
584
+# define cpu_has_mac2008_only	__opt(MIPS_CPU_MAC_2008_ONLY)
585
+#endif
586
+
587
+#ifndef cpu_has_ftlbparex
588
+# define cpu_has_ftlbparex	__opt(MIPS_CPU_FTLBPAREX)
589
+#endif
590
+
591
+#ifndef cpu_has_gsexcex
592
+# define cpu_has_gsexcex	__opt(MIPS_CPU_GSEXCEX)
593
+#endif
594
+
551
595
 #ifdef CONFIG_SMP
552
596
 /*
553
597
  * Some systems share FTLB RAMs between threads within a core (siblings in
..
..
@@ -597,6 +641,27 @@
597
641
 #endif /* CONFIG_MIPS_MT_SMP */
598
642
 
599
643
 /*
644
+ * We only enable MMID support for configurations which natively support 64 bit
645
+ * atomics because getting good performance from the allocator relies upon
646
+ * efficient atomic64_*() functions.
647
+ */
648
+#ifndef cpu_has_mmid
649
+# ifdef CONFIG_GENERIC_ATOMIC64
650
+#  define cpu_has_mmid		0
651
+# else
652
+#  define cpu_has_mmid		__isa_ge_and_opt(6, MIPS_CPU_MMID)
653
+# endif
654
+#endif
655
+
656
+#ifndef cpu_has_mm_sysad
657
+# define cpu_has_mm_sysad	__opt(MIPS_CPU_MM_SYSAD)
658
+#endif
659
+
660
+#ifndef cpu_has_mm_full
661
+# define cpu_has_mm_full	__opt(MIPS_CPU_MM_FULL)
662
+#endif
663
+
664
+/*
600
665
  * Guest capabilities
601
666
  */
602
667
 #ifndef cpu_guest_has_conf1
..
..
@@ -641,6 +706,9 @@
641
706
 #ifndef cpu_guest_has_htw
642
707
 #define cpu_guest_has_htw	(cpu_data[0].guest.options & MIPS_CPU_HTW)
643
708
 #endif
709
+#ifndef cpu_guest_has_ldpte
710
+#define cpu_guest_has_ldpte	(cpu_data[0].guest.options & MIPS_CPU_LDPTE)
711
+#endif
644
712
 #ifndef cpu_guest_has_mvh
645
713
 #define cpu_guest_has_mvh	(cpu_data[0].guest.options & MIPS_CPU_MVH)
646
714
 #endif