rtl88x2CE_WiFi_linux driver

hc

2024-05-10 cde9070d9970eef1f7ec2360586c802a16230ad8

 kernel/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
..
..
@@ -31,6 +31,7 @@
31
31
  * network ports from the rest of the cvmx-helper files.
32
32
  */
33
33
 
34
+#include <linux/bug.h>
34
35
 #include <asm/octeon/octeon.h>
35
36
 #include <asm/octeon/cvmx-bootinfo.h>
36
37
 
..
..
@@ -206,60 +207,22 @@
206
207
  * Returns The ports link status. If the link isn't fully resolved, this must
207
208
  *	   return zero.
208
209
  */
209
-cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
210
+union cvmx_helper_link_info __cvmx_helper_board_link_get(int ipd_port)
210
211
 {
211
-	cvmx_helper_link_info_t result;
212
+	union cvmx_helper_link_info result;
213
+
214
+	WARN_ONCE(!octeon_is_simulation(),
215
+	     "Using deprecated link status - please update your DT");
212
216
 
213
217
 	/* Unless we fix it later, all links are defaulted to down */
214
218
 	result.u64 = 0;
215
219
 
216
-	/*
217
-	 * This switch statement should handle all ports that either don't use
218
-	 * Marvell PHYS, or don't support in-band status.
219
-	 */
220
-	switch (cvmx_sysinfo_get()->board_type) {
221
-	case CVMX_BOARD_TYPE_SIM:
220
+	if (octeon_is_simulation()) {
222
221
 		/* The simulator gives you a simulated 1Gbps full duplex link */
223
222
 		result.s.link_up = 1;
224
223
 		result.s.full_duplex = 1;
225
224
 		result.s.speed = 1000;
226
225
 		return result;
227
-	case CVMX_BOARD_TYPE_EBH3100:
228
-	case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
229
-	case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
230
-	case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
231
-		/* Port 1 on these boards is always Gigabit */
232
-		if (ipd_port == 1) {
233
-			result.s.link_up = 1;
234
-			result.s.full_duplex = 1;
235
-			result.s.speed = 1000;
236
-			return result;
237
-		}
238
-		/* Fall through to the generic code below */
239
-		break;
240
-	case CVMX_BOARD_TYPE_CUST_NB5:
241
-		/* Port 1 on these boards is always Gigabit */
242
-		if (ipd_port == 1) {
243
-			result.s.link_up = 1;
244
-			result.s.full_duplex = 1;
245
-			result.s.speed = 1000;
246
-			return result;
247
-		}
248
-		break;
249
-	case CVMX_BOARD_TYPE_BBGW_REF:
250
-		/* Port 1 on these boards is always Gigabit */
251
-		if (ipd_port == 2) {
252
-			/* Port 2 is not hooked up */
253
-			result.u64 = 0;
254
-			return result;
255
-		} else {
256
-			/* Ports 0 and 1 connect to the switch */
257
-			result.s.link_up = 1;
258
-			result.s.full_duplex = 1;
259
-			result.s.speed = 1000;
260
-			return result;
261
-		}
262
-		break;
263
226
 	}
264
227
 
265
228
 	if (OCTEON_IS_MODEL(OCTEON_CN3XXX)
..
..
@@ -355,45 +318,6 @@
355
318
 		break;
356
319
 	}
357
320
 	return supported_ports;
358
-}
359
-
360
-/**
361
- * Enable packet input/output from the hardware. This function is
362
- * called after by cvmx_helper_packet_hardware_enable() to
363
- * perform board specific initialization. For most boards
364
- * nothing is needed.
365
- *
366
- * @interface: Interface to enable
367
- *
368
- * Returns Zero on success, negative on failure
369
- */
370
-int __cvmx_helper_board_hardware_enable(int interface)
371
-{
372
-	if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5) {
373
-		if (interface == 0) {
374
-			/* Different config for switch port */
375
-			cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0);
376
-			cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0);
377
-			/*
378
-			 * Boards with gigabit WAN ports need a
379
-			 * different setting that is compatible with
380
-			 * 100 Mbit settings
381
-			 */
382
-			cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface),
383
-				       0xc);
384
-			cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface),
385
-				       0xc);
386
-		}
387
-	} else if (cvmx_sysinfo_get()->board_type ==
388
-			CVMX_BOARD_TYPE_UBNT_E100) {
389
-		cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 0);
390
-		cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 0x10);
391
-		cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0);
392
-		cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0x10);
393
-		cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(2, interface), 0);
394
-		cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(2, interface), 0x10);
395
-	}
396
-	return 0;
397
321
 }
398
322
 
399
323
 /**