~hc/RK356X_SDK_RELEASE.git

..	..	@@ -8,10 +8,10 @@
8	8	#include <dt-bindings/interrupt-controller/arm-gic.h>
9	9	#include <dt-bindings/interrupt-controller/irq.h>
10	10	#include <dt-bindings/pinctrl/rockchip.h>
11		-#include <dt-bindings/soc/rockchip-system-status.h>
12		-#include <dt-bindings/suspend/rockchip-rk3328.h>
13	11	#include <dt-bindings/power/rk3328-power.h>
14	12	#include <dt-bindings/soc/rockchip,boot-mode.h>
	13	+#include <dt-bindings/soc/rockchip-system-status.h>
	14	+#include <dt-bindings/suspend/rockchip-rk3328.h>
15	15	#include <dt-bindings/thermal/thermal.h>
16	16	#include "rk3328-dram-default-timing.dtsi"
17	17
..	..	@@ -25,6 +25,10 @@
25	25	aliases {
26	26	ethernet0 = &gmac2io;
27	27	ethernet1 = &gmac2phy;
	28	+ gpio0 = &gpio0;
	29	+ gpio1 = &gpio1;
	30	+ gpio2 = &gpio2;
	31	+ gpio3 = &gpio3;
28	32	i2c0 = &i2c0;
29	33	i2c1 = &i2c1;
30	34	i2c2 = &i2c2;
..	..	@@ -40,10 +44,11 @@
40	44
41	45	cpu0: cpu@0 {
42	46	device_type = "cpu";
43		- compatible = "arm,cortex-a53", "arm,armv8";
	47	+ compatible = "arm,cortex-a53";
44	48	reg = <0x0 0x0>;
45	49	clocks = <&cru ARMCLK>;
46	50	#cooling-cells = <2>;
	51	+ cpu-idle-states = <&CPU_SLEEP>;
47	52	dynamic-power-coefficient = <120>;
48	53	enable-method = "psci";
49	54	next-level-cache = <&l2>;
..	..	@@ -52,10 +57,11 @@
52	57
53	58	cpu1: cpu@1 {
54	59	device_type = "cpu";
55		- compatible = "arm,cortex-a53", "arm,armv8";
	60	+ compatible = "arm,cortex-a53";
56	61	reg = <0x0 0x1>;
57	62	clocks = <&cru ARMCLK>;
58	63	#cooling-cells = <2>;
	64	+ cpu-idle-states = <&CPU_SLEEP>;
59	65	dynamic-power-coefficient = <120>;
60	66	enable-method = "psci";
61	67	next-level-cache = <&l2>;
..	..	@@ -64,10 +70,11 @@
64	70
65	71	cpu2: cpu@2 {
66	72	device_type = "cpu";
67		- compatible = "arm,cortex-a53", "arm,armv8";
	73	+ compatible = "arm,cortex-a53";
68	74	reg = <0x0 0x2>;
69	75	clocks = <&cru ARMCLK>;
70	76	#cooling-cells = <2>;
	77	+ cpu-idle-states = <&CPU_SLEEP>;
71	78	dynamic-power-coefficient = <120>;
72	79	enable-method = "psci";
73	80	next-level-cache = <&l2>;
..	..	@@ -76,14 +83,28 @@
76	83
77	84	cpu3: cpu@3 {
78	85	device_type = "cpu";
79		- compatible = "arm,cortex-a53", "arm,armv8";
	86	+ compatible = "arm,cortex-a53";
80	87	reg = <0x0 0x3>;
81	88	clocks = <&cru ARMCLK>;
82	89	#cooling-cells = <2>;
	90	+ cpu-idle-states = <&CPU_SLEEP>;
83	91	dynamic-power-coefficient = <120>;
84	92	enable-method = "psci";
85	93	next-level-cache = <&l2>;
86	94	operating-points-v2 = <&cpu0_opp_table>;
	95	+ };
	96	+
	97	+ idle-states {
	98	+ entry-method = "psci";
	99	+
	100	+ CPU_SLEEP: cpu-sleep {
	101	+ compatible = "arm,idle-state";
	102	+ local-timer-stop;
	103	+ arm,psci-suspend-param = <0x0010000>;
	104	+ entry-latency-us = <120>;
	105	+ exit-latency-us = <250>;
	106	+ min-residency-us = <900>;
	107	+ };
87	108	};
88	109
89	110	l2: l2-cache0 {
..	..	@@ -149,21 +170,101 @@
149	170	};
150	171	};
151	172
152		- amba {
153		- compatible = "simple-bus";
154		- #address-cells = <2>;
155		- #size-cells = <2>;
156		- ranges;
	173	+ dmc: dmc {
	174	+ compatible = "rockchip,rk3328-dmc";
	175	+ devfreq-events = <&dfi>;
	176	+ clocks = <&cru SCLK_DDRCLK>;
	177	+ clock-names = "dmc_clk";
	178	+ operating-points-v2 = <&dmc_opp_table>;
	179	+ ddr_timing = <&ddr_timing>;
	180	+ upthreshold = <40>;
	181	+ downdifferential = <20>;
	182	+ system-status-freq = <
	183	+ /system status freq(KHz)/
	184	+ SYS_STATUS_NORMAL 786000
	185	+ SYS_STATUS_REBOOT 786000
	186	+ SYS_STATUS_SUSPEND 786000
	187	+ SYS_STATUS_VIDEO_1080P 786000
	188	+ SYS_STATUS_VIDEO_4K 786000
	189	+ SYS_STATUS_VIDEO_4K_10B 924000
	190	+ SYS_STATUS_PERFORMANCE 924000
	191	+ SYS_STATUS_BOOST 924000
	192	+ >;
	193	+ auto-min-freq = <786000>;
	194	+ auto-freq-en = <0>;
	195	+ #cooling-cells = <2>;
	196	+ status = "disabled";
	197	+ };
157	198
158		- dmac: dmac@ff1f0000 {
159		- compatible = "arm,pl330", "arm,primecell";
160		- reg = <0x0 0xff1f0000 0x0 0x4000>;
161		- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
162		- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
163		- clocks = <&cru ACLK_DMAC>;
164		- clock-names = "apb_pclk";
165		- #dma-cells = <1>;
166		- arm,pl330-periph-burst;
	199	+ dmc_opp_table: dmc-opp-table {
	200	+ compatible = "operating-points-v2";
	201	+ rockchip,leakage-voltage-sel = <
	202	+ 1 10 0
	203	+ 11 254 1
	204	+ >;
	205	+ nvmem-cells = <&logic_leakage>;
	206	+ nvmem-cell-names = "ddr_leakage";
	207	+
	208	+ opp-400000000 {
	209	+ opp-hz = /bits/ 64 <400000000>;
	210	+ opp-microvolt = <950000>;
	211	+ opp-microvolt-L0 = <950000>;
	212	+ opp-microvolt-L1 = <950000>;
	213	+ status = "disabled";
	214	+ };
	215	+ opp-600000000 {
	216	+ opp-hz = /bits/ 64 <600000000>;
	217	+ opp-microvolt = <1025000>;
	218	+ opp-microvolt-L0 = <1025000>;
	219	+ opp-microvolt-L1 = <1000000>;
	220	+ status = "disabled";
	221	+ };
	222	+ opp-786000000 {
	223	+ opp-hz = /bits/ 64 <786000000>;
	224	+ opp-microvolt = <1075000>;
	225	+ opp-microvolt-L0 = <1075000>;
	226	+ opp-microvolt-L1 = <1050000>;
	227	+ };
	228	+ opp-798000000 {
	229	+ opp-hz = /bits/ 64 <798000000>;
	230	+ opp-microvolt = <1075000>;
	231	+ opp-microvolt-L0 = <1075000>;
	232	+ opp-microvolt-L1 = <1050000>;
	233	+ };
	234	+ opp-840000000 {
	235	+ opp-hz = /bits/ 64 <840000000>;
	236	+ opp-microvolt = <1075000>;
	237	+ opp-microvolt-L0 = <1075000>;
	238	+ opp-microvolt-L1 = <1050000>;
	239	+ };
	240	+ opp-924000000 {
	241	+ opp-hz = /bits/ 64 <924000000>;
	242	+ opp-microvolt = <1125000>;
	243	+ opp-microvolt-L0 = <1125000>;
	244	+ opp-microvolt-L1 = <1100000>;
	245	+ };
	246	+ /* 1056M is only for ddr4 */
	247	+ opp-1056000000 {
	248	+ opp-hz = /bits/ 64 <1056000000>;
	249	+ opp-microvolt = <1175000>;
	250	+ opp-microvolt-L0 = <1175000>;
	251	+ opp-microvolt-L1 = <1150000>;
	252	+ status = "disabled";
	253	+ };
	254	+ };
	255	+
	256	+ analog_sound: analog-sound {
	257	+ compatible = "simple-audio-card";
	258	+ simple-audio-card,format = "i2s";
	259	+ simple-audio-card,mclk-fs = <256>;
	260	+ simple-audio-card,name = "rockchip,rk3328";
	261	+
	262	+ simple-audio-card,cpu {
	263	+ sound-dai = <&i2s1>;
	264	+ };
	265	+
	266	+ simple-audio-card,codec {
	267	+ sound-dai = <&codec>;
167	268	};
168	269	};
169	270
..	..	@@ -182,10 +283,38 @@
182	283	nvmem-cell-names = "id", "cpu-version";
183	284	};
184	285
	286	+ display_subsystem: display-subsystem {
	287	+ compatible = "rockchip,display-subsystem";
	288	+ ports = <&vop_out>;
	289	+ status = "disabled";
	290	+ };
	291	+
185	292	firmware {
186		- optee: optee {
	293	+ optee {
187	294	compatible = "linaro,optee-tz";
188	295	method = "smc";
	296	+ };
	297	+ };
	298	+
	299	+ gmac_clkin: external-gmac-clock {
	300	+ compatible = "fixed-clock";
	301	+ clock-frequency = <125000000>;
	302	+ clock-output-names = "gmac_clkin";
	303	+ #clock-cells = <0>;
	304	+ };
	305	+
	306	+ hdmi_sound: hdmi-sound {
	307	+ compatible = "simple-audio-card";
	308	+ simple-audio-card,format = "i2s";
	309	+ simple-audio-card,mclk-fs = <128>;
	310	+ simple-audio-card,name = "rockchip,hdmi";
	311	+
	312	+ simple-audio-card,cpu {
	313	+ sound-dai = <&i2s0>;
	314	+ };
	315	+
	316	+ simple-audio-card,codec {
	317	+ sound-dai = <&hdmi>;
189	318	};
190	319	};
191	320
..	..	@@ -196,18 +325,34 @@
196	325
197	326	rockchip_suspend: rockchip-suspend {
198	327	compatible = "rockchip,pm-rk3328";
199		- status = "disabled";
200	328	rockchip,sleep-mode-config = <0>;
201	329	rockchip,virtual-poweroff = <0>;
	330	+ status = "disabled";
202	331	};
203	332
204	333	rockchip_system_monitor: rockchip-system-monitor {
205	334	compatible = "rockchip,system-monitor";
206		-
207	335	rockchip,thermal-zone = "soc-thermal";
208	336	rockchip,polling-delay = <200>; /* milliseconds */
209		-
210	337	rockchip,video-4k-offline-cpus = "3";
	338	+ };
	339	+
	340	+ spdif_out: spdif-out {
	341	+ compatible = "linux,spdif-dit";
	342	+ #sound-dai-cells = <0>;
	343	+ };
	344	+
	345	+ spdif_sound: spdif-sound {
	346	+ compatible = "simple-audio-card";
	347	+ simple-audio-card,name = "rockchip,spdif";
	348	+
	349	+ simple-audio-card,cpu {
	350	+ sound-dai = <&spdif>;
	351	+ };
	352	+
	353	+ simple-audio-card,codec {
	354	+ sound-dai = <&spdif_out>;
	355	+ };
211	356	};
212	357
213	358	timer {
..	..	@@ -225,6 +370,13 @@
225	370	clock-output-names = "xin24m";
226	371	};
227	372
	373	+ xin32k: xin32k {
	374	+ compatible = "fixed-clock";
	375	+ clock-frequency = <32768>;
	376	+ clock-output-names = "xin32k";
	377	+ #clock-cells = <0>;
	378	+ };
	379	+
228	380	i2s0: i2s@ff000000 {
229	381	compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
230	382	reg = <0x0 0xff000000 0x0 0x1000>;
..	..	@@ -235,6 +387,7 @@
235	387	dma-names = "tx", "rx";
236	388	resets = <&cru SRST_I2S0>, <&cru SRST_I2S0_H>;
237	389	reset-names = "reset-m", "reset-h";
	390	+ #sound-dai-cells = <0>;
238	391	status = "disabled";
239	392	};
240	393
..	..	@@ -248,6 +401,7 @@
248	401	dma-names = "tx", "rx";
249	402	resets = <&cru SRST_I2S1>, <&cru SRST_I2S1_H>;
250	403	reset-names = "reset-m", "reset-h";
	404	+ #sound-dai-cells = <0>;
251	405	status = "disabled";
252	406	};
253	407
..	..	@@ -269,6 +423,7 @@
269	423	&i2s2m0_sdo
270	424	&i2s2m0_sdi>;
271	425	pinctrl-1 = <&i2s2m0_sleep>;
	426	+ #sound-dai-cells = <0>;
272	427	status = "disabled";
273	428	};
274	429
..	..	@@ -281,12 +436,13 @@
281	436	dmas = <&dmac 10>;
282	437	dma-names = "tx";
283	438	pinctrl-names = "default";
284		- pinctrl-0 = <&spdifm2_tx>;
	439	+ pinctrl-0 = <&spdifm0_tx>;
	440	+ #sound-dai-cells = <0>;
285	441	status = "disabled";
286	442	};
287	443
288	444	pdm: pdm@ff040000 {
289		- compatible = "rockchip,rk3328-pdm";
	445	+ compatible = "rockchip,pdm";
290	446	reg = <0x0 0xff040000 0x0 0x1000>;
291	447	clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
292	448	clock-names = "pdm_clk", "pdm_hclk";
..	..	@@ -294,11 +450,13 @@
294	450	dma-names = "rx";
295	451	pinctrl-names = "default", "sleep";
296	452	pinctrl-0 = <&pdmm0_clk
	453	+ &pdmm0_fsync
297	454	&pdmm0_sdi0
298	455	&pdmm0_sdi1
299	456	&pdmm0_sdi2
300	457	&pdmm0_sdi3>;
301	458	pinctrl-1 = <&pdmm0_clk_sleep
	459	+ &pdmm0_fsync_sleep
302	460	&pdmm0_sdi0_sleep
303	461	&pdmm0_sdi1_sleep
304	462	&pdmm0_sdi2_sleep
..	..	@@ -344,12 +502,16 @@
344	502	grf: syscon@ff100000 {
345	503	compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
346	504	reg = <0x0 0xff100000 0x0 0x1000>;
347		- #address-cells = <1>;
348		- #size-cells = <1>;
349	505
350	506	io_domains: io-domains {
351	507	compatible = "rockchip,rk3328-io-voltage-domain";
352	508	status = "disabled";
	509	+ };
	510	+
	511	+ grf_gpio: grf-gpio {
	512	+ compatible = "rockchip,rk3328-grf-gpio";
	513	+ gpio-controller;
	514	+ #gpio-cells = <2>;
353	515	};
354	516
355	517	power: power-controller {
..	..	@@ -359,10 +521,10 @@
359	521	#size-cells = <0>;
360	522	status = "okay";
361	523
362		- pd_hevc@RK3328_PD_HEVC {
	524	+ power-domain@RK3328_PD_HEVC {
363	525	reg = <RK3328_PD_HEVC>;
364	526	};
365		- pd_video@RK3328_PD_VIDEO {
	527	+ power-domain@RK3328_PD_VIDEO {
366	528	reg = <RK3328_PD_VIDEO>;
367	529	clocks = <&cru ACLK_RKVDEC>,
368	530	<&cru HCLK_RKVDEC>,
..	..	@@ -370,7 +532,7 @@
370	532	<&cru SCLK_VDEC_CORE>;
371	533	pm_qos = <&qos_rkvdec_r>, <&qos_rkvdec_w>;
372	534	};
373		- pd_vpu@RK3328_PD_VPU {
	535	+ power-domain@RK3328_PD_VPU {
374	536	reg = <RK3328_PD_VPU>;
375	537	clocks = <&cru ACLK_VPU>,
376	538	<&cru HCLK_VPU>;
..	..	@@ -381,12 +543,65 @@
381	543	reboot_mode: reboot-mode {
382	544	compatible = "syscon-reboot-mode";
383	545	offset = <0x5c8>;
	546	+ mode-bootloader = <BOOT_BL_DOWNLOAD>;
	547	+ mode-charge = <BOOT_CHARGING>;
	548	+ mode-fastboot = <BOOT_FASTBOOT>;
	549	+ mode-loader = <BOOT_BL_DOWNLOAD>;
384	550	mode-normal = <BOOT_NORMAL>;
385	551	mode-recovery = <BOOT_RECOVERY>;
386		- mode-bootloader = <BOOT_FASTBOOT>;
387		- mode-loader = <BOOT_BL_DOWNLOAD>;
	552	+ mode-ums = <BOOT_UMS>;
388	553	};
	554	+ };
389	555
	556	+ thermal-zones {
	557	+ soc_thermal: soc-thermal {
	558	+ polling-delay-passive = <20>; /* milliseconds */
	559	+ polling-delay = <1000>; /* milliseconds */
	560	+ sustainable-power = <1000>; /* milliwatts */
	561	+
	562	+ thermal-sensors = <&tsadc 0>;
	563	+
	564	+ trips {
	565	+ threshold: trip-point-0 {
	566	+ temperature = <70000>; /* millicelsius */
	567	+ hysteresis = <2000>; /* millicelsius */
	568	+ type = "passive";
	569	+ };
	570	+ target: trip-point-1 {
	571	+ temperature = <85000>; /* millicelsius */
	572	+ hysteresis = <2000>; /* millicelsius */
	573	+ type = "passive";
	574	+ };
	575	+ soc_crit: soc-crit {
	576	+ temperature = <115000>; /* millicelsius */
	577	+ hysteresis = <2000>; /* millicelsius */
	578	+ type = "critical";
	579	+ };
	580	+ };
	581	+
	582	+ cooling-maps {
	583	+ map0 {
	584	+ trip = <&target>;
	585	+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	586	+ contribution = <4096>;
	587	+ };
	588	+ map1 {
	589	+ trip = <&target>;
	590	+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	591	+ contribution = <4096>;
	592	+ };
	593	+ map2 {
	594	+ trip = <&target>;
	595	+ cooling-device = <&rkvdec THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	596	+ contribution = <1024>;
	597	+ };
	598	+ map3 {
	599	+ trip = <&target>;
	600	+ cooling-device = <&dmc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	601	+ contribution = <1024>;
	602	+ };
	603	+ };
	604	+ };
390	605	};
391	606
392	607	uart0: serial@ff110000 {
..	..	@@ -432,6 +647,11 @@
432	647	reg-io-width = <4>;
433	648	reg-shift = <2>;
434	649	status = "disabled";
	650	+ };
	651	+
	652	+ pmu: power-management@ff140000 {
	653	+ compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
	654	+ reg = <0x0 0xff140000 0x0 0x1000>;
435	655	};
436	656
437	657	i2c0: i2c@ff150000 {
..	..	@@ -506,11 +726,13 @@
506	726	reg = <0x0 0xff1a0000 0x0 0x100>;
507	727	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
508	728	clocks = <&cru PCLK_BUS_PRE>;
	729	+ status = "disabled";
509	730	};
510	731
511	732	pwm0: pwm@ff1b0000 {
512	733	compatible = "rockchip,rk3328-pwm";
513	734	reg = <0x0 0xff1b0000 0x0 0x10>;
	735	+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
514	736	clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
515	737	clock-names = "pwm", "pclk";
516	738	pinctrl-names = "active";
..	..	@@ -522,6 +744,7 @@
522	744	pwm1: pwm@ff1b0010 {
523	745	compatible = "rockchip,rk3328-pwm";
524	746	reg = <0x0 0xff1b0010 0x0 0x10>;
	747	+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
525	748	clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
526	749	clock-names = "pwm", "pclk";
527	750	pinctrl-names = "active";
..	..	@@ -533,6 +756,7 @@
533	756	pwm2: pwm@ff1b0020 {
534	757	compatible = "rockchip,rk3328-pwm";
535	758	reg = <0x0 0xff1b0020 0x0 0x10>;
	759	+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
536	760	clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
537	761	clock-names = "pwm", "pclk";
538	762	pinctrl-names = "active";
..	..	@@ -553,56 +777,15 @@
553	777	status = "disabled";
554	778	};
555	779
556		- thermal-zones {
557		- soc_thermal: soc-thermal {
558		- polling-delay-passive = <20>;
559		- polling-delay = <1000>;
560		- sustainable-power = <1000>;
561		-
562		- thermal-sensors = <&tsadc 0>;
563		-
564		- trips {
565		- threshold: trip-point0 {
566		- temperature = <70000>;
567		- hysteresis = <2000>;
568		- type = "passive";
569		- };
570		- target: trip-point1 {
571		- temperature = <85000>;
572		- hysteresis = <2000>;
573		- type = "passive";
574		- };
575		- soc_crit: soc-crit {
576		- temperature = <115000>;
577		- hysteresis = <2000>;
578		- type = "critical";
579		- };
580		- };
581		-
582		- cooling-maps {
583		- map0 {
584		- trip = <&target>;
585		- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
586		- contribution = <4096>;
587		- };
588		- map1 {
589		- trip = <&target>;
590		- cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
591		- contribution = <4096>;
592		- };
593		- map2 {
594		- trip = <&target>;
595		- cooling-device = <&rkvdec THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
596		- contribution = <1024>;
597		- };
598		- map3 {
599		- trip = <&target>;
600		- cooling-device = <&dmc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
601		- contribution = <1024>;
602		- };
603		- };
604		- };
605		-
	780	+ dmac: dma-controller@ff1f0000 {
	781	+ compatible = "arm,pl330", "arm,primecell";
	782	+ reg = <0x0 0xff1f0000 0x0 0x4000>;
	783	+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	784	+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	785	+ arm,pl330-periph-burst;
	786	+ clocks = <&cru ACLK_DMAC>;
	787	+ clock-names = "apb_pclk";
	788	+ #dma-cells = <1>;
606	789	};
607	790
608	791	tsadc: tsadc@ff250000 {
..	..	@@ -614,12 +797,12 @@
614	797	clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
615	798	clock-names = "tsadc", "apb_pclk";
616	799	pinctrl-names = "gpio", "otpout";
617		- pinctrl-0 = <&otp_gpio>;
	800	+ pinctrl-0 = <&otp_pin>;
618	801	pinctrl-1 = <&otp_out>;
619	802	resets = <&cru SRST_TSADC>;
620	803	reset-names = "tsadc-apb";
621	804	rockchip,grf = <&grf>;
622		- rockchip,hw-tshut-temp = <120000>;
	805	+ rockchip,hw-tshut-temp = <100000>;
623	806	#thermal-sensor-cells = <1>;
624	807	status = "disabled";
625	808	};
..	..	@@ -664,7 +847,6 @@
664	847	gpu: gpu@ff300000 {
665	848	compatible = "arm,mali-450";
666	849	reg = <0x0 0xff300000 0x0 0x30000>;
667		-
668	850	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
669	851	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
670	852	<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
..	..	@@ -683,6 +865,7 @@
683	865	clock-names = "clk_mali";
684	866	#cooling-cells = <2>; /* min followed by max */
685	867	operating-points-v2 = <&gpu_opp_table>;
	868	+ resets = <&cru SRST_GPU_A>;
686	869	status = "disabled";
687	870
688	871	gpu_power_model: power_model {
..	..	@@ -738,37 +921,8 @@
738	921	rockchip,resetgroup-count = <4>;
739	922	rockchip,grf = <&grf>;
740	923	rockchip,grf-offset = <0x040c>;
741		- rockchip,grf-values = <0x8000000>, <0x8000800>;
742		- rockchip,grf-names = "grf_vepu2", "grf_vepu22";
743		- status = "disabled";
744		- };
745		-
746		- vepu22: vepu22@ff330000 {
747		- compatible = "rockchip,hevc-encoder-v22";
748		- reg = <0x0 0xff330000 0 0x200>;
749		- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
750		- clocks = <&cru ACLK_H265>, <&cru PCLK_H265>,
751		- <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
752		- <&cru ACLK_RKVENC>, <&cru ACLK_AXISRAM>;
753		- clock-names = "aclk_h265", "pclk_h265", "clk_core",
754		- "clk_dsp", "aclk_venc", "aclk_axi2sram";
755		- iommus = <&vepu22_mmu>;
756		- rockchip,srv = <&mpp_srv>;
757		- rockchip,taskqueue-node = <2>;
758		- rockchip,resetgroup-node = <2>;
759		- power-domains = <&power RK3328_PD_HEVC>;
760		- status = "disabled";
761		- };
762		-
763		- vepu22_mmu: iommu@ff330200 {
764		- compatible = "rockchip,iommu";
765		- reg = <0x0 0xff330200 0 0x100>;
766		- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
767		- interrupt-names = "vepu22_mmu";
768		- clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
769		- clock-names = "aclk", "iface";
770		- power-domains = <&power RK3328_PD_HEVC>;
771		- #iommu-cells = <0>;
	924	+ rockchip,grf-values = <0x8000000>;
	925	+ rockchip,grf-names = "grf_vepu2";
772	926	status = "disabled";
773	927	};
774	928
..	..	@@ -779,7 +933,7 @@
779	933	clocks = <&cru ACLK_H264>, <&cru HCLK_H264>;
780	934	clock-names = "aclk_vcodec", "hclk_vcodec";
781	935	resets = <&cru SRST_RKVENC_H264_A>,
782		- <&cru SRST_RKVENC_H264_H>;
	936	+ <&cru SRST_RKVENC_H264_H>;
783	937	reset-names = "video_a", "video_h";
784	938	iommus = <&vepu_mmu>;
785	939	rockchip,srv = <&mpp_srv>;
..	..	@@ -823,10 +977,10 @@
823	977	reg = <0x0 0xff350800 0x0 0x40>;
824	978	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
825	979	interrupt-names = "vpu_mmu";
826		- clock-names = "aclk", "iface";
827	980	clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
828		- power-domains = <&power RK3328_PD_VPU>;
	981	+ clock-names = "aclk", "iface";
829	982	#iommu-cells = <0>;
	983	+ power-domains = <&power RK3328_PD_VPU>;
830	984	status = "disabled";
831	985	};
832	986
..	..	@@ -848,7 +1002,7 @@
848	1002	};
849	1003
850	1004	rkvdec: rkvdec@ff36000 {
851		- compatible = "rockchip,rkv-decoder-rk3328";
	1005	+ compatible = "rockchip,rkv-decoder-rk3328", "rockchip,rkv-decoder-v2";
852	1006	reg = <0x0 0xff360000 0x0 0x400>;
853	1007	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
854	1008	interrupt-names = "irq_dec";
..	..	@@ -920,8 +1074,8 @@
920	1074	interrupt-names = "rkvdec_mmu";
921	1075	clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
922	1076	clock-names = "aclk", "iface";
923		- power-domains = <&power RK3328_PD_VIDEO>;
924	1077	#iommu-cells = <0>;
	1078	+ power-domains = <&power RK3328_PD_VIDEO>;
925	1079	status = "disabled";
926	1080	};
927	1081
..	..	@@ -953,6 +1107,32 @@
953	1107	};
954	1108	};
955	1109
	1110	+ tve: tve@ff373e00 {
	1111	+ compatible = "rockchip,rk3328-tve";
	1112	+ reg = <0x0 0xff373e00 0x0 0x100>,
	1113	+ <0x0 0xff420000 0x0 0x10000>;
	1114	+ rockchip,saturation = <0x00376749>;
	1115	+ rockchip,brightcontrast = <0x0000a305>;
	1116	+ rockchip,adjtiming = <0xb6c00880>;
	1117	+ rockchip,lumafilter0 = <0x01ff0000>;
	1118	+ rockchip,lumafilter1 = <0xf40200fe>;
	1119	+ rockchip,lumafilter2 = <0xf332d70c>;
	1120	+ rockchip,daclevel = <0x22>;
	1121	+ rockchip,dac1level = <0x7>;
	1122	+ status = "disabled";
	1123	+
	1124	+ ports {
	1125	+ tve_in: port {
	1126	+ #address-cells = <1>;
	1127	+ #size-cells = <0>;
	1128	+ tve_in_vop: endpoint@0 {
	1129	+ reg = <0>;
	1130	+ remote-endpoint = <&vop_out_tve>;
	1131	+ };
	1132	+ };
	1133	+ };
	1134	+ };
	1135	+
956	1136	vop_mmu: iommu@ff373f00 {
957	1137	compatible = "rockchip,iommu";
958	1138	reg = <0x0 0xff373f00 0x0 0x100>;
..	..	@@ -961,6 +1141,17 @@
961	1141	clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
962	1142	clock-names = "aclk", "iface";
963	1143	#iommu-cells = <0>;
	1144	+ status = "disabled";
	1145	+ };
	1146	+
	1147	+ cif: cif@ff380000 {
	1148	+ compatible = "rockchip,cif", "rockchip,rk3328-cif";
	1149	+ reg = <0x0 0xff380000 0x0 0x400>;
	1150	+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	1151	+ clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>;
	1152	+ clock-names = "aclk_cif", "hclk_cif";
	1153	+ resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_P>;
	1154	+ reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_p";
964	1155	status = "disabled";
965	1156	};
966	1157
..	..	@@ -994,7 +1185,7 @@
994	1185	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
995	1186	interrupt-names = "iep_mmu";
996	1187	clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
997		- clock-names = "aclk", "iface";
	1188	+ clock-names = "aclk", "hclk";
998	1189	power-domains = <&power RK3328_PD_VIDEO>;
999	1190	#iommu-cells = <0>;
1000	1191	status = "disabled";
..	..	@@ -1008,23 +1199,21 @@
1008	1199	<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1009	1200	clocks = <&cru PCLK_HDMI>,
1010	1201	<&cru SCLK_HDMI_SFC>,
1011		- <&cru SCLK_RTC32K>,
1012		- <&cru HCLK_VIO>;
	1202	+ <&cru SCLK_RTC32K>;
1013	1203	clock-names = "iahb",
1014	1204	"isfr",
1015		- "cec",
1016		- "hclk_vio";
	1205	+ "cec";
1017	1206	phys = <&hdmiphy>;
1018	1207	phy-names = "hdmi";
1019		- pinctrl-names = "default", "gpio";
	1208	+ pinctrl-names = "default", "pin";
1020	1209	pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
1021		- pinctrl-1 = <&i2c3_gpio>;
	1210	+ pinctrl-1 = <&i2c3_pins>;
1022	1211	resets = <&cru SRST_HDMI_P>,
1023	1212	<&cru SRST_HDMIPHY>;
1024	1213	reset-names = "hdmi",
1025	1214	"hdmiphy";
1026	1215	rockchip,grf = <&grf>;
1027		- max-tmdsclk = <371250>;
	1216	+ #sound-dai-cells = <0>;
1028	1217	status = "disabled";
1029	1218
1030	1219	ports {
..	..	@@ -1039,56 +1228,27 @@
1039	1228	};
1040	1229	};
1041	1230
1042		- tve: tve@ff373e00 {
1043		- compatible = "rockchip,rk3328-tve";
1044		- reg = <0x0 0xff373e00 0x0 0x100>,
1045		- <0x0 0xff420000 0x0 0x10000>;
1046		- rockchip,saturation = <0x00376749>;
1047		- rockchip,brightcontrast = <0x0000a305>;
1048		- rockchip,adjtiming = <0xb6c00880>;
1049		- rockchip,lumafilter0 = <0x01ff0000>;
1050		- rockchip,lumafilter1 = <0xf40200fe>;
1051		- rockchip,lumafilter2 = <0xf332d70c>;
1052		- rockchip,daclevel = <0x22>;
1053		- rockchip,dac1level = <0x7>;
1054		- status = "disabled";
1055		-
1056		- ports {
1057		- tve_in: port {
1058		- #address-cells = <1>;
1059		- #size-cells = <0>;
1060		- tve_in_vop: endpoint@0 {
1061		- reg = <0>;
1062		- remote-endpoint = <&vop_out_tve>;
1063		- };
1064		- };
1065		- };
1066		- };
1067		-
1068		- display_subsystem: display-subsystem {
1069		- compatible = "rockchip,display-subsystem";
1070		- ports = <&vop_out>;
1071		- status = "disabled";
1072		- };
1073		-
1074	1231	codec: codec@ff410000 {
1075	1232	compatible = "rockchip,rk3328-codec";
1076	1233	reg = <0x0 0xff410000 0x0 0x1000>;
1077		- rockchip,grf = <&grf>;
1078		- clocks = <&cru PCLK_ACODEC>, <&cru SCLK_I2S1>;
	1234	+ clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
1079	1235	clock-names = "pclk", "mclk";
	1236	+ rockchip,grf = <&grf>;
	1237	+ #sound-dai-cells = <0>;
1080	1238	status = "disabled";
1081	1239	};
1082	1240
1083		- hdmiphy: hdmiphy@ff430000 {
	1241	+ hdmiphy: phy@ff430000 {
1084	1242	compatible = "rockchip,rk3328-hdmi-phy";
1085	1243	reg = <0x0 0xff430000 0x0 0x10000>;
1086	1244	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1087		- #phy-cells = <0>;
1088		- clocks = <&cru PCLK_HDMIPHY>, <&xin24m>;
1089		- clock-names = "sysclk", "refclk";
1090		- #clock-cells = <0>;
	1245	+ clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
	1246	+ clock-names = "sysclk", "refclk", "refpclk";
1091	1247	clock-output-names = "hdmi_phy";
	1248	+ #clock-cells = <0>;
	1249	+ nvmem-cells = <&efuse_cpu_version>;
	1250	+ nvmem-cell-names = "cpu-version";
	1251	+ #phy-cells = <0>;
1092	1252	status = "disabled";
1093	1253	};
1094	1254
..	..	@@ -1109,7 +1269,8 @@
1109	1269	<&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
1110	1270	<&cru SCLK_UART1>, <&cru SCLK_UART2>,
1111	1271	<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
1112		- <&cru ACLK_RGA_PRE>, <&cru ACLK_RKVDEC_PRE>,
	1272	+ <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
	1273	+ <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
1113	1274	<&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
1114	1275	<&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
1115	1276	<&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
..	..	@@ -1119,8 +1280,7 @@
1119	1280	<&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
1120	1281	<&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
1121	1282	<&cru HCLK_PERI>, <&cru PCLK_PERI>,
1122		- <&cru SCLK_RTC32K>, <&cru ACLK_VOP>,
1123		- <&cru ACLK_GMAC>;
	1283	+ <&cru SCLK_RTC32K>;
1124	1284	assigned-clock-parents =
1125	1285	<&cru HDMIPHY>, <&cru PLL_APLL>,
1126	1286	<&cru PLL_GPLL>, <&xin24m>,
..	..	@@ -1131,6 +1291,7 @@
1131	1291	<24000000>, <24000000>,
1132	1292	<15000000>, <15000000>,
1133	1293	<100000000>, <100000000>,
	1294	+ <100000000>, <100000000>,
1134	1295	<50000000>, <100000000>,
1135	1296	<100000000>, <100000000>,
1136	1297	<50000000>, <50000000>,
..	..	@@ -1140,8 +1301,7 @@
1140	1301	<150000000>, <75000000>,
1141	1302	<75000000>, <150000000>,
1142	1303	<75000000>, <75000000>,
1143		- <32768>, <400000000>,
1144		- <180000000>;
	1304	+ <32768>;
1145	1305	};
1146	1306
1147	1307	usb2phy_grf: syscon@ff450000 {
..	..	@@ -1222,7 +1382,7 @@
1222	1382	};
1223	1383	};
1224	1384
1225		- sdmmc: dwmmc@ff500000 {
	1385	+ sdmmc: mmc@ff500000 {
1226	1386	compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
1227	1387	reg = <0x0 0xff500000 0x0 0x4000>;
1228	1388	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -1234,7 +1394,7 @@
1234	1394	status = "disabled";
1235	1395	};
1236	1396
1237		- sdio: dwmmc@ff510000 {
	1397	+ sdio: mmc@ff510000 {
1238	1398	compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
1239	1399	reg = <0x0 0xff510000 0x0 0x4000>;
1240	1400	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -1246,7 +1406,7 @@
1246	1406	status = "disabled";
1247	1407	};
1248	1408
1249		- emmc: dwmmc@ff520000 {
	1409	+ emmc: mmc@ff520000 {
1250	1410	compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
1251	1411	reg = <0x0 0xff520000 0x0 0x4000>;
1252	1412	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -1274,6 +1434,7 @@
1274	1434	resets = <&cru SRST_GMAC2IO_A>;
1275	1435	reset-names = "stmmaceth";
1276	1436	rockchip,grf = <&grf>;
	1437	+ snps,txpbl = <0x4>;
1277	1438	status = "disabled";
1278	1439	};
1279	1440
..	..	@@ -1302,7 +1463,7 @@
1302	1463	#address-cells = <1>;
1303	1464	#size-cells = <0>;
1304	1465
1305		- phy: phy@0 {
	1466	+ phy: ethernet-phy@0 {
1306	1467	compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
1307	1468	reg = <0>;
1308	1469	clocks = <&cru SCLK_MAC2PHY_OUT>;
..	..	@@ -1319,13 +1480,12 @@
1319	1480	"snps,dwc2";
1320	1481	reg = <0x0 0xff580000 0x0 0x40000>;
1321	1482	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1322		- clocks = <&cru HCLK_OTG>;
1323		- clock-names = "otg";
	1483	+ clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>;
	1484	+ clock-names = "otg", "otg_pmu";
1324	1485	dr_mode = "otg";
1325	1486	g-np-tx-fifo-size = <16>;
1326	1487	g-rx-fifo-size = <280>;
1327	1488	g-tx-fifo-size = <256 128 128 64 32 16>;
1328		- g-use-dma;
1329	1489	phys = <&u2phy_otg>;
1330	1490	phy-names = "usb2-phy";
1331	1491	status = "disabled";
..	..	@@ -1335,8 +1495,9 @@
1335	1495	compatible = "generic-ehci";
1336	1496	reg = <0x0 0xff5c0000 0x0 0x10000>;
1337	1497	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1338		- clocks = <&cru HCLK_HOST0>, <&u2phy>;
1339		- clock-names = "usbhost", "utmi";
	1498	+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
	1499	+ <&u2phy>;
	1500	+ clock-names = "usbhost", "arbiter", "utmi";
1340	1501	phys = <&u2phy_host>;
1341	1502	phy-names = "usb";
1342	1503	status = "disabled";
..	..	@@ -1346,27 +1507,28 @@
1346	1507	compatible = "generic-ohci";
1347	1508	reg = <0x0 0xff5d0000 0x0 0x10000>;
1348	1509	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1349		- clocks = <&cru HCLK_HOST0>, <&u2phy>;
1350		- clock-names = "usbhost", "utmi";
	1510	+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
	1511	+ <&u2phy>;
	1512	+ clock-names = "usbhost", "arbiter", "utmi";
1351	1513	phys = <&u2phy_host>;
1352	1514	phy-names = "usb";
1353	1515	status = "disabled";
1354	1516	};
1355	1517
1356		- sdmmc_ext: dwmmc@ff5f0000 {
	1518	+ sdmmc_ext: mmc@ff5f0000 {
1357	1519	compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
1358	1520	reg = <0x0 0xff5f0000 0x0 0x4000>;
1359	1521	clock-freq-min-max = <400000 150000000>;
1360	1522	clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
1361	1523	<&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
1362		- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
	1524	+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1363	1525	fifo-depth = <0x100>;
1364	1526	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1365	1527	status = "disabled";
1366	1528	};
1367	1529
1368		- usbdrd3: usb@ff600000 {
1369		- compatible = "rockchip,rk3328-dwc3";
	1530	+ usbdrd3: usbdrd {
	1531	+ compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
1370	1532	clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
1371	1533	<&cru ACLK_USB3OTG>;
1372	1534	clock-names = "ref_clk", "suspend_clk",
..	..	@@ -1384,13 +1546,14 @@
1384	1546	phys = <&u3phy_utmi>, <&u3phy_pipe>;
1385	1547	phy-names = "usb2-phy", "usb3-phy";
1386	1548	phy_type = "utmi_wide";
	1549	+ snps,dis-del-phy-power-chg-quirk;
1387	1550	snps,dis_enblslpm_quirk;
	1551	+ snps,dis-tx-ipgap-linecheck-quirk;
1388	1552	snps,dis-u2-freeclk-exists-quirk;
1389	1553	snps,dis_u2_susphy_quirk;
1390		- snps,dis-u3-autosuspend-quirk;
1391	1554	snps,dis_u3_susphy_quirk;
1392		- snps,dis-del-phy-power-chg-quirk;
1393		- snps,tx-ipgap-linecheck-dis-quirk;
	1555	+ snps,parkmode-disable-hs-quirk;
	1556	+ snps,parkmode-disable-ss-quirk;
1394	1557	status = "disabled";
1395	1558	};
1396	1559	};
..	..	@@ -1411,102 +1574,10 @@
1411	1574	};
1412	1575
1413	1576	dfi: dfi@ff790000 {
1414		- reg = <0x00 0xff790000 0x00 0x400>;
1415	1577	compatible = "rockchip,rk3328-dfi";
	1578	+ reg = <0x00 0xff790000 0x00 0x400>;
1416	1579	rockchip,grf = <&grf>;
1417	1580	status = "disabled";
1418		- };
1419		-
1420		- dmc: dmc {
1421		- compatible = "rockchip,rk3328-dmc";
1422		- devfreq-events = <&dfi>;
1423		- clocks = <&cru SCLK_DDRCLK>;
1424		- clock-names = "dmc_clk";
1425		- operating-points-v2 = <&dmc_opp_table>;
1426		- ddr_timing = <&ddr_timing>;
1427		- upthreshold = <40>;
1428		- downdifferential = <20>;
1429		- system-status-freq = <
1430		- /system status freq(KHz)/
1431		- SYS_STATUS_NORMAL 786000
1432		- SYS_STATUS_REBOOT 786000
1433		- SYS_STATUS_SUSPEND 786000
1434		- SYS_STATUS_VIDEO_1080P 786000
1435		- SYS_STATUS_VIDEO_4K 786000
1436		- SYS_STATUS_VIDEO_4K_10B 933000
1437		- SYS_STATUS_PERFORMANCE 933000
1438		- SYS_STATUS_BOOST 933000
1439		- >;
1440		- auto-min-freq = <786000>;
1441		- auto-freq-en = <0>;
1442		- #cooling-cells = <2>;
1443		- status = "disabled";
1444		-
1445		- ddr_power_model: ddr_power_model {
1446		- compatible = "ddr_power_model";
1447		- dynamic-power-coefficient = <120>;
1448		- static-power-coefficient = <200>;
1449		- ts = <32000 4700 (-80) 2>;
1450		- thermal-zone = "soc-thermal";
1451		- };
1452		- };
1453		-
1454		- dmc_opp_table: dmc-opp-table {
1455		- compatible = "operating-points-v2";
1456		-
1457		- rockchip,leakage-voltage-sel = <
1458		- 1 10 0
1459		- 11 254 1
1460		- >;
1461		- nvmem-cells = <&logic_leakage>;
1462		- nvmem-cell-names = "ddr_leakage";
1463		-
1464		- opp-400000000 {
1465		- opp-hz = /bits/ 64 <400000000>;
1466		- opp-microvolt = <950000>;
1467		- opp-microvolt-L0 = <950000>;
1468		- opp-microvolt-L1 = <950000>;
1469		- status = "disabled";
1470		- };
1471		- opp-600000000 {
1472		- opp-hz = /bits/ 64 <600000000>;
1473		- opp-microvolt = <1025000>;
1474		- opp-microvolt-L0 = <1025000>;
1475		- opp-microvolt-L1 = <1000000>;
1476		- status = "disabled";
1477		- };
1478		- opp-786000000 {
1479		- opp-hz = /bits/ 64 <786000000>;
1480		- opp-microvolt = <1075000>;
1481		- opp-microvolt-L0 = <1075000>;
1482		- opp-microvolt-L1 = <1050000>;
1483		- };
1484		- opp-800000000 {
1485		- opp-hz = /bits/ 64 <800000000>;
1486		- opp-microvolt = <1075000>;
1487		- opp-microvolt-L0 = <1075000>;
1488		- opp-microvolt-L1 = <1050000>;
1489		- };
1490		- opp-850000000 {
1491		- opp-hz = /bits/ 64 <850000000>;
1492		- opp-microvolt = <1075000>;
1493		- opp-microvolt-L0 = <1075000>;
1494		- opp-microvolt-L1 = <1050000>;
1495		- };
1496		- opp-933000000 {
1497		- opp-hz = /bits/ 64 <933000000>;
1498		- opp-microvolt = <1125000>;
1499		- opp-microvolt-L0 = <1125000>;
1500		- opp-microvolt-L1 = <1100000>;
1501		- };
1502		- /* 1066M is only for ddr4 */
1503		- opp-1066000000 {
1504		- opp-hz = /bits/ 64 <1066000000>;
1505		- opp-microvolt = <1175000>;
1506		- opp-microvolt-L0 = <1175000>;
1507		- opp-microvolt-L1 = <1150000>;
1508		- status = "disabled";
1509		- };
1510	1581	};
1511	1582
1512	1583	gic: interrupt-controller@ff811000 {
..	..	@@ -1529,7 +1600,7 @@
1529	1600	#size-cells = <2>;
1530	1601	ranges;
1531	1602
1532		- gpio0: gpio0@ff210000 {
	1603	+ gpio0: gpio@ff210000 {
1533	1604	compatible = "rockchip,gpio-bank";
1534	1605	reg = <0x0 0xff210000 0x0 0x100>;
1535	1606	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -1542,7 +1613,7 @@
1542	1613	#interrupt-cells = <2>;
1543	1614	};
1544	1615
1545		- gpio1: gpio1@ff220000 {
	1616	+ gpio1: gpio@ff220000 {
1546	1617	compatible = "rockchip,gpio-bank";
1547	1618	reg = <0x0 0xff220000 0x0 0x100>;
1548	1619	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -1555,7 +1626,7 @@
1555	1626	#interrupt-cells = <2>;
1556	1627	};
1557	1628
1558		- gpio2: gpio2@ff230000 {
	1629	+ gpio2: gpio@ff230000 {
1559	1630	compatible = "rockchip,gpio-bank";
1560	1631	reg = <0x0 0xff230000 0x0 0x100>;
1561	1632	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -1568,7 +1639,7 @@
1568	1639	#interrupt-cells = <2>;
1569	1640	};
1570	1641
1571		- gpio3: gpio3@ff240000 {
	1642	+ gpio3: gpio@ff240000 {
1572	1643	compatible = "rockchip,gpio-bank";
1573	1644	reg = <0x0 0xff240000 0x0 0x100>;
1574	1645	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -1681,7 +1752,7 @@
1681	1752	rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1682	1753	<0 RK_PA6 2 &pcfg_pull_none>;
1683	1754	};
1684		- i2c3_gpio: i2c3-gpio {
	1755	+ i2c3_pins: i2c3-pins {
1685	1756	rockchip,pins =
1686	1757	<0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1687	1758	<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
..	..	@@ -1791,7 +1862,7 @@
1791	1862	};
1792	1863
1793	1864	tsadc {
1794		- otp_gpio: otp-gpio {
	1865	+ otp_pin: otp-pin {
1795	1866	rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1796	1867	};
1797	1868
..	..	@@ -1814,7 +1885,7 @@
1814	1885	rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1815	1886	};
1816	1887
1817		- uart0_rts_gpio: uart0-rts-gpio {
	1888	+ uart0_rts_pin: uart0-rts-pin {
1818	1889	rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1819	1890	};
1820	1891	};
..	..	@@ -1833,7 +1904,7 @@
1833	1904	rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1834	1905	};
1835	1906
1836		- uart1_rts_gpio: uart1-rts-gpio {
	1907	+ uart1_rts_pin: uart1-rts-pin {
1837	1908	rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1838	1909	};
1839	1910	};
..	..	@@ -2059,7 +2130,7 @@
2059	2130	rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
2060	2131	};
2061	2132
2062		- sdmmc0m0_gpio: sdmmc0m0-gpio {
	2133	+ sdmmc0m0_pin: sdmmc0m0-pin {
2063	2134	rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
2064	2135	};
2065	2136	};
..	..	@@ -2069,7 +2140,7 @@
2069	2140	rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
2070	2141	};
2071	2142
2072		- sdmmc0m1_gpio: sdmmc0m1-gpio {
	2143	+ sdmmc0m1_pin: sdmmc0m1-pin {
2073	2144	rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
2074	2145	};
2075	2146	};
..	..	@@ -2102,7 +2173,7 @@
2102	2173	<1 RK_PA3 1 &pcfg_pull_up_8ma>;
2103	2174	};
2104	2175
2105		- sdmmc0_gpio: sdmmc0-gpio {
	2176	+ sdmmc0_pins: sdmmc0-pins {
2106	2177	rockchip,pins =
2107	2178	<1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2108	2179	<1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
..	..	@@ -2144,7 +2215,7 @@
2144	2215	<3 RK_PA7 3 &pcfg_pull_up_4ma>;
2145	2216	};
2146	2217
2147		- sdmmc0ext_gpio: sdmmc0ext-gpio {
	2218	+ sdmmc0ext_pins: sdmmc0ext-pins {
2148	2219	rockchip,pins =
2149	2220	<3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2150	2221	<3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
..	..	@@ -2189,7 +2260,7 @@
2189	2260	<1 RK_PC1 1 &pcfg_pull_up_8ma>;
2190	2261	};
2191	2262
2192		- sdmmc1_gpio: sdmmc1-gpio {
	2263	+ sdmmc1_pins: sdmmc1-pins {
2193	2264	rockchip,pins =
2194	2265	<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2195	2266	<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
..	..	@@ -2249,10 +2320,8 @@
2249	2320	pwm0_pin: pwm0-pin {
2250	2321	rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
2251	2322	};
2252		-
2253	2323	pwm0_pin_pull_up: pwm0-pin-pull-up {
2254		- rockchip,pins =
2255		- <2 RK_PA4 1 &pcfg_pull_up>;
	2324	+ rockchip,pins = <2 RK_PA4 1 &pcfg_pull_up>;
2256	2325	};
2257	2326	};
2258	2327
..	..	@@ -2260,10 +2329,8 @@
2260	2329	pwm1_pin: pwm1-pin {
2261	2330	rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
2262	2331	};
2263		-
2264	2332	pwm1_pin_pull_up: pwm1-pin-pull-up {
2265		- rockchip,pins =
2266		- <2 RK_PA5 1 &pcfg_pull_up>;
	2333	+ rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>;
2267	2334	};
2268	2335	};
2269	2336
..	..	@@ -2368,12 +2435,12 @@
2368	2435	};
2369	2436
2370	2437	gmac2phy {
2371		- fephyled_speed100: fephyled-speed100 {
2372		- rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
2373		- };
2374		-
2375	2438	fephyled_speed10: fephyled-speed10 {
2376	2439	rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
	2440	+ };
	2441	+
	2442	+ fephyled_speed100: fephyled-speed100 {
	2443	+ rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
2377	2444	};
2378	2445
2379	2446	fephyled_duplex: fephyled-duplex {
..	..	@@ -2409,7 +2476,7 @@
2409	2476	tsadc_int: tsadc-int {
2410	2477	rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
2411	2478	};
2412		- tsadc_gpio: tsadc-gpio {
	2479	+ tsadc_pin: tsadc-pin {
2413	2480	rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
2414	2481	};
2415	2482	};