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2024-05-10 cde9070d9970eef1f7ec2360586c802a16230ad8 
 kernel/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
....@@ -40,14 +40,78 @@
4040 
4141   Required properties:
4242   - compatible: "nvidia,tegra<chip>-vi"
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-  - reg: Physical base address and length of the controller's registers.
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+  - reg: Physical base address and length of the controller registers.
4444   - interrupts: The interrupt outputs from the controller.
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-  - clocks: Must contain one entry, for the module clock.
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+  - clocks: clocks: Must contain one entry, for the module clock.
4646     See ../clocks/clock-bindings.txt for details.
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-  - resets: Must contain an entry for each entry in reset-names.
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-    See ../reset/reset.txt for details.
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-  - reset-names: Must include the following entries:
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-    - vi
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+  - Tegra20/Tegra30/Tegra114/Tegra124:
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+    - resets: Must contain an entry for each entry in reset-names.
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+      See ../reset/reset.txt for details.
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+    - reset-names: Must include the following entries:
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+      - vi
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+  - Tegra210:
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+    - power-domains: Must include venc powergate node as vi is in VE partition.
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+
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+  ports (optional node)
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+  vi can have optional ports node and max 6 ports are supported. Each port
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+  should have single 'endpoint' child node. All port nodes are grouped under
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+  ports node. Please refer to the bindings defined in
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+  Documentation/devicetree/bindings/media/video-interfaces.txt
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+
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+  csi (required node)
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+  Tegra210 has CSI part of VI sharing same host interface and register space.
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+  So, VI device node should have CSI child node.
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+
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+    - csi: mipi csi interface to vi
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+
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+      Required properties:
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+      - compatible: "nvidia,tegra210-csi"
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+      - reg: Physical base address offset to parent and length of the controller
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+        registers.
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+      - clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks.
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+        See ../clocks/clock-bindings.txt for details.
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+      - power-domains: Must include sor powergate node as csicil is in
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+        SOR partition.
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+
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+      channel (optional nodes)
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+      Maximum 6 channels are supported with each csi brick as either x4 or x2
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+      based on hw connectivity to sensor.
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+
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+      Required properties:
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+      - reg: csi port number. Valid port numbers are 0 through 5.
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+      - nvidia,mipi-calibrate: Should contain a phandle and a specifier
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+        specifying which pads are used by this CSI port and need to be
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+	calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt.
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+
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+      Each channel node must contain 2 port nodes which can be grouped
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+      under 'ports' node and each port should have a single child 'endpoint'
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+      node.
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+
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+        ports node
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+        Please refer to the bindings defined in
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+        Documentation/devicetree/bindings/media/video-interfaces.txt
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+
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+        ports node must contain below 2 port nodes.
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+        port@0 with single child 'endpoint' node always a sink.
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+        port@1 with single child 'endpoint' node always a source.
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+
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+        port@0 (required node)
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+        Required properties:
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+        - reg: 0
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+
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+	  endpoint (required node)
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+	  Required properties:
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+	  - data-lanes: an array of data lane from 1 to 4. Valid array
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+	    lengths are 1/2/4.
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+	  - remote-endpoint: phandle to sensor 'endpoint' node.
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+
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+        port@1 (required node)
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+        Required properties:
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+        - reg: 1
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+
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+	  endpoint (required node)
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+	  Required properties:
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+	  - remote-endpoint: phandle to vi port 'endpoint' node.
51115 
52116 - epp: encoder pre-processor
53117 
....@@ -238,6 +302,9 @@
238302   - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
239303   - nvidia,edid: supplies a binary EDID blob
240304   - nvidia,panel: phandle of a display panel
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+  - nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane
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+    of the SOR, identified by the cell's index, is mapped via the crossbar to
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+    the pad specified by the cell's value.
241308 
242309   Optional properties when driving an eDP output:
243310   - nvidia,dpaux: phandle to a DispayPort AUX interface
....@@ -306,13 +373,84 @@
306373 			reset-names = "mpe";
307374 		};
308375 
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-		vi {
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-			compatible = "nvidia,tegra20-vi";
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-			reg = <0x54080000 0x00040000>;
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-			interrupts = <0 69 0x04>;
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-			clocks = <&tegra_car TEGRA20_CLK_VI>;
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-			resets = <&tegra_car 100>;
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-			reset-names = "vi";
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+		vi@54080000 {
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+			compatible = "nvidia,tegra210-vi";
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+			reg = <0x0 0x54080000 0x0 0x700>;
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+			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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+			assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
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+			assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
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+
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+			clocks = <&tegra_car TEGRA210_CLK_VI>;
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+			power-domains = <&pd_venc>;
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+
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+
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+			ranges = <0x0 0x0 0x54080000 0x2000>;
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+
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+			ports {
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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+
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+				port@0 {
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+					reg = <0>;
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+					imx219_vi_in0: endpoint {
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+						remote-endpoint = <&imx219_csi_out0>;
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+					};
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+				};
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+			};
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+
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+			csi@838 {
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+				compatible = "nvidia,tegra210-csi";
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+				reg = <0x838 0x1300>;
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+				assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
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+						  <&tegra_car TEGRA210_CLK_CILCD>,
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+						  <&tegra_car TEGRA210_CLK_CILE>,
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+						  <&tegra_car TEGRA210_CLK_CSI_TPG>;
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+				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
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+							 <&tegra_car TEGRA210_CLK_PLL_P>,
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+							 <&tegra_car TEGRA210_CLK_PLL_P>;
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+				assigned-clock-rates = <102000000>,
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+						       <102000000>,
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+						       <102000000>,
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+						       <972000000>;
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+
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+				clocks = <&tegra_car TEGRA210_CLK_CSI>,
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+					 <&tegra_car TEGRA210_CLK_CILAB>,
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+					 <&tegra_car TEGRA210_CLK_CILCD>,
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+					 <&tegra_car TEGRA210_CLK_CILE>,
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+					 <&tegra_car TEGRA210_CLK_CSI_TPG>;
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+				clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
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+				power-domains = <&pd_sor>;
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+
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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+
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+				channel@0 {
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+					reg = <0>;
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+					nvidia,mipi-calibrate = <&mipi 0x001>;
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+
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+					ports {
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+						#address-cells = <1>;
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+						#size-cells = <0>;
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+
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+						port@0 {
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+							reg = <0>;
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+							imx219_csi_in0: endpoint {
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+								data-lanes = <1 2>;
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+								remote-endpoint = <&imx219_out0>;
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+							};
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+						};
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+
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+						port@1 {
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+							reg = <1>;
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+							imx219_csi_out0: endpoint {
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+								remote-endpoint = <&imx219_vi_in0>;
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+							};
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+						};
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+					};
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+				};
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+			};
316454 		};
317455 
318456 		epp {