.. | .. |
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697 | 697 | int dcs_mask; |
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698 | 698 | int dcs_l, dcs_r; |
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699 | 699 | int dcs_l_reg, dcs_r_reg; |
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| 700 | + int an_out_reg; |
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700 | 701 | int timeout; |
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701 | 702 | int pwr_reg; |
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702 | 703 | |
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.. | .. |
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712 | 713 | dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1; |
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713 | 714 | dcs_r_reg = WM8904_DC_SERVO_8; |
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714 | 715 | dcs_l_reg = WM8904_DC_SERVO_9; |
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| 716 | + an_out_reg = WM8904_ANALOGUE_OUT1_LEFT; |
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715 | 717 | dcs_l = 0; |
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716 | 718 | dcs_r = 1; |
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717 | 719 | break; |
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.. | .. |
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720 | 722 | dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3; |
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721 | 723 | dcs_r_reg = WM8904_DC_SERVO_6; |
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722 | 724 | dcs_l_reg = WM8904_DC_SERVO_7; |
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| 725 | + an_out_reg = WM8904_ANALOGUE_OUT2_LEFT; |
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723 | 726 | dcs_l = 2; |
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724 | 727 | dcs_r = 3; |
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725 | 728 | break; |
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.. | .. |
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792 | 795 | snd_soc_component_update_bits(component, reg, |
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793 | 796 | WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, |
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794 | 797 | WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP); |
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| 798 | + |
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| 799 | + /* Update volume, requires PGA to be powered */ |
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| 800 | + val = snd_soc_component_read(component, an_out_reg); |
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| 801 | + snd_soc_component_write(component, an_out_reg, val); |
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795 | 802 | break; |
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796 | 803 | |
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797 | 804 | case SND_SOC_DAPM_POST_PMU: |
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.. | .. |
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2299 | 2306 | regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0, |
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2300 | 2307 | WM8904_POBCTRL, 0); |
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2301 | 2308 | |
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| 2309 | + /* Fill the cache for the ADC test register */ |
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| 2310 | + regmap_read(wm8904->regmap, WM8904_ADC_TEST_0, &val); |
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| 2311 | + |
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2302 | 2312 | /* Can leave the device powered off until we need it */ |
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2303 | 2313 | regcache_cache_only(wm8904->regmap, true); |
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2304 | 2314 | regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); |
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