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hc
2024-05-14 bedbef8ad3e75a304af6361af235302bcc61d06b 
 kernel/include/linux/brcmphy.h
....@@ -15,7 +15,9 @@
1515 #define PHY_ID_BCMAC131			0x0143bc70
1616 #define PHY_ID_BCM5481			0x0143bca0
1717 #define PHY_ID_BCM5395			0x0143bcf0
18
+#define PHY_ID_BCM53125			0x03625f20
1819 #define PHY_ID_BCM54810			0x03625d00
20
+#define PHY_ID_BCM54811			0x03625cc0
1921 #define PHY_ID_BCM5482			0x0143bcb0
2022 #define PHY_ID_BCM5411			0x00206070
2123 #define PHY_ID_BCM5421			0x002060e0
....@@ -24,10 +26,13 @@
2426 #define PHY_ID_BCM5461			0x002060c0
2527 #define PHY_ID_BCM54612E		0x03625e60
2628 #define PHY_ID_BCM54616S		0x03625d10
29
+#define PHY_ID_BCM54140			0xae025009
2730 #define PHY_ID_BCM57780			0x03625d90
2831 #define PHY_ID_BCM89610			0x03625cd0
2932 
33
+#define PHY_ID_BCM72113			0x35905310
3034 #define PHY_ID_BCM7250			0xae025280
35
+#define PHY_ID_BCM7255			0xae025120
3136 #define PHY_ID_BCM7260			0xae025190
3237 #define PHY_ID_BCM7268			0xae025090
3338 #define PHY_ID_BCM7271			0xae0253b0
....@@ -78,6 +83,7 @@
7883 #define MII_BCM54XX_ECR		0x10	/* BCM54xx extended control register */
7984 #define MII_BCM54XX_ECR_IM	0x1000	/* Interrupt mask */
8085 #define MII_BCM54XX_ECR_IF	0x0800	/* Interrupt force */
86
+#define MII_BCM54XX_ECR_FIFOE	0x0001	/* FIFO elasticity */
8187 
8288 #define MII_BCM54XX_ESR		0x11	/* BCM54xx extended status register */
8389 #define MII_BCM54XX_ESR_IS	0x1000	/* Interrupt status */
....@@ -112,15 +118,25 @@
112118 #define MII_BCM54XX_SHD_VAL(x)	((x & 0x1f) << 10)
113119 #define MII_BCM54XX_SHD_DATA(x)	((x & 0x3ff) << 0)
114120 
121
+#define MII_BCM54XX_RDB_ADDR	0x1e
122
+#define MII_BCM54XX_RDB_DATA	0x1f
123
+
124
+/* legacy access control via rdb/expansion register */
125
+#define BCM54XX_RDB_REG0087		0x0087
126
+#define BCM54XX_EXP_REG7E		(MII_BCM54XX_EXP_SEL_ER + 0x7E)
127
+#define BCM54XX_ACCESS_MODE_LEGACY_EN	BIT(15)
128
+
115129 /*
116130  * AUXILIARY CONTROL SHADOW ACCESS REGISTERS.  (PHY REG 0x18)
117131  */
118132 #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL	0x00
119133 #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB		0x0400
120134 #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA	0x0800
135
+#define MII_BCM54XX_AUXCTL_ACTL_EXT_PKT_LEN	0x4000
121136 
122137 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC			0x07
123138 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN	0x0010
139
+#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN	0x0080
124140 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN	0x0100
125141 #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX		0x0200
126142 #define MII_BCM54XX_AUXCTL_MISC_WREN			0x8000
....@@ -147,6 +163,22 @@
147163 #define BCM_LED_SRC_OFF		0xe	/* Tied high */
148164 #define BCM_LED_SRC_ON		0xf	/* Tied low */
149165 
166
+/*
167
+ * Broadcom Multicolor LED configurations (expansion register 4)
168
+ */
169
+#define BCM_EXP_MULTICOLOR		(MII_BCM54XX_EXP_SEL_ER + 0x04)
170
+#define BCM_LED_MULTICOLOR_IN_PHASE	BIT(8)
171
+#define BCM_LED_MULTICOLOR_LINK_ACT	0x0
172
+#define BCM_LED_MULTICOLOR_SPEED	0x1
173
+#define BCM_LED_MULTICOLOR_ACT_FLASH	0x2
174
+#define BCM_LED_MULTICOLOR_FDX		0x3
175
+#define BCM_LED_MULTICOLOR_OFF		0x4
176
+#define BCM_LED_MULTICOLOR_ON		0x5
177
+#define BCM_LED_MULTICOLOR_ALT		0x6
178
+#define BCM_LED_MULTICOLOR_FLASH	0x7
179
+#define BCM_LED_MULTICOLOR_LINK		0x8
180
+#define BCM_LED_MULTICOLOR_ACT		0x9
181
+#define BCM_LED_MULTICOLOR_PROGRAM	0xa
150182 
151183 /*
152184  * BCM5482: Shadow registers
....@@ -183,9 +215,18 @@
183215 #define BCM5482_SHD_SSD		0x14	/* 10100: Secondary SerDes control */
184216 #define BCM5482_SHD_SSD_LEDM	0x0008	/* SSD LED Mode enable */
185217 #define BCM5482_SHD_SSD_EN	0x0001	/* SSD enable */
186
-#define BCM5482_SHD_MODE	0x1f	/* 11111: Mode Control Register */
187
-#define BCM5482_SHD_MODE_1000BX	0x0001	/* Enable 1000BASE-X registers */
188218 
219
+/* 10011: SerDes 100-FX Control Register */
220
+#define BCM54616S_SHD_100FX_CTRL	0x13
221
+#define	BCM54616S_100FX_MODE		BIT(0)	/* 100-FX SerDes Enable */
222
+
223
+/* 11111: Mode Control Register */
224
+#define BCM54XX_SHD_MODE		0x1f
225
+#define BCM54XX_SHD_INTF_SEL_MASK	GENMASK(2, 1)	/* INTERF_SEL[1:0] */
226
+#define BCM54XX_SHD_INTF_SEL_RGMII	0x02
227
+#define BCM54XX_SHD_INTF_SEL_SGMII	0x04
228
+#define BCM54XX_SHD_INTF_SEL_GBIC	0x06
229
+#define BCM54XX_SHD_MODE_1000BX		BIT(0)	/* Enable 1000-X registers */
189230 
190231 /*
191232  * EXPANSION SHADOW ACCESS REGISTERS.  (PHY REG 0x15, 0x16, and 0x17)
....@@ -220,6 +261,7 @@
220261 #define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN	(1 << 0)
221262 #define BCM54810_SHD_CLK_CTL			0x3
222263 #define BCM54810_SHD_CLK_CTL_GTXCLK_EN		(1 << 9)
264
+#define BCM54810_SHD_SCR3_TRDDAPD		0x0100
223265 
224266 /* BCM54612E Registers */
225267 #define BCM54612E_EXP_SPARE0		(MII_BCM54XX_EXP_SEL_ETC + 0x34)
....@@ -264,4 +306,51 @@
264306 #define MII_BRCM_CORE_EXPB0	0xB0
265307 #define MII_BRCM_CORE_EXPB1	0xB1
266308 
309
+/* Enhanced Cable Diagnostics */
310
+#define BCM54XX_RDB_ECD_CTRL			0x2a0
311
+#define BCM54XX_EXP_ECD_CTRL			(MII_BCM54XX_EXP_SEL_ER + 0xc0)
312
+
313
+#define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT3	1	/* CAT3 or worse */
314
+#define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT5	0	/* CAT5 or better */
315
+#define BCM54XX_ECD_CTRL_CABLE_TYPE_MASK	BIT(0)	/* cable type */
316
+#define BCM54XX_ECD_CTRL_INVALID		BIT(3)	/* invalid result */
317
+#define BCM54XX_ECD_CTRL_UNIT_CM		0	/* centimeters */
318
+#define BCM54XX_ECD_CTRL_UNIT_M			1	/* meters */
319
+#define BCM54XX_ECD_CTRL_UNIT_MASK		BIT(10)	/* cable length unit */
320
+#define BCM54XX_ECD_CTRL_IN_PROGRESS		BIT(11)	/* test in progress */
321
+#define BCM54XX_ECD_CTRL_BREAK_LINK		BIT(12)	/* unconnect link
322
+							 * during test
323
+							 */
324
+#define BCM54XX_ECD_CTRL_CROSS_SHORT_DIS	BIT(13)	/* disable inter-pair
325
+							 * short check
326
+							 */
327
+#define BCM54XX_ECD_CTRL_RUN			BIT(15)	/* run immediate */
328
+
329
+#define BCM54XX_RDB_ECD_FAULT_TYPE		0x2a1
330
+#define BCM54XX_EXP_ECD_FAULT_TYPE		(MII_BCM54XX_EXP_SEL_ER + 0xc1)
331
+#define BCM54XX_ECD_FAULT_TYPE_INVALID		0x0
332
+#define BCM54XX_ECD_FAULT_TYPE_OK		0x1
333
+#define BCM54XX_ECD_FAULT_TYPE_OPEN		0x2
334
+#define BCM54XX_ECD_FAULT_TYPE_SAME_SHORT	0x3 /* short same pair */
335
+#define BCM54XX_ECD_FAULT_TYPE_CROSS_SHORT	0x4 /* short different pairs */
336
+#define BCM54XX_ECD_FAULT_TYPE_BUSY		0x9
337
+#define BCM54XX_ECD_FAULT_TYPE_PAIR_D_MASK	GENMASK(3, 0)
338
+#define BCM54XX_ECD_FAULT_TYPE_PAIR_C_MASK	GENMASK(7, 4)
339
+#define BCM54XX_ECD_FAULT_TYPE_PAIR_B_MASK	GENMASK(11, 8)
340
+#define BCM54XX_ECD_FAULT_TYPE_PAIR_A_MASK	GENMASK(15, 12)
341
+#define BCM54XX_ECD_PAIR_A_LENGTH_RESULTS	0x2a2
342
+#define BCM54XX_ECD_PAIR_B_LENGTH_RESULTS	0x2a3
343
+#define BCM54XX_ECD_PAIR_C_LENGTH_RESULTS	0x2a4
344
+#define BCM54XX_ECD_PAIR_D_LENGTH_RESULTS	0x2a5
345
+
346
+#define BCM54XX_RDB_ECD_PAIR_A_LENGTH_RESULTS	0x2a2
347
+#define BCM54XX_EXP_ECD_PAIR_A_LENGTH_RESULTS	(MII_BCM54XX_EXP_SEL_ER + 0xc2)
348
+#define BCM54XX_RDB_ECD_PAIR_B_LENGTH_RESULTS	0x2a3
349
+#define BCM54XX_EXP_ECD_PAIR_B_LENGTH_RESULTS	(MII_BCM54XX_EXP_SEL_ER + 0xc3)
350
+#define BCM54XX_RDB_ECD_PAIR_C_LENGTH_RESULTS	0x2a4
351
+#define BCM54XX_EXP_ECD_PAIR_C_LENGTH_RESULTS	(MII_BCM54XX_EXP_SEL_ER + 0xc4)
352
+#define BCM54XX_RDB_ECD_PAIR_D_LENGTH_RESULTS	0x2a5
353
+#define BCM54XX_EXP_ECD_PAIR_D_LENGTH_RESULTS	(MII_BCM54XX_EXP_SEL_ER + 0xc5)
354
+#define BCM54XX_ECD_LENGTH_RESULTS_INVALID	0xffff
355
+
267356 #endif /* _LINUX_BRCMPHY_H */