修改内核路径

hc

2024-05-14 bedbef8ad3e75a304af6361af235302bcc61d06b

 kernel/drivers/soundwire/cadence_master.h
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@@ -8,6 +8,12 @@
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 #define SDW_CADENCE_GSYNC_KHZ		4 /* 4 kHz */
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 #define SDW_CADENCE_GSYNC_HZ		(SDW_CADENCE_GSYNC_KHZ * 1000)
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+/*
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+ * The Cadence IP supports up to 32 entries in the FIFO, though implementations
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+ * can configure the IP to have a smaller FIFO.
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+ */
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+#define CDNS_MCP_IP_MAX_CMD_LEN		32
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+
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 /**
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  * struct sdw_cdns_pdi: PDI (Physical Data Interface) instance
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  *
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@@ -119,7 +125,12 @@
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 	struct sdw_bus bus;
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 	unsigned int instance;
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-	u32 response_buf[0x80];
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+	/*
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+	 * The datasheet says the RX FIFO AVAIL can be 2 entries more
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+	 * than the FIFO capacity, so allow for this.
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+	 */
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+	u32 response_buf[CDNS_MCP_IP_MAX_CMD_LEN + 2];
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+
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 	struct completion tx_complete;
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 	struct sdw_defer *defer;
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