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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
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1 | 2 | /* |
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2 | 3 | * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. |
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3 | 4 | * |
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.. | .. |
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6 | 7 | * |
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7 | 8 | * Description: |
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8 | 9 | * QE UCC Fast API Set - UCC Fast specific routines implementations. |
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9 | | - * |
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10 | | - * This program is free software; you can redistribute it and/or modify it |
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11 | | - * under the terms of the GNU General Public License as published by the |
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12 | | - * Free Software Foundation; either version 2 of the License, or (at your |
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13 | | - * option) any later version. |
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14 | 10 | */ |
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15 | 11 | #include <linux/kernel.h> |
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16 | 12 | #include <linux/errno.h> |
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.. | .. |
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33 | 29 | printk(KERN_INFO "Base address: 0x%p\n", uccf->uf_regs); |
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34 | 30 | |
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35 | 31 | printk(KERN_INFO "gumr : addr=0x%p, val=0x%08x\n", |
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36 | | - &uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr)); |
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| 32 | + &uccf->uf_regs->gumr, qe_ioread32be(&uccf->uf_regs->gumr)); |
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37 | 33 | printk(KERN_INFO "upsmr : addr=0x%p, val=0x%08x\n", |
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38 | | - &uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr)); |
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| 34 | + &uccf->uf_regs->upsmr, qe_ioread32be(&uccf->uf_regs->upsmr)); |
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39 | 35 | printk(KERN_INFO "utodr : addr=0x%p, val=0x%04x\n", |
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40 | | - &uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr)); |
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| 36 | + &uccf->uf_regs->utodr, qe_ioread16be(&uccf->uf_regs->utodr)); |
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41 | 37 | printk(KERN_INFO "udsr : addr=0x%p, val=0x%04x\n", |
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42 | | - &uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr)); |
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| 38 | + &uccf->uf_regs->udsr, qe_ioread16be(&uccf->uf_regs->udsr)); |
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43 | 39 | printk(KERN_INFO "ucce : addr=0x%p, val=0x%08x\n", |
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44 | | - &uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce)); |
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| 40 | + &uccf->uf_regs->ucce, qe_ioread32be(&uccf->uf_regs->ucce)); |
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45 | 41 | printk(KERN_INFO "uccm : addr=0x%p, val=0x%08x\n", |
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46 | | - &uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm)); |
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| 42 | + &uccf->uf_regs->uccm, qe_ioread32be(&uccf->uf_regs->uccm)); |
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47 | 43 | printk(KERN_INFO "uccs : addr=0x%p, val=0x%02x\n", |
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48 | | - &uccf->uf_regs->uccs, in_8(&uccf->uf_regs->uccs)); |
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| 44 | + &uccf->uf_regs->uccs, qe_ioread8(&uccf->uf_regs->uccs)); |
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49 | 45 | printk(KERN_INFO "urfb : addr=0x%p, val=0x%08x\n", |
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50 | | - &uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb)); |
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| 46 | + &uccf->uf_regs->urfb, qe_ioread32be(&uccf->uf_regs->urfb)); |
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51 | 47 | printk(KERN_INFO "urfs : addr=0x%p, val=0x%04x\n", |
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52 | | - &uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs)); |
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| 48 | + &uccf->uf_regs->urfs, qe_ioread16be(&uccf->uf_regs->urfs)); |
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53 | 49 | printk(KERN_INFO "urfet : addr=0x%p, val=0x%04x\n", |
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54 | | - &uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet)); |
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| 50 | + &uccf->uf_regs->urfet, qe_ioread16be(&uccf->uf_regs->urfet)); |
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55 | 51 | printk(KERN_INFO "urfset: addr=0x%p, val=0x%04x\n", |
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56 | | - &uccf->uf_regs->urfset, in_be16(&uccf->uf_regs->urfset)); |
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| 52 | + &uccf->uf_regs->urfset, |
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| 53 | + qe_ioread16be(&uccf->uf_regs->urfset)); |
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57 | 54 | printk(KERN_INFO "utfb : addr=0x%p, val=0x%08x\n", |
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58 | | - &uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb)); |
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| 55 | + &uccf->uf_regs->utfb, qe_ioread32be(&uccf->uf_regs->utfb)); |
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59 | 56 | printk(KERN_INFO "utfs : addr=0x%p, val=0x%04x\n", |
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60 | | - &uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs)); |
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| 57 | + &uccf->uf_regs->utfs, qe_ioread16be(&uccf->uf_regs->utfs)); |
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61 | 58 | printk(KERN_INFO "utfet : addr=0x%p, val=0x%04x\n", |
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62 | | - &uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet)); |
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| 59 | + &uccf->uf_regs->utfet, qe_ioread16be(&uccf->uf_regs->utfet)); |
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63 | 60 | printk(KERN_INFO "utftt : addr=0x%p, val=0x%04x\n", |
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64 | | - &uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt)); |
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| 61 | + &uccf->uf_regs->utftt, qe_ioread16be(&uccf->uf_regs->utftt)); |
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65 | 62 | printk(KERN_INFO "utpt : addr=0x%p, val=0x%04x\n", |
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66 | | - &uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt)); |
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| 63 | + &uccf->uf_regs->utpt, qe_ioread16be(&uccf->uf_regs->utpt)); |
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67 | 64 | printk(KERN_INFO "urtry : addr=0x%p, val=0x%08x\n", |
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68 | | - &uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry)); |
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| 65 | + &uccf->uf_regs->urtry, qe_ioread32be(&uccf->uf_regs->urtry)); |
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69 | 66 | printk(KERN_INFO "guemr : addr=0x%p, val=0x%02x\n", |
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70 | | - &uccf->uf_regs->guemr, in_8(&uccf->uf_regs->guemr)); |
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| 67 | + &uccf->uf_regs->guemr, qe_ioread8(&uccf->uf_regs->guemr)); |
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71 | 68 | } |
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72 | 69 | EXPORT_SYMBOL(ucc_fast_dump_regs); |
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73 | 70 | |
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.. | .. |
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89 | 86 | |
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90 | 87 | void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf) |
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91 | 88 | { |
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92 | | - out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD); |
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| 89 | + qe_iowrite16be(UCC_FAST_TOD, &uccf->uf_regs->utodr); |
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93 | 90 | } |
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94 | 91 | EXPORT_SYMBOL(ucc_fast_transmit_on_demand); |
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95 | 92 | |
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.. | .. |
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101 | 98 | uf_regs = uccf->uf_regs; |
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102 | 99 | |
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103 | 100 | /* Enable reception and/or transmission on this UCC. */ |
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104 | | - gumr = in_be32(&uf_regs->gumr); |
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| 101 | + gumr = qe_ioread32be(&uf_regs->gumr); |
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105 | 102 | if (mode & COMM_DIR_TX) { |
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106 | 103 | gumr |= UCC_FAST_GUMR_ENT; |
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107 | 104 | uccf->enabled_tx = 1; |
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.. | .. |
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110 | 107 | gumr |= UCC_FAST_GUMR_ENR; |
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111 | 108 | uccf->enabled_rx = 1; |
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112 | 109 | } |
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113 | | - out_be32(&uf_regs->gumr, gumr); |
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| 110 | + qe_iowrite32be(gumr, &uf_regs->gumr); |
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114 | 111 | } |
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115 | 112 | EXPORT_SYMBOL(ucc_fast_enable); |
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116 | 113 | |
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.. | .. |
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122 | 119 | uf_regs = uccf->uf_regs; |
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123 | 120 | |
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124 | 121 | /* Disable reception and/or transmission on this UCC. */ |
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125 | | - gumr = in_be32(&uf_regs->gumr); |
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| 122 | + gumr = qe_ioread32be(&uf_regs->gumr); |
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126 | 123 | if (mode & COMM_DIR_TX) { |
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127 | 124 | gumr &= ~UCC_FAST_GUMR_ENT; |
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128 | 125 | uccf->enabled_tx = 0; |
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.. | .. |
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131 | 128 | gumr &= ~UCC_FAST_GUMR_ENR; |
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132 | 129 | uccf->enabled_rx = 0; |
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133 | 130 | } |
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134 | | - out_be32(&uf_regs->gumr, gumr); |
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| 131 | + qe_iowrite32be(gumr, &uf_regs->gumr); |
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135 | 132 | } |
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136 | 133 | EXPORT_SYMBOL(ucc_fast_disable); |
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137 | 134 | |
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.. | .. |
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200 | 197 | __func__); |
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201 | 198 | return -ENOMEM; |
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202 | 199 | } |
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| 200 | + uccf->ucc_fast_tx_virtual_fifo_base_offset = -1; |
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| 201 | + uccf->ucc_fast_rx_virtual_fifo_base_offset = -1; |
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203 | 202 | |
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204 | 203 | /* Fill fast UCC structure */ |
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205 | 204 | uccf->uf_info = uf_info; |
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.. | .. |
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263 | 262 | gumr |= uf_info->tenc; |
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264 | 263 | gumr |= uf_info->tcrc; |
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265 | 264 | gumr |= uf_info->mode; |
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266 | | - out_be32(&uf_regs->gumr, gumr); |
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| 265 | + qe_iowrite32be(gumr, &uf_regs->gumr); |
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267 | 266 | |
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268 | 267 | /* Allocate memory for Tx Virtual Fifo */ |
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269 | 268 | uccf->ucc_fast_tx_virtual_fifo_base_offset = |
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270 | 269 | qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); |
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271 | | - if (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) { |
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| 270 | + if (uccf->ucc_fast_tx_virtual_fifo_base_offset < 0) { |
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272 | 271 | printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO\n", |
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273 | 272 | __func__); |
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274 | | - uccf->ucc_fast_tx_virtual_fifo_base_offset = 0; |
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275 | 273 | ucc_fast_free(uccf); |
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276 | 274 | return -ENOMEM; |
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277 | 275 | } |
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.. | .. |
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281 | 279 | qe_muram_alloc(uf_info->urfs + |
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282 | 280 | UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR, |
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283 | 281 | UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); |
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284 | | - if (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) { |
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| 282 | + if (uccf->ucc_fast_rx_virtual_fifo_base_offset < 0) { |
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285 | 283 | printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO\n", |
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286 | 284 | __func__); |
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287 | | - uccf->ucc_fast_rx_virtual_fifo_base_offset = 0; |
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288 | 285 | ucc_fast_free(uccf); |
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289 | 286 | return -ENOMEM; |
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290 | 287 | } |
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291 | 288 | |
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292 | 289 | /* Set Virtual Fifo registers */ |
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293 | | - out_be16(&uf_regs->urfs, uf_info->urfs); |
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294 | | - out_be16(&uf_regs->urfet, uf_info->urfet); |
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295 | | - out_be16(&uf_regs->urfset, uf_info->urfset); |
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296 | | - out_be16(&uf_regs->utfs, uf_info->utfs); |
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297 | | - out_be16(&uf_regs->utfet, uf_info->utfet); |
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298 | | - out_be16(&uf_regs->utftt, uf_info->utftt); |
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| 290 | + qe_iowrite16be(uf_info->urfs, &uf_regs->urfs); |
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| 291 | + qe_iowrite16be(uf_info->urfet, &uf_regs->urfet); |
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| 292 | + qe_iowrite16be(uf_info->urfset, &uf_regs->urfset); |
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| 293 | + qe_iowrite16be(uf_info->utfs, &uf_regs->utfs); |
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| 294 | + qe_iowrite16be(uf_info->utfet, &uf_regs->utfet); |
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| 295 | + qe_iowrite16be(uf_info->utftt, &uf_regs->utftt); |
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299 | 296 | /* utfb, urfb are offsets from MURAM base */ |
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300 | | - out_be32(&uf_regs->utfb, uccf->ucc_fast_tx_virtual_fifo_base_offset); |
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301 | | - out_be32(&uf_regs->urfb, uccf->ucc_fast_rx_virtual_fifo_base_offset); |
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| 297 | + qe_iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset, |
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| 298 | + &uf_regs->utfb); |
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| 299 | + qe_iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset, |
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| 300 | + &uf_regs->urfb); |
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302 | 301 | |
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303 | 302 | /* Mux clocking */ |
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304 | 303 | /* Grant Support */ |
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.. | .. |
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366 | 365 | } |
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367 | 366 | |
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368 | 367 | /* Set interrupt mask register at UCC level. */ |
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369 | | - out_be32(&uf_regs->uccm, uf_info->uccm_mask); |
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| 368 | + qe_iowrite32be(uf_info->uccm_mask, &uf_regs->uccm); |
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370 | 369 | |
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371 | 370 | /* First, clear anything pending at UCC level, |
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372 | 371 | * otherwise, old garbage may come through |
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373 | 372 | * as soon as the dam is opened. */ |
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374 | 373 | |
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375 | 374 | /* Writing '1' clears */ |
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376 | | - out_be32(&uf_regs->ucce, 0xffffffff); |
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| 375 | + qe_iowrite32be(0xffffffff, &uf_regs->ucce); |
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377 | 376 | |
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378 | 377 | *uccf_ret = uccf; |
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379 | 378 | return 0; |
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.. | .. |
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385 | 384 | if (!uccf) |
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386 | 385 | return; |
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387 | 386 | |
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388 | | - if (uccf->ucc_fast_tx_virtual_fifo_base_offset) |
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389 | | - qe_muram_free(uccf->ucc_fast_tx_virtual_fifo_base_offset); |
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390 | | - |
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391 | | - if (uccf->ucc_fast_rx_virtual_fifo_base_offset) |
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392 | | - qe_muram_free(uccf->ucc_fast_rx_virtual_fifo_base_offset); |
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| 387 | + qe_muram_free(uccf->ucc_fast_tx_virtual_fifo_base_offset); |
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| 388 | + qe_muram_free(uccf->ucc_fast_rx_virtual_fifo_base_offset); |
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393 | 389 | |
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394 | 390 | if (uccf->uf_regs) |
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395 | 391 | iounmap(uccf->uf_regs); |
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