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2024-05-14 bedbef8ad3e75a304af6361af235302bcc61d06b 
 kernel/drivers/pinctrl/pinctrl-amd.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * GPIO driver for AMD
34  *
....@@ -5,13 +6,8 @@
56  * Authors: Ken Xue <Ken.Xue@amd.com>
67  *      Wu, Jeff <Jeff.Wu@amd.com>
78  *
8
- * This program is free software; you can redistribute it and/or modify it
9
- * under the terms and conditions of the GNU General Public License,
10
- * version 2, as published by the Free Software Foundation.
11
- *
129  * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
1310  *			Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
14
- *
1511  */
1612 
1713 #include <linux/err.h>
....@@ -24,7 +20,7 @@
2420 #include <linux/errno.h>
2521 #include <linux/log2.h>
2622 #include <linux/io.h>
27
-#include <linux/gpio.h>
23
+#include <linux/gpio/driver.h>
2824 #include <linux/slab.h>
2925 #include <linux/platform_device.h>
3026 #include <linux/mutex.h>
....@@ -50,7 +46,10 @@
5046 	pin_reg = readl(gpio_dev->base + offset * 4);
5147 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
5248 
53
-	return !(pin_reg & BIT(OUTPUT_ENABLE_OFF));
49
+	if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
50
+		return GPIO_LINE_DIRECTION_OUT;
51
+
52
+	return GPIO_LINE_DIRECTION_IN;
5453 }
5554 
5655 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
....@@ -127,6 +126,14 @@
127126 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
128127 
129128 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
129
+
130
+	/* Use special handling for Pin0 debounce */
131
+	if (offset == 0) {
132
+		pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
133
+		if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
134
+			debounce = 0;
135
+	}
136
+
130137 	pin_reg = readl(gpio_dev->base + offset * 4);
131138 
132139 	if (debounce) {
....@@ -182,18 +189,6 @@
182189 	return ret;
183190 }
184191 
185
-static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
186
-			       unsigned long config)
187
-{
188
-	u32 debounce;
189
-
190
-	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
191
-		return -ENOTSUPP;
192
-
193
-	debounce = pinconf_to_config_argument(config);
194
-	return amd_gpio_set_debounce(gc, offset, debounce);
195
-}
196
-
197192 #ifdef CONFIG_DEBUG_FS
198193 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
199194 {
....@@ -216,6 +211,7 @@
216211 	char *output_value;
217212 	char *output_enable;
218213 
214
+	seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG));
219215 	for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
220216 		seq_printf(s, "GPIO bank%d\t", bank);
221217 
....@@ -418,21 +414,12 @@
418414 {
419415 	int ret = 0;
420416 	u32 pin_reg, pin_reg_irq_en, mask;
421
-	unsigned long flags, irq_flags;
417
+	unsigned long flags;
422418 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
423419 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
424420 
425421 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
426422 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
427
-
428
-	/* Ignore the settings coming from the client and
429
-	 * read the values from the ACPI tables
430
-	 * while setting the trigger type
431
-	 */
432
-
433
-	irq_flags = irq_get_trigger_type(d->irq);
434
-	if (irq_flags != IRQ_TYPE_NONE)
435
-		type = irq_flags;
436423 
437424 	switch (type & IRQ_TYPE_SENSE_MASK) {
438425 	case IRQ_TYPE_EDGE_RISING:
....@@ -482,7 +469,7 @@
482469 	/*
483470 	 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
484471 	 * debounce registers of any GPIO will block wake/interrupt status
485
-	 * generation for *all* GPIOs for a lenght of time that depends on
472
+	 * generation for *all* GPIOs for a length of time that depends on
486473 	 * WAKE_INT_MASTER_REG.MaskStsLength[11:0].  During this period the
487474 	 * INTERRUPT_ENABLE bit will read as 0.
488475 	 *
....@@ -666,7 +653,7 @@
666653 		break;
667654 
668655 	default:
669
-		dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
656
+		dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
670657 			param);
671658 		return -ENOTSUPP;
672659 	}
....@@ -677,7 +664,7 @@
677664 }
678665 
679666 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
680
-				unsigned long *configs, unsigned num_configs)
667
+			   unsigned long *configs, unsigned int num_configs)
681668 {
682669 	int i;
683670 	u32 arg;
....@@ -719,7 +706,7 @@
719706 			break;
720707 
721708 		default:
722
-			dev_err(&gpio_dev->pdev->dev,
709
+			dev_dbg(&gpio_dev->pdev->dev,
723710 				"Invalid config param %04x\n", param);
724711 			ret = -ENOTSUPP;
725712 		}
....@@ -767,12 +754,54 @@
767754 	return 0;
768755 }
769756 
757
+static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin,
758
+			       unsigned long config)
759
+{
760
+	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
761
+
762
+	if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) {
763
+		u32 debounce = pinconf_to_config_argument(config);
764
+
765
+		return amd_gpio_set_debounce(gc, pin, debounce);
766
+	}
767
+
768
+	return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1);
769
+}
770
+
770771 static const struct pinconf_ops amd_pinconf_ops = {
771772 	.pin_config_get		= amd_pinconf_get,
772773 	.pin_config_set		= amd_pinconf_set,
773774 	.pin_config_group_get = amd_pinconf_group_get,
774775 	.pin_config_group_set = amd_pinconf_group_set,
775776 };
777
+
778
+static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
779
+{
780
+	struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
781
+	unsigned long flags;
782
+	u32 pin_reg, mask;
783
+	int i;
784
+
785
+	mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
786
+		BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) |
787
+		BIT(WAKE_CNTRL_OFF_S4);
788
+
789
+	for (i = 0; i < desc->npins; i++) {
790
+		int pin = desc->pins[i].number;
791
+		const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
792
+
793
+		if (!pd)
794
+			continue;
795
+
796
+		raw_spin_lock_irqsave(&gpio_dev->lock, flags);
797
+
798
+		pin_reg = readl(gpio_dev->base + pin * 4);
799
+		pin_reg &= ~mask;
800
+		writel(pin_reg, gpio_dev->base + pin * 4);
801
+
802
+		raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
803
+	}
804
+}
776805 
777806 #ifdef CONFIG_PM_SLEEP
778807 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
....@@ -795,9 +824,9 @@
795824 
796825 static int amd_gpio_suspend(struct device *dev)
797826 {
798
-	struct platform_device *pdev = to_platform_device(dev);
799
-	struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
827
+	struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
800828 	struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
829
+	unsigned long flags;
801830 	int i;
802831 
803832 	for (i = 0; i < desc->npins; i++) {
....@@ -806,7 +835,9 @@
806835 		if (!amd_gpio_should_save(gpio_dev, pin))
807836 			continue;
808837 
809
-		gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4);
838
+		raw_spin_lock_irqsave(&gpio_dev->lock, flags);
839
+		gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING;
840
+		raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
810841 	}
811842 
812843 	return 0;
....@@ -814,9 +845,9 @@
814845 
815846 static int amd_gpio_resume(struct device *dev)
816847 {
817
-	struct platform_device *pdev = to_platform_device(dev);
818
-	struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
848
+	struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
819849 	struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
850
+	unsigned long flags;
820851 	int i;
821852 
822853 	for (i = 0; i < desc->npins; i++) {
....@@ -825,7 +856,10 @@
825856 		if (!amd_gpio_should_save(gpio_dev, pin))
826857 			continue;
827858 
828
-		writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4);
859
+		raw_spin_lock_irqsave(&gpio_dev->lock, flags);
860
+		gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;
861
+		writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4);
862
+		raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
829863 	}
830864 
831865 	return 0;
....@@ -851,6 +885,7 @@
851885 	int irq_base;
852886 	struct resource *res;
853887 	struct amd_gpio *gpio_dev;
888
+	struct gpio_irq_chip *girq;
854889 
855890 	gpio_dev = devm_kzalloc(&pdev->dev,
856891 				sizeof(struct amd_gpio), GFP_KERNEL);
....@@ -865,16 +900,14 @@
865900 		return -EINVAL;
866901 	}
867902 
868
-	gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
903
+	gpio_dev->base = devm_ioremap(&pdev->dev, res->start,
869904 						resource_size(res));
870905 	if (!gpio_dev->base)
871906 		return -ENOMEM;
872907 
873908 	irq_base = platform_get_irq(pdev, 0);
874
-	if (irq_base < 0) {
875
-		dev_err(&pdev->dev, "Failed to get gpio IRQ: %d\n", irq_base);
909
+	if (irq_base < 0)
876910 		return irq_base;
877
-	}
878911 
879912 #ifdef CONFIG_PM_SLEEP
880913 	gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
....@@ -914,6 +947,18 @@
914947 		return PTR_ERR(gpio_dev->pctrl);
915948 	}
916949 
950
+	/* Disable and mask interrupts */
951
+	amd_gpio_irq_init(gpio_dev);
952
+
953
+	girq = &gpio_dev->gc.irq;
954
+	girq->chip = &amd_gpio_irqchip;
955
+	/* This will let us handle the parent IRQ in the driver */
956
+	girq->parent_handler = NULL;
957
+	girq->num_parents = 0;
958
+	girq->parents = NULL;
959
+	girq->default_type = IRQ_TYPE_NONE;
960
+	girq->handler = handle_simple_irq;
961
+
917962 	ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
918963 	if (ret)
919964 		return ret;
....@@ -925,19 +970,8 @@
925970 		goto out2;
926971 	}
927972 
928
-	ret = gpiochip_irqchip_add(&gpio_dev->gc,
929
-				&amd_gpio_irqchip,
930
-				0,
931
-				handle_simple_irq,
932
-				IRQ_TYPE_NONE);
933
-	if (ret) {
934
-		dev_err(&pdev->dev, "could not add irqchip\n");
935
-		ret = -ENODEV;
936
-		goto out2;
937
-	}
938
-
939
-	ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0,
940
-			       KBUILD_MODNAME, gpio_dev);
973
+	ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler,
974
+			       IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
941975 	if (ret)
942976 		goto out2;
943977 
....@@ -963,6 +997,7 @@
963997 	return 0;
964998 }
965999 
1000
+#ifdef CONFIG_ACPI
9661001 static const struct acpi_device_id amd_gpio_acpi_match[] = {
9671002 	{ "AMD0030", 0 },
9681003 	{ "AMDI0030", 0},
....@@ -970,6 +1005,7 @@
9701005 	{ },
9711006 };
9721007 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
1008
+#endif
9731009 
9741010 static struct platform_driver amd_gpio_driver = {
9751011 	.driver		= {