~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,19 +1,8 @@
	1	+/* SPDX-License-Identifier: ISC */
1	2	/*
2	3	* Copyright (c) 2005-2011 Atheros Communications Inc.
3	4	* Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
4		- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
5		- *
6		- * Permission to use, copy, modify, and/or distribute this software for any
7		- * purpose with or without fee is hereby granted, provided that the above
8		- * copyright notice and this permission notice appear in all copies.
9		- *
10		- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11		- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12		- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13		- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14		- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15		- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16		- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	5	+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
17	6	*/
18	7
19	8	#ifndef _CORE_H_
..	..	@@ -90,15 +79,12 @@
90	79	/* The magic used by QCA spec */
91	80	#define ATH10K_SMBIOS_BDF_EXT_MAGIC "BDF_"
92	81
93		-struct ath10k;
	82	+/* Default Airtime weight multipler (Tuned for multiclient performance) */
	83	+#define ATH10K_AIRTIME_WEIGHT_MULTIPLIER 4
94	84
95		-enum ath10k_bus {
96		- ATH10K_BUS_PCI,
97		- ATH10K_BUS_AHB,
98		- ATH10K_BUS_SDIO,
99		- ATH10K_BUS_USB,
100		- ATH10K_BUS_SNOC,
101		-};
	85	+#define ATH10K_MAX_RETRY_COUNT 30
	86	+
	87	+struct ath10k;
102	88
103	89	static inline const char *ath10k_bus_str(enum ath10k_bus bus)
104	90	{
..	..	@@ -124,6 +110,8 @@
124	110	ATH10K_SKB_F_DELIVER_CAB = BIT(2),
125	111	ATH10K_SKB_F_MGMT = BIT(3),
126	112	ATH10K_SKB_F_QOS = BIT(4),
	113	+ ATH10K_SKB_F_RAW_TX = BIT(5),
	114	+ ATH10K_SKB_F_NOACK_TID = BIT(6),
127	115	};
128	116
129	117	struct ath10k_skb_cb {
..	..	@@ -131,13 +119,16 @@
131	119	u8 flags;
132	120	u8 eid;
133	121	u16 msdu_id;
	122	+ u16 airtime_est;
134	123	struct ieee80211_vif *vif;
135	124	struct ieee80211_txq *txq;
	125	+ u32 ucast_cipher;
136	126	} __packed;
137	127
138	128	struct ath10k_skb_rxcb {
139	129	dma_addr_t paddr;
140	130	struct hlist_node hlist;
	131	+ u8 eid;
141	132	};
142	133
143	134	static inline struct ath10k_skb_cb ATH10K_SKB_CB(struct sk_buff skb)
..	..	@@ -161,6 +152,26 @@
161	152	return QCA988X_HOST_INTEREST_ADDRESS + item_offset;
162	153	}
163	154
	155	+enum ath10k_phy_mode {
	156	+ ATH10K_PHY_MODE_LEGACY = 0,
	157	+ ATH10K_PHY_MODE_HT = 1,
	158	+ ATH10K_PHY_MODE_VHT = 2,
	159	+};
	160	+
	161	+/* Data rate 100KBPS based on IE Index */
	162	+struct ath10k_index_ht_data_rate_type {
	163	+ u8 beacon_rate_index;
	164	+ u16 supported_rate[4];
	165	+};
	166	+
	167	+/* Data rate 100KBPS based on IE Index */
	168	+struct ath10k_index_vht_data_rate_type {
	169	+ u8 beacon_rate_index;
	170	+ u16 supported_VHT80_rate[2];
	171	+ u16 supported_VHT40_rate[2];
	172	+ u16 supported_VHT20_rate[2];
	173	+};
	174	+
164	175	struct ath10k_bmi {
165	176	bool done_sent;
166	177	};
..	..	@@ -183,6 +194,7 @@
183	194	struct wmi_cmd_map *cmd;
184	195	struct wmi_vdev_param_map *vdev_param;
185	196	struct wmi_pdev_param_map *pdev_param;
	197	+ struct wmi_peer_param_map *peer_param;
186	198	const struct wmi_ops *ops;
187	199	const struct wmi_peer_flags_map *peer_flags;
188	200
..	..	@@ -203,14 +215,14 @@
203	215	u32 peer_rssi;
204	216	u32 peer_tx_rate;
205	217	u32 peer_rx_rate; /* 10x only */
206		- u32 rx_duration;
	218	+ u64 rx_duration;
207	219	};
208	220
209	221	struct ath10k_fw_extd_stats_peer {
210	222	struct list_head list;
211	223
212	224	u8 peer_macaddr[ETH_ALEN];
213		- u32 rx_duration;
	225	+ u64 rx_duration;
214	226	};
215	227
216	228	struct ath10k_fw_stats_vdev {
..	..	@@ -414,6 +426,14 @@
414	426
415	427	/* protected by ar->data_lock */
416	428	struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1];
	429	+ union htt_rx_pn_t tids_last_pn[ATH10K_TXRX_NUM_EXT_TIDS];
	430	+ bool tids_last_pn_valid[ATH10K_TXRX_NUM_EXT_TIDS];
	431	+ union htt_rx_pn_t frag_tids_last_pn[ATH10K_TXRX_NUM_EXT_TIDS];
	432	+ u32 frag_tids_seq[ATH10K_TXRX_NUM_EXT_TIDS];
	433	+ struct {
	434	+ enum htt_security_types sec_type;
	435	+ int pn_len;
	436	+ } rx_pn[ATH10K_HTT_TXRX_PEER_SECURITY_MAX];
417	437	};
418	438
419	439	struct ath10k_txq {
..	..	@@ -451,15 +471,48 @@
451	471	};
452	472
453	473	struct ath10k_sta_tid_stats {
454		- unsigned long int rx_pkt_from_fw;
455		- unsigned long int rx_pkt_unchained;
456		- unsigned long int rx_pkt_drop_chained;
457		- unsigned long int rx_pkt_drop_filter;
458		- unsigned long int rx_pkt_err[ATH10K_PKT_RX_ERR_MAX];
459		- unsigned long int rx_pkt_queued_for_mac;
460		- unsigned long int rx_pkt_ampdu[ATH10K_AMPDU_SUBFRM_NUM_MAX];
461		- unsigned long int rx_pkt_amsdu[ATH10K_AMSDU_SUBFRM_NUM_MAX];
	474	+ unsigned long rx_pkt_from_fw;
	475	+ unsigned long rx_pkt_unchained;
	476	+ unsigned long rx_pkt_drop_chained;
	477	+ unsigned long rx_pkt_drop_filter;
	478	+ unsigned long rx_pkt_err[ATH10K_PKT_RX_ERR_MAX];
	479	+ unsigned long rx_pkt_queued_for_mac;
	480	+ unsigned long rx_pkt_ampdu[ATH10K_AMPDU_SUBFRM_NUM_MAX];
	481	+ unsigned long rx_pkt_amsdu[ATH10K_AMSDU_SUBFRM_NUM_MAX];
462	482	};
	483	+
	484	+enum ath10k_counter_type {
	485	+ ATH10K_COUNTER_TYPE_BYTES,
	486	+ ATH10K_COUNTER_TYPE_PKTS,
	487	+ ATH10K_COUNTER_TYPE_MAX,
	488	+};
	489	+
	490	+enum ath10k_stats_type {
	491	+ ATH10K_STATS_TYPE_SUCC,
	492	+ ATH10K_STATS_TYPE_FAIL,
	493	+ ATH10K_STATS_TYPE_RETRY,
	494	+ ATH10K_STATS_TYPE_AMPDU,
	495	+ ATH10K_STATS_TYPE_MAX,
	496	+};
	497	+
	498	+struct ath10k_htt_data_stats {
	499	+ u64 legacy[ATH10K_COUNTER_TYPE_MAX][ATH10K_LEGACY_NUM];
	500	+ u64 ht[ATH10K_COUNTER_TYPE_MAX][ATH10K_HT_MCS_NUM];
	501	+ u64 vht[ATH10K_COUNTER_TYPE_MAX][ATH10K_VHT_MCS_NUM];
	502	+ u64 bw[ATH10K_COUNTER_TYPE_MAX][ATH10K_BW_NUM];
	503	+ u64 nss[ATH10K_COUNTER_TYPE_MAX][ATH10K_NSS_NUM];
	504	+ u64 gi[ATH10K_COUNTER_TYPE_MAX][ATH10K_GI_NUM];
	505	+ u64 rate_table[ATH10K_COUNTER_TYPE_MAX][ATH10K_RATE_TABLE_NUM];
	506	+};
	507	+
	508	+struct ath10k_htt_tx_stats {
	509	+ struct ath10k_htt_data_stats stats[ATH10K_STATS_TYPE_MAX];
	510	+ u64 tx_duration;
	511	+ u64 ba_fails;
	512	+ u64 ack_fails;
	513	+};
	514	+
	515	+#define ATH10K_TID_MAX 8
463	516
464	517	struct ath10k_sta {
465	518	struct ath10k_vif *arvif;
..	..	@@ -471,9 +524,19 @@
471	524	u32 smps;
472	525	u16 peer_id;
473	526	struct rate_info txrate;
	527	+ struct ieee80211_tx_info tx_info;
	528	+ u32 tx_retries;
	529	+ u32 tx_failed;
	530	+ u32 last_tx_bitrate;
474	531
	532	+ u32 rx_rate_code;
	533	+ u32 rx_bitrate_kbps;
	534	+ u32 tx_rate_code;
	535	+ u32 tx_bitrate_kbps;
475	536	struct work_struct update_wk;
476	537	u64 rx_duration;
	538	+ struct ath10k_htt_tx_stats *tx_stats;
	539	+ u32 ucast_cipher;
477	540
478	541	#ifdef CONFIG_MAC80211_DEBUGFS
479	542	/* protected by conf_mutex */
..	..	@@ -482,9 +545,19 @@
482	545	/* Protected with ar->data_lock */
483	546	struct ath10k_sta_tid_stats tid_stats[IEEE80211_NUM_TIDS + 1];
484	547	#endif
	548	+ /* Protected with ar->data_lock */
	549	+ u32 peer_ps_state;
	550	+ struct work_struct tid_config_wk;
	551	+ int noack[ATH10K_TID_MAX];
	552	+ int retry_long[ATH10K_TID_MAX];
	553	+ int ampdu[ATH10K_TID_MAX];
	554	+ u8 rate_ctrl[ATH10K_TID_MAX];
	555	+ u32 rate_code[ATH10K_TID_MAX];
	556	+ int rtscts[ATH10K_TID_MAX];
485	557	};
486	558
487		-#define ATH10K_VDEV_SETUP_TIMEOUT_HZ (5 * HZ)
	559	+#define ATH10K_VDEV_SETUP_TIMEOUT_HZ (5 * HZ)
	560	+#define ATH10K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ)
488	561
489	562	enum ath10k_beacon_state {
490	563	ATH10K_BEACON_SCHEDULED = 0,
..	..	@@ -544,10 +617,23 @@
544	617	bool nohwcrypt;
545	618	int num_legacy_stations;
546	619	int txpower;
	620	+ bool ftm_responder;
547	621	struct wmi_wmm_params_all_arg wmm_params;
548	622	struct work_struct ap_csa_work;
549	623	struct delayed_work connection_loss_work;
550	624	struct cfg80211_bitrate_mask bitrate_mask;
	625	+
	626	+ /* For setting VHT peer fixed rate, protected by conf_mutex */
	627	+ int vht_num_rates;
	628	+ u8 vht_pfr;
	629	+ u32 tid_conf_changed[ATH10K_TID_MAX];
	630	+ int noack[ATH10K_TID_MAX];
	631	+ int retry_long[ATH10K_TID_MAX];
	632	+ int ampdu[ATH10K_TID_MAX];
	633	+ u8 rate_ctrl[ATH10K_TID_MAX];
	634	+ u32 rate_code[ATH10K_TID_MAX];
	635	+ int rtscts[ATH10K_TID_MAX];
	636	+ u32 tids_rst;
551	637	};
552	638
553	639	struct ath10k_vif_iter {
..	..	@@ -591,6 +677,7 @@
591	677	bool fw_stats_done;
592	678
593	679	unsigned long htt_stats_mask;
	680	+ unsigned long reset_htt_stats;
594	681	struct delayed_work htt_stats_dwork;
595	682	struct ath10k_dfs_stats dfs_stats;
596	683	struct ath_dfs_pool_stats dfs_pool_stats;
..	..	@@ -607,6 +694,8 @@
607	694	u32 reg_addr;
608	695	u32 nf_cal_period;
609	696	void *cal_data;
	697	+ u32 enable_extd_tx_stats;
	698	+ u8 fw_dbglog_mode;
610	699	};
611	700
612	701	enum ath10k_state {
..	..	@@ -733,6 +822,12 @@
733	822
734	823	/* Firmware load is done externally, not by bmi */
735	824	ATH10K_FW_FEATURE_NON_BMI = 19,
	825	+
	826	+ /* Firmware sends only one chan_info event per channel */
	827	+ ATH10K_FW_FEATURE_SINGLE_CHAN_INFO_PER_CHANNEL = 20,
	828	+
	829	+ /* Firmware allows setting peer fixed rate */
	830	+ ATH10K_FW_FEATURE_PEER_FIXED_RATE = 21,
736	831
737	832	/* keep last */
738	833	ATH10K_FW_FEATURE_COUNT,
..	..	@@ -861,6 +956,9 @@
861	956	const struct firmware *board;
862	957	const void *board_data;
863	958	size_t board_len;
	959	+ const struct firmware *ext_board;
	960	+ const void *ext_board_data;
	961	+ size_t ext_board_len;
864	962
865	963	struct ath10k_fw_file fw_file;
866	964	};
..	..	@@ -880,16 +978,34 @@
880	978	u32 reserved2;
881	979	};
882	980
	981	+enum ath10k_dev_type {
	982	+ ATH10K_DEV_TYPE_LL,
	983	+ ATH10K_DEV_TYPE_HL,
	984	+};
	985	+
	986	+struct ath10k_bus_params {
	987	+ u32 chip_id;
	988	+ enum ath10k_dev_type dev_type;
	989	+ bool link_can_suspend;
	990	+ bool hl_msdu_ids;
	991	+};
	992	+
883	993	struct ath10k {
884	994	struct ath_common ath_common;
885	995	struct ieee80211_hw *hw;
886	996	struct ieee80211_ops *ops;
887	997	struct device *dev;
	998	+ struct msa_region {
	999	+ dma_addr_t paddr;
	1000	+ u32 mem_size;
	1001	+ void *vaddr;
	1002	+ } msa;
888	1003	u8 mac_addr[ETH_ALEN];
889	1004
890	1005	enum ath10k_hw_rev hw_rev;
891	1006	u16 dev_id;
892	1007	u32 chip_id;
	1008	+ enum ath10k_dev_type dev_type;
893	1009	u32 target_version;
894	1010	u8 fw_version_major;
895	1011	u32 fw_version_minor;
..	..	@@ -902,13 +1018,24 @@
902	1018	u32 hw_eeprom_rd;
903	1019	u32 ht_cap_info;
904	1020	u32 vht_cap_info;
	1021	+ u32 vht_supp_mcs;
905	1022	u32 num_rf_chains;
906	1023	u32 max_spatial_stream;
907	1024	/* protected by conf_mutex */
	1025	+ u32 low_2ghz_chan;
	1026	+ u32 high_2ghz_chan;
908	1027	u32 low_5ghz_chan;
909	1028	u32 high_5ghz_chan;
910	1029	bool ani_enabled;
	1030	+ u32 sys_cap_info;
911	1031
	1032	+ /* protected by data_lock */
	1033	+ bool hw_rfkill_on;
	1034	+
	1035	+ /* protected by conf_mutex */
	1036	+ u8 ps_state_enable;
	1037	+
	1038	+ bool nlo_enabled;
912	1039	bool p2p;
913	1040
914	1041	struct {
..	..	@@ -917,6 +1044,7 @@
917	1044	} hif;
918	1045
919	1046	struct completion target_suspend;
	1047	+ struct completion driver_recovery;
920	1048
921	1049	const struct ath10k_hw_regs *regs;
922	1050	const struct ath10k_hw_ce_regs *hw_ce_regs;
..	..	@@ -946,8 +1074,13 @@
946	1074	u32 subsystem_device;
947	1075
948	1076	bool bmi_ids_valid;
	1077	+ bool qmi_ids_valid;
	1078	+ u32 qmi_board_id;
	1079	+ u32 qmi_chip_id;
949	1080	u8 bmi_board_id;
	1081	+ u8 bmi_eboard_id;
950	1082	u8 bmi_chip_id;
	1083	+ bool ext_bid_supported;
951	1084
952	1085	char bdf_ext[ATH10K_SMBIOS_BDF_EXT_STR_LENGTH];
953	1086	} id;
..	..	@@ -1005,20 +1138,22 @@
1005	1138
1006	1139	int last_wmi_vdev_start_status;
1007	1140	struct completion vdev_setup_done;
	1141	+ struct completion vdev_delete_done;
	1142	+ struct completion peer_stats_info_complete;
1008	1143
1009	1144	struct workqueue_struct *workqueue;
1010	1145	/* Auxiliary workqueue */
1011	1146	struct workqueue_struct *workqueue_aux;
1012		-
	1147	+ struct workqueue_struct *workqueue_tx_complete;
1013	1148	/* prevents concurrent FW reconfiguration */
1014	1149	struct mutex conf_mutex;
1015	1150
	1151	+ /* protects coredump data */
	1152	+ struct mutex dump_mutex;
	1153	+
1016	1154	/* protects shared structure data */
1017	1155	spinlock_t data_lock;
1018		- /* protects: ar->txqs, artxq->list */
1019		- spinlock_t txqs_lock;
1020	1156
1021		- struct list_head txqs;
1022	1157	struct list_head arvifs;
1023	1158	struct list_head peers;
1024	1159	struct ath10k_peer *peer_map[ATH10K_MAX_NUM_PEER_IDS];
..	..	@@ -1050,6 +1185,8 @@
1050	1185
1051	1186	struct work_struct register_work;
1052	1187	struct work_struct restart_work;
	1188	+ struct work_struct bundle_tx_work;
	1189	+ struct work_struct tx_complete_work;
1053	1190
1054	1191	/* cycle count is reported twice for each visited channel during scan.
1055	1192	* access protected by data_lock
..	..	@@ -1101,6 +1238,7 @@
1101	1238
1102	1239	struct {
1103	1240	/* protected by data_lock */
	1241	+ u32 rx_crc_err_drop;
1104	1242	u32 fw_crash_counter;
1105	1243	u32 fw_warm_reset_counter;
1106	1244	u32 fw_cold_reset_counter;
..	..	@@ -1129,6 +1267,7 @@
1129	1267
1130	1268	u32 ampdu_reference;
1131	1269
	1270	+ const u8 *wmi_key_cipher;
1132	1271	void *ce_priv;
1133	1272
1134	1273	u32 sta_tid_stats_mask;
..	..	@@ -1137,9 +1276,14 @@
1137	1276	enum ath10k_radar_confirmation_state radar_conf_state;
1138	1277	struct ath10k_radar_found_info last_radar_info;
1139	1278	struct work_struct radar_confirmation_work;
	1279	+ struct ath10k_bus_params bus_param;
	1280	+ struct completion peer_delete_done;
	1281	+
	1282	+ bool coex_support;
	1283	+ int coex_gpio_pin;
1140	1284
1141	1285	/* must be last */
1142		- u8 drv_priv[0] __aligned(sizeof(void *));
	1286	+ u8 drv_priv[] __aligned(sizeof(void *));
1143	1287	};
1144	1288
1145	1289	static inline bool ath10k_peer_stats_enabled(struct ath10k *ar)
..	..	@@ -1168,7 +1312,11 @@
1168	1312	const struct ath10k_fw_components *fw_components);
1169	1313	int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt);
1170	1314	void ath10k_core_stop(struct ath10k *ar);
1171		-int ath10k_core_register(struct ath10k *ar, u32 chip_id);
	1315	+int ath10k_core_register(struct ath10k *ar,
	1316	+ const struct ath10k_bus_params *bus_params);
1172	1317	void ath10k_core_unregister(struct ath10k *ar);
	1318	+int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type);
	1319	+int ath10k_core_check_dt(struct ath10k *ar);
	1320	+void ath10k_core_free_board_files(struct ath10k *ar);
1173	1321
1174	1322	#endif /* _CORE_H_ */