修改内核路径

hc

2024-05-14 bedbef8ad3e75a304af6361af235302bcc61d06b

 kernel/drivers/net/phy/phy-c45.c
..
..
@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
1
2
 /*
2
3
  * Clause 45 PHY support
3
4
  */
..
..
@@ -47,6 +48,16 @@
47
48
 		/* Assume 1000base-T */
48
49
 		ctrl2 |= MDIO_PMA_CTRL2_1000BT;
49
50
 		break;
51
+	case SPEED_2500:
52
+		ctrl1 |= MDIO_CTRL1_SPEED2_5G;
53
+		/* Assume 2.5Gbase-T */
54
+		ctrl2 |= MDIO_PMA_CTRL2_2_5GBT;
55
+		break;
56
+	case SPEED_5000:
57
+		ctrl1 |= MDIO_CTRL1_SPEED5G;
58
+		/* Assume 5Gbase-T */
59
+		ctrl2 |= MDIO_PMA_CTRL2_5GBT;
60
+		break;
50
61
 	case SPEED_10000:
51
62
 		ctrl1 |= MDIO_CTRL1_SPEED10G;
52
63
 		/* Assume 10Gbase-T */
..
..
@@ -60,9 +71,58 @@
60
71
 	if (ret < 0)
61
72
 		return ret;
62
73
 
63
-	return phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2);
74
+	ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2);
75
+	if (ret < 0)
76
+		return ret;
77
+
78
+	return genphy_c45_an_disable_aneg(phydev);
64
79
 }
65
80
 EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced);
81
+
82
+/**
83
+ * genphy_c45_an_config_aneg - configure advertisement registers
84
+ * @phydev: target phy_device struct
85
+ *
86
+ * Configure advertisement registers based on modes set in phydev->advertising
87
+ *
88
+ * Returns negative errno code on failure, 0 if advertisement didn't change,
89
+ * or 1 if advertised modes changed.
90
+ */
91
+int genphy_c45_an_config_aneg(struct phy_device *phydev)
92
+{
93
+	int changed, ret;
94
+	u32 adv;
95
+
96
+	linkmode_and(phydev->advertising, phydev->advertising,
97
+		     phydev->supported);
98
+
99
+	changed = genphy_config_eee_advert(phydev);
100
+
101
+	adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
102
+
103
+	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
104
+				     ADVERTISE_ALL | ADVERTISE_100BASE4 |
105
+				     ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
106
+				     adv);
107
+	if (ret < 0)
108
+		return ret;
109
+	if (ret > 0)
110
+		changed = 1;
111
+
112
+	adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
113
+
114
+	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
115
+				     MDIO_AN_10GBT_CTRL_ADV10G |
116
+				     MDIO_AN_10GBT_CTRL_ADV5G |
117
+				     MDIO_AN_10GBT_CTRL_ADV2_5G, adv);
118
+	if (ret < 0)
119
+		return ret;
120
+	if (ret > 0)
121
+		changed = 1;
122
+
123
+	return changed;
124
+}
125
+EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg);
66
126
 
67
127
 /**
68
128
  * genphy_c45_an_disable_aneg - disable auto-negotiation
..
..
@@ -75,15 +135,9 @@
75
135
  */
76
136
 int genphy_c45_an_disable_aneg(struct phy_device *phydev)
77
137
 {
78
-	int val;
79
138
 
80
-	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
81
-	if (val < 0)
82
-		return val;
83
-
84
-	val &= ~(MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
85
-
86
-	return phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, val);
139
+	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
140
+				  MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
87
141
 }
88
142
 EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
89
143
 
..
..
@@ -97,17 +151,40 @@
97
151
  */
98
152
 int genphy_c45_restart_aneg(struct phy_device *phydev)
99
153
 {
100
-	int val;
101
-
102
-	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
103
-	if (val < 0)
104
-		return val;
105
-
106
-	val |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART;
107
-
108
-	return phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, val);
154
+	return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
155
+				MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
109
156
 }
110
157
 EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);
158
+
159
+/**
160
+ * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation
161
+ * @phydev: target phy_device struct
162
+ * @restart: whether aneg restart is requested
163
+ *
164
+ * This assumes that the auto-negotiation MMD is present.
165
+ *
166
+ * Check, and restart auto-negotiation if needed.
167
+ */
168
+int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart)
169
+{
170
+	int ret;
171
+
172
+	if (!restart) {
173
+		/* Configure and restart aneg if it wasn't set before */
174
+		ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
175
+		if (ret < 0)
176
+			return ret;
177
+
178
+		if (!(ret & MDIO_AN_CTRL1_ENABLE))
179
+			restart = true;
180
+	}
181
+
182
+	if (restart)
183
+		return genphy_c45_restart_aneg(phydev);
184
+
185
+	return 0;
186
+}
187
+EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg);
111
188
 
112
189
 /**
113
190
  * genphy_c45_aneg_done - return auto-negotiation complete status
..
..
@@ -131,29 +208,46 @@
131
208
 /**
132
209
  * genphy_c45_read_link - read the overall link status from the MMDs
133
210
  * @phydev: target phy_device struct
134
- * @mmd_mask: MMDs to read status from
135
211
  *
136
212
  * Read the link status from the specified MMDs, and if they all indicate
137
- * that the link is up, return positive.  If an error is encountered,
213
+ * that the link is up, set phydev->link to 1.  If an error is encountered,
138
214
  * a negative errno will be returned, otherwise zero.
139
215
  */
140
-int genphy_c45_read_link(struct phy_device *phydev, u32 mmd_mask)
216
+int genphy_c45_read_link(struct phy_device *phydev)
141
217
 {
218
+	u32 mmd_mask = MDIO_DEVS_PMAPMD;
142
219
 	int val, devad;
143
220
 	bool link = true;
144
221
 
145
-	while (mmd_mask) {
222
+	if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) {
223
+		val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
224
+		if (val < 0)
225
+			return val;
226
+
227
+		/* Autoneg is being started, therefore disregard current
228
+		 * link status and report link as down.
229
+		 */
230
+		if (val & MDIO_AN_CTRL1_RESTART) {
231
+			phydev->link = 0;
232
+			return 0;
233
+		}
234
+	}
235
+
236
+	while (mmd_mask && link) {
146
237
 		devad = __ffs(mmd_mask);
147
238
 		mmd_mask &= ~BIT(devad);
148
239
 
149
240
 		/* The link state is latched low so that momentary link
150
241
 		 * drops can be detected. Do not double-read the status
151
-		 * in polling mode to detect such short link drops.
242
+		 * in polling mode to detect such short link drops except
243
+		 * the link was already down.
152
244
 		 */
153
-		if (!phy_polling_mode(phydev)) {
245
+		if (!phy_polling_mode(phydev) || !phydev->link) {
154
246
 			val = phy_read_mmd(phydev, devad, MDIO_STAT1);
155
247
 			if (val < 0)
156
248
 				return val;
249
+			else if (val & MDIO_STAT1_LSTATUS)
250
+				continue;
157
251
 		}
158
252
 
159
253
 		val = phy_read_mmd(phydev, devad, MDIO_STAT1);
..
..
@@ -164,7 +258,9 @@
164
258
 			link = false;
165
259
 	}
166
260
 
167
-	return link;
261
+	phydev->link = link;
262
+
263
+	return 0;
168
264
 }
169
265
 EXPORT_SYMBOL_GPL(genphy_c45_read_link);
170
266
 
..
..
@@ -182,12 +278,30 @@
182
278
 {
183
279
 	int val;
184
280
 
281
+	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
282
+	if (val < 0)
283
+		return val;
284
+
285
+	if (!(val & MDIO_AN_STAT1_COMPLETE)) {
286
+		linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
287
+				   phydev->lp_advertising);
288
+		mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
289
+		mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0);
290
+		phydev->pause = 0;
291
+		phydev->asym_pause = 0;
292
+
293
+		return 0;
294
+	}
295
+
296
+	linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising,
297
+			 val & MDIO_AN_STAT1_LPABLE);
298
+
185
299
 	/* Read the link partner's base page advertisement */
186
300
 	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
187
301
 	if (val < 0)
188
302
 		return val;
189
303
 
190
-	phydev->lp_advertising = mii_lpa_to_ethtool_lpa_t(val);
304
+	mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val);
191
305
 	phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0;
192
306
 	phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0;
193
307
 
..
..
@@ -196,8 +310,7 @@
196
310
 	if (val < 0)
197
311
 		return val;
198
312
 
199
-	if (val & MDIO_AN_10GBT_STAT_LP10G)
200
-		phydev->lp_advertising |= ADVERTISED_10000baseT_Full;
313
+	mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val);
201
314
 
202
315
 	return 0;
203
316
 }
..
..
@@ -210,6 +323,8 @@
210
323
 int genphy_c45_read_pma(struct phy_device *phydev)
211
324
 {
212
325
 	int val;
326
+
327
+	linkmode_zero(phydev->lp_advertising);
213
328
 
214
329
 	val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
215
330
 	if (val < 0)
..
..
@@ -224,6 +339,12 @@
224
339
 		break;
225
340
 	case MDIO_PMA_CTRL1_SPEED1000:
226
341
 		phydev->speed = SPEED_1000;
342
+		break;
343
+	case MDIO_CTRL1_SPEED2_5G:
344
+		phydev->speed = SPEED_2500;
345
+		break;
346
+	case MDIO_CTRL1_SPEED5G:
347
+		phydev->speed = SPEED_5000;
227
348
 		break;
228
349
 	case MDIO_CTRL1_SPEED10G:
229
350
 		phydev->speed = SPEED_10000;
..
..
@@ -272,6 +393,165 @@
272
393
 }
273
394
 EXPORT_SYMBOL_GPL(genphy_c45_read_mdix);
274
395
 
396
+/**
397
+ * genphy_c45_pma_read_abilities - read supported link modes from PMA
398
+ * @phydev: target phy_device struct
399
+ *
400
+ * Read the supported link modes from the PMA Status 2 (1.8) register. If bit
401
+ * 1.8.9 is set, the list of supported modes is build using the values in the
402
+ * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related
403
+ * modes. If bit 1.11.14 is set, then the list is also extended with the modes
404
+ * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and
405
+ * 5GBASET are supported.
406
+ */
407
+int genphy_c45_pma_read_abilities(struct phy_device *phydev)
408
+{
409
+	int val;
410
+
411
+	linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
412
+	if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) {
413
+		val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
414
+		if (val < 0)
415
+			return val;
416
+
417
+		if (val & MDIO_AN_STAT1_ABLE)
418
+			linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
419
+					 phydev->supported);
420
+	}
421
+
422
+	val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
423
+	if (val < 0)
424
+		return val;
425
+
426
+	linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
427
+			 phydev->supported,
428
+			 val & MDIO_PMA_STAT2_10GBSR);
429
+
430
+	linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
431
+			 phydev->supported,
432
+			 val & MDIO_PMA_STAT2_10GBLR);
433
+
434
+	linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
435
+			 phydev->supported,
436
+			 val & MDIO_PMA_STAT2_10GBER);
437
+
438
+	if (val & MDIO_PMA_STAT2_EXTABLE) {
439
+		val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
440
+		if (val < 0)
441
+			return val;
442
+
443
+		linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
444
+				 phydev->supported,
445
+				 val & MDIO_PMA_EXTABLE_10GBLRM);
446
+		linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
447
+				 phydev->supported,
448
+				 val & MDIO_PMA_EXTABLE_10GBT);
449
+		linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
450
+				 phydev->supported,
451
+				 val & MDIO_PMA_EXTABLE_10GBKX4);
452
+		linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
453
+				 phydev->supported,
454
+				 val & MDIO_PMA_EXTABLE_10GBKR);
455
+		linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
456
+				 phydev->supported,
457
+				 val & MDIO_PMA_EXTABLE_1000BT);
458
+		linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
459
+				 phydev->supported,
460
+				 val & MDIO_PMA_EXTABLE_1000BKX);
461
+
462
+		linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
463
+				 phydev->supported,
464
+				 val & MDIO_PMA_EXTABLE_100BTX);
465
+		linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
466
+				 phydev->supported,
467
+				 val & MDIO_PMA_EXTABLE_100BTX);
468
+
469
+		linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
470
+				 phydev->supported,
471
+				 val & MDIO_PMA_EXTABLE_10BT);
472
+		linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
473
+				 phydev->supported,
474
+				 val & MDIO_PMA_EXTABLE_10BT);
475
+
476
+		if (val & MDIO_PMA_EXTABLE_NBT) {
477
+			val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
478
+					   MDIO_PMA_NG_EXTABLE);
479
+			if (val < 0)
480
+				return val;
481
+
482
+			linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
483
+					 phydev->supported,
484
+					 val & MDIO_PMA_NG_EXTABLE_2_5GBT);
485
+
486
+			linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
487
+					 phydev->supported,
488
+					 val & MDIO_PMA_NG_EXTABLE_5GBT);
489
+		}
490
+	}
491
+
492
+	return 0;
493
+}
494
+EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities);
495
+
496
+/**
497
+ * genphy_c45_read_status - read PHY status
498
+ * @phydev: target phy_device struct
499
+ *
500
+ * Reads status from PHY and sets phy_device members accordingly.
501
+ */
502
+int genphy_c45_read_status(struct phy_device *phydev)
503
+{
504
+	int ret;
505
+
506
+	ret = genphy_c45_read_link(phydev);
507
+	if (ret)
508
+		return ret;
509
+
510
+	phydev->speed = SPEED_UNKNOWN;
511
+	phydev->duplex = DUPLEX_UNKNOWN;
512
+	phydev->pause = 0;
513
+	phydev->asym_pause = 0;
514
+
515
+	if (phydev->autoneg == AUTONEG_ENABLE) {
516
+		ret = genphy_c45_read_lpa(phydev);
517
+		if (ret)
518
+			return ret;
519
+
520
+		phy_resolve_aneg_linkmode(phydev);
521
+	} else {
522
+		ret = genphy_c45_read_pma(phydev);
523
+	}
524
+
525
+	return ret;
526
+}
527
+EXPORT_SYMBOL_GPL(genphy_c45_read_status);
528
+
529
+/**
530
+ * genphy_c45_config_aneg - restart auto-negotiation or forced setup
531
+ * @phydev: target phy_device struct
532
+ *
533
+ * Description: If auto-negotiation is enabled, we configure the
534
+ *   advertising, and then restart auto-negotiation.  If it is not
535
+ *   enabled, then we force a configuration.
536
+ */
537
+int genphy_c45_config_aneg(struct phy_device *phydev)
538
+{
539
+	bool changed = false;
540
+	int ret;
541
+
542
+	if (phydev->autoneg == AUTONEG_DISABLE)
543
+		return genphy_c45_pma_setup_forced(phydev);
544
+
545
+	ret = genphy_c45_an_config_aneg(phydev);
546
+	if (ret < 0)
547
+		return ret;
548
+	if (ret > 0)
549
+		changed = true;
550
+
551
+	return genphy_c45_check_and_restart_aneg(phydev, changed);
552
+}
553
+EXPORT_SYMBOL_GPL(genphy_c45_config_aneg);
554
+
275
555
 /* The gen10g_* functions are the old Clause 45 stub */
276
556
 
277
557
 int gen10g_config_aneg(struct phy_device *phydev)
..
..
@@ -280,64 +560,9 @@
280
560
 }
281
561
 EXPORT_SYMBOL_GPL(gen10g_config_aneg);
282
562
 
283
-int gen10g_read_status(struct phy_device *phydev)
284
-{
285
-	u32 mmd_mask = phydev->c45_ids.devices_in_package;
286
-	int ret;
287
-
288
-	/* For now just lie and say it's 10G all the time */
289
-	phydev->speed = SPEED_10000;
290
-	phydev->duplex = DUPLEX_FULL;
291
-
292
-	/* Avoid reading the vendor MMDs */
293
-	mmd_mask &= ~(BIT(MDIO_MMD_VEND1) | BIT(MDIO_MMD_VEND2));
294
-
295
-	ret = genphy_c45_read_link(phydev, mmd_mask);
296
-
297
-	phydev->link = ret > 0 ? 1 : 0;
298
-
299
-	return 0;
300
-}
301
-EXPORT_SYMBOL_GPL(gen10g_read_status);
302
-
303
-int gen10g_no_soft_reset(struct phy_device *phydev)
304
-{
305
-	/* Do nothing for now */
306
-	return 0;
307
-}
308
-EXPORT_SYMBOL_GPL(gen10g_no_soft_reset);
309
-
310
-int gen10g_config_init(struct phy_device *phydev)
311
-{
312
-	/* Temporarily just say we support everything */
313
-	phydev->supported = SUPPORTED_10000baseT_Full;
314
-	phydev->advertising = SUPPORTED_10000baseT_Full;
315
-
316
-	return 0;
317
-}
318
-EXPORT_SYMBOL_GPL(gen10g_config_init);
319
-
320
-int gen10g_suspend(struct phy_device *phydev)
321
-{
322
-	return 0;
323
-}
324
-EXPORT_SYMBOL_GPL(gen10g_suspend);
325
-
326
-int gen10g_resume(struct phy_device *phydev)
327
-{
328
-	return 0;
329
-}
330
-EXPORT_SYMBOL_GPL(gen10g_resume);
331
-
332
-struct phy_driver genphy_10g_driver = {
563
+struct phy_driver genphy_c45_driver = {
333
564
 	.phy_id         = 0xffffffff,
334
565
 	.phy_id_mask    = 0xffffffff,
335
-	.name           = "Generic 10G PHY",
336
-	.soft_reset	= gen10g_no_soft_reset,
337
-	.config_init    = gen10g_config_init,
338
-	.features       = 0,
339
-	.config_aneg    = gen10g_config_aneg,
340
-	.read_status    = gen10g_read_status,
341
-	.suspend        = gen10g_suspend,
342
-	.resume         = gen10g_resume,
566
+	.name           = "Generic Clause 45 PHY",
567
+	.read_status    = genphy_c45_read_status,
343
568
 };