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| 1 | +// SPDX-License-Identifier: GPL-2.0+ |
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1 | 2 | /* |
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2 | 3 | * Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> |
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3 | 4 | * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de> |
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4 | | - * |
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5 | | - * This program is free software; you can redistribute it and/or modify |
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6 | | - * it under the terms of the GNU General Public License as published by |
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7 | | - * the Free Software Foundation; either version 2 of the License, or |
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8 | | - * (at your option) any later version. |
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9 | | - * |
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10 | | - * This program is distributed in the hope that it will be useful, |
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11 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | | - * GNU General Public License for more details. |
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14 | 5 | */ |
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15 | 6 | |
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16 | 7 | #include <linux/mdio.h> |
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.. | .. |
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20 | 11 | |
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21 | 12 | #define XWAY_MDIO_IMASK 0x19 /* interrupt mask */ |
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22 | 13 | #define XWAY_MDIO_ISTAT 0x1A /* interrupt status */ |
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| 14 | +#define XWAY_MDIO_LED 0x1B /* led control */ |
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| 15 | + |
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| 16 | +/* bit 15:12 are reserved */ |
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| 17 | +#define XWAY_MDIO_LED_LED3_EN BIT(11) /* Enable the integrated function of LED3 */ |
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| 18 | +#define XWAY_MDIO_LED_LED2_EN BIT(10) /* Enable the integrated function of LED2 */ |
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| 19 | +#define XWAY_MDIO_LED_LED1_EN BIT(9) /* Enable the integrated function of LED1 */ |
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| 20 | +#define XWAY_MDIO_LED_LED0_EN BIT(8) /* Enable the integrated function of LED0 */ |
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| 21 | +/* bit 7:4 are reserved */ |
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| 22 | +#define XWAY_MDIO_LED_LED3_DA BIT(3) /* Direct Access to LED3 */ |
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| 23 | +#define XWAY_MDIO_LED_LED2_DA BIT(2) /* Direct Access to LED2 */ |
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| 24 | +#define XWAY_MDIO_LED_LED1_DA BIT(1) /* Direct Access to LED1 */ |
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| 25 | +#define XWAY_MDIO_LED_LED0_DA BIT(0) /* Direct Access to LED0 */ |
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23 | 26 | |
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24 | 27 | #define XWAY_MDIO_INIT_WOL BIT(15) /* Wake-On-LAN */ |
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25 | 28 | #define XWAY_MDIO_INIT_MSRE BIT(14) |
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.. | .. |
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168 | 171 | /* Clear all pending interrupts */ |
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169 | 172 | phy_read(phydev, XWAY_MDIO_ISTAT); |
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170 | 173 | |
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| 174 | + /* Ensure that integrated led function is enabled for all leds */ |
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| 175 | + err = phy_write(phydev, XWAY_MDIO_LED, |
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| 176 | + XWAY_MDIO_LED_LED0_EN | |
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| 177 | + XWAY_MDIO_LED_LED1_EN | |
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| 178 | + XWAY_MDIO_LED_LED2_EN | |
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| 179 | + XWAY_MDIO_LED_LED3_EN); |
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| 180 | + if (err) |
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| 181 | + return err; |
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| 182 | + |
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171 | 183 | phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, |
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172 | 184 | XWAY_MMD_LEDCH_NACS_NONE | |
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173 | 185 | XWAY_MMD_LEDCH_SBF_F02HZ | |
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.. | .. |
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241 | 253 | .phy_id = PHY_ID_PHY11G_1_3, |
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242 | 254 | .phy_id_mask = 0xffffffff, |
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243 | 255 | .name = "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.3", |
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244 | | - .features = PHY_GBIT_FEATURES, |
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245 | | - .flags = PHY_HAS_INTERRUPT, |
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| 256 | + /* PHY_GBIT_FEATURES */ |
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246 | 257 | .config_init = xway_gphy_config_init, |
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247 | 258 | .config_aneg = xway_gphy14_config_aneg, |
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248 | 259 | .ack_interrupt = xway_gphy_ack_interrupt, |
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.. | .. |
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254 | 265 | .phy_id = PHY_ID_PHY22F_1_3, |
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255 | 266 | .phy_id_mask = 0xffffffff, |
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256 | 267 | .name = "Intel XWAY PHY22F (PEF 7061) v1.3", |
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257 | | - .features = PHY_BASIC_FEATURES, |
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258 | | - .flags = PHY_HAS_INTERRUPT, |
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| 268 | + /* PHY_BASIC_FEATURES */ |
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259 | 269 | .config_init = xway_gphy_config_init, |
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260 | 270 | .config_aneg = xway_gphy14_config_aneg, |
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261 | 271 | .ack_interrupt = xway_gphy_ack_interrupt, |
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.. | .. |
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267 | 277 | .phy_id = PHY_ID_PHY11G_1_4, |
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268 | 278 | .phy_id_mask = 0xffffffff, |
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269 | 279 | .name = "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.4", |
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270 | | - .features = PHY_GBIT_FEATURES, |
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271 | | - .flags = PHY_HAS_INTERRUPT, |
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| 280 | + /* PHY_GBIT_FEATURES */ |
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272 | 281 | .config_init = xway_gphy_config_init, |
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273 | 282 | .config_aneg = xway_gphy14_config_aneg, |
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274 | 283 | .ack_interrupt = xway_gphy_ack_interrupt, |
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.. | .. |
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280 | 289 | .phy_id = PHY_ID_PHY22F_1_4, |
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281 | 290 | .phy_id_mask = 0xffffffff, |
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282 | 291 | .name = "Intel XWAY PHY22F (PEF 7061) v1.4", |
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283 | | - .features = PHY_BASIC_FEATURES, |
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284 | | - .flags = PHY_HAS_INTERRUPT, |
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| 292 | + /* PHY_BASIC_FEATURES */ |
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285 | 293 | .config_init = xway_gphy_config_init, |
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286 | 294 | .config_aneg = xway_gphy14_config_aneg, |
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287 | 295 | .ack_interrupt = xway_gphy_ack_interrupt, |
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.. | .. |
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293 | 301 | .phy_id = PHY_ID_PHY11G_1_5, |
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294 | 302 | .phy_id_mask = 0xffffffff, |
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295 | 303 | .name = "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.5 / v1.6", |
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296 | | - .features = PHY_GBIT_FEATURES, |
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297 | | - .flags = PHY_HAS_INTERRUPT, |
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| 304 | + /* PHY_GBIT_FEATURES */ |
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298 | 305 | .config_init = xway_gphy_config_init, |
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299 | 306 | .ack_interrupt = xway_gphy_ack_interrupt, |
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300 | 307 | .did_interrupt = xway_gphy_did_interrupt, |
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.. | .. |
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305 | 312 | .phy_id = PHY_ID_PHY22F_1_5, |
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306 | 313 | .phy_id_mask = 0xffffffff, |
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307 | 314 | .name = "Intel XWAY PHY22F (PEF 7061) v1.5 / v1.6", |
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308 | | - .features = PHY_BASIC_FEATURES, |
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309 | | - .flags = PHY_HAS_INTERRUPT, |
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| 315 | + /* PHY_BASIC_FEATURES */ |
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310 | 316 | .config_init = xway_gphy_config_init, |
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311 | 317 | .ack_interrupt = xway_gphy_ack_interrupt, |
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312 | 318 | .did_interrupt = xway_gphy_did_interrupt, |
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.. | .. |
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317 | 323 | .phy_id = PHY_ID_PHY11G_VR9_1_1, |
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318 | 324 | .phy_id_mask = 0xffffffff, |
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319 | 325 | .name = "Intel XWAY PHY11G (xRX v1.1 integrated)", |
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320 | | - .features = PHY_GBIT_FEATURES, |
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321 | | - .flags = PHY_HAS_INTERRUPT, |
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| 326 | + /* PHY_GBIT_FEATURES */ |
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322 | 327 | .config_init = xway_gphy_config_init, |
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323 | 328 | .ack_interrupt = xway_gphy_ack_interrupt, |
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324 | 329 | .did_interrupt = xway_gphy_did_interrupt, |
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.. | .. |
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329 | 334 | .phy_id = PHY_ID_PHY22F_VR9_1_1, |
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330 | 335 | .phy_id_mask = 0xffffffff, |
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331 | 336 | .name = "Intel XWAY PHY22F (xRX v1.1 integrated)", |
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332 | | - .features = PHY_BASIC_FEATURES, |
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333 | | - .flags = PHY_HAS_INTERRUPT, |
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| 337 | + /* PHY_BASIC_FEATURES */ |
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334 | 338 | .config_init = xway_gphy_config_init, |
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335 | 339 | .ack_interrupt = xway_gphy_ack_interrupt, |
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336 | 340 | .did_interrupt = xway_gphy_did_interrupt, |
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.. | .. |
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341 | 345 | .phy_id = PHY_ID_PHY11G_VR9_1_2, |
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342 | 346 | .phy_id_mask = 0xffffffff, |
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343 | 347 | .name = "Intel XWAY PHY11G (xRX v1.2 integrated)", |
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344 | | - .features = PHY_GBIT_FEATURES, |
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345 | | - .flags = PHY_HAS_INTERRUPT, |
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| 348 | + /* PHY_GBIT_FEATURES */ |
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346 | 349 | .config_init = xway_gphy_config_init, |
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347 | 350 | .ack_interrupt = xway_gphy_ack_interrupt, |
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348 | 351 | .did_interrupt = xway_gphy_did_interrupt, |
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.. | .. |
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353 | 356 | .phy_id = PHY_ID_PHY22F_VR9_1_2, |
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354 | 357 | .phy_id_mask = 0xffffffff, |
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355 | 358 | .name = "Intel XWAY PHY22F (xRX v1.2 integrated)", |
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356 | | - .features = PHY_BASIC_FEATURES, |
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357 | | - .flags = PHY_HAS_INTERRUPT, |
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| 359 | + /* PHY_BASIC_FEATURES */ |
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358 | 360 | .config_init = xway_gphy_config_init, |
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359 | 361 | .ack_interrupt = xway_gphy_ack_interrupt, |
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360 | 362 | .did_interrupt = xway_gphy_did_interrupt, |
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