hc
2024-05-14 bedbef8ad3e75a304af6361af235302bcc61d06b
kernel/drivers/net/phy/dp83tc811.c
....@@ -139,19 +139,19 @@
139139 value &= ~DP83811_WOL_SECURE_ON;
140140 }
141141
142
- value |= (DP83811_WOL_EN | DP83811_WOL_INDICATION_SEL |
143
- DP83811_WOL_CLR_INDICATION);
144
- phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
145
- value);
142
+ /* Clear any pending WoL interrupt */
143
+ phy_read(phydev, MII_DP83811_INT_STAT1);
144
+
145
+ value |= DP83811_WOL_EN | DP83811_WOL_INDICATION_SEL |
146
+ DP83811_WOL_CLR_INDICATION;
147
+
148
+ return phy_write_mmd(phydev, DP83811_DEVADDR,
149
+ MII_DP83811_WOL_CFG, value);
146150 } else {
147
- value = phy_read_mmd(phydev, DP83811_DEVADDR,
148
- MII_DP83811_WOL_CFG);
149
- value &= ~DP83811_WOL_EN;
150
- phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
151
- value);
151
+ return phy_clear_bits_mmd(phydev, DP83811_DEVADDR,
152
+ MII_DP83811_WOL_CFG, DP83811_WOL_EN);
152153 }
153154
154
- return 0;
155155 }
156156
157157 static void dp83811_get_wol(struct phy_device *phydev,
....@@ -280,10 +280,6 @@
280280 {
281281 int value, err;
282282
283
- err = genphy_config_init(phydev);
284
- if (err < 0)
285
- return err;
286
-
287283 value = phy_read(phydev, MII_DP83811_SGMII_CTRL);
288284 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
289285 err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
....@@ -299,8 +295,8 @@
299295
300296 value = DP83811_WOL_MAGIC_EN | DP83811_WOL_SECURE_ON | DP83811_WOL_EN;
301297
302
- return phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
303
- value);
298
+ return phy_clear_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
299
+ value);
304300 }
305301
306302 static int dp83811_phy_reset(struct phy_device *phydev)
....@@ -328,14 +324,10 @@
328324
329325 static int dp83811_resume(struct phy_device *phydev)
330326 {
331
- int value;
332
-
333327 genphy_resume(phydev);
334328
335
- value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);
336
-
337
- phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG, value |
338
- DP83811_WOL_CLR_INDICATION);
329
+ phy_set_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
330
+ DP83811_WOL_CLR_INDICATION);
339331
340332 return 0;
341333 }
....@@ -345,8 +337,7 @@
345337 .phy_id = DP83TC811_PHY_ID,
346338 .phy_id_mask = 0xfffffff0,
347339 .name = "TI DP83TC811",
348
- .features = PHY_BASIC_FEATURES,
349
- .flags = PHY_HAS_INTERRUPT,
340
+ /* PHY_BASIC_FEATURES */
350341 .config_init = dp83811_config_init,
351342 .config_aneg = dp83811_config_aneg,
352343 .soft_reset = dp83811_phy_reset,