修改内核路径

hc

2024-05-14 bedbef8ad3e75a304af6361af235302bcc61d06b

 kernel/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
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@@ -2009,6 +2009,11 @@
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 		goto cleanup_clk;
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 	}
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+	/* Reset core now that clocks are enabled, prior to accessing MDIO */
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+	ret = __axienet_device_reset(lp);
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+	if (ret)
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+		goto cleanup_clk;
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+
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 	/* Autodetect the need for 64-bit DMA pointers.
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 	 * When the IP is configured for a bus width bigger than 32 bits,
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 	 * writing the MSB registers is mandatory, even if they are all 0.
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@@ -2054,11 +2059,6 @@
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 	lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
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 	lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
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-
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-	/* Reset core now that clocks are enabled, prior to accessing MDIO */
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-	ret = __axienet_device_reset(lp);
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-	if (ret)
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-		goto cleanup_clk;
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 	ret = axienet_mdio_setup(lp);
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 	if (ret)