.. | .. |
---|
865 | 865 | struct imx327 *imx327 = to_imx327(sd); |
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866 | 866 | const struct imx327_mode *mode = imx327->cur_mode; |
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867 | 867 | |
---|
868 | | - mutex_lock(&imx327->mutex); |
---|
869 | 868 | fi->interval = mode->max_fps; |
---|
870 | | - mutex_unlock(&imx327->mutex); |
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871 | 869 | |
---|
872 | 870 | return 0; |
---|
873 | 871 | } |
---|
874 | 872 | |
---|
875 | | -static int imx327_g_mbus_config(struct v4l2_subdev *sd, |
---|
| 873 | +static int imx327_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id, |
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876 | 874 | struct v4l2_mbus_config *config) |
---|
877 | 875 | { |
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878 | 876 | struct imx327 *imx327 = to_imx327(sd); |
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.. | .. |
---|
881 | 879 | val = 1 << (IMX327_4LANES - 1) | |
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882 | 880 | V4L2_MBUS_CSI2_CHANNEL_0 | |
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883 | 881 | V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; |
---|
884 | | - if (imx327->bus_cfg.bus_type == 3) |
---|
885 | | - config->type = V4L2_MBUS_CCP2; |
---|
886 | | - else |
---|
887 | | - config->type = V4L2_MBUS_CSI2; |
---|
| 882 | + config->type = imx327->bus_cfg.bus_type; |
---|
888 | 883 | config->flags = val; |
---|
889 | 884 | |
---|
890 | 885 | return 0; |
---|
.. | .. |
---|
1145 | 1140 | break; |
---|
1146 | 1141 | case RKMODULE_GET_LVDS_CFG: |
---|
1147 | 1142 | lvds_cfg = (struct rkmodule_lvds_cfg *)arg; |
---|
1148 | | - if (imx327->bus_cfg.bus_type == 3) |
---|
| 1143 | + if (imx327->bus_cfg.bus_type == V4L2_MBUS_CCP2) |
---|
1149 | 1144 | memcpy(lvds_cfg, &imx327->cur_mode->lvds_cfg, |
---|
1150 | 1145 | sizeof(struct rkmodule_lvds_cfg)); |
---|
1151 | 1146 | else |
---|
.. | .. |
---|
1558 | 1553 | if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) { |
---|
1559 | 1554 | sel->r.left = CROP_START(imx327->cur_mode->width, DST_WIDTH); |
---|
1560 | 1555 | sel->r.width = DST_WIDTH; |
---|
1561 | | - if (imx327->bus_cfg.bus_type == 3) { |
---|
| 1556 | + if (imx327->bus_cfg.bus_type == V4L2_MBUS_CCP2) { |
---|
1562 | 1557 | if (imx327->cur_mode->hdr_mode == NO_HDR) |
---|
1563 | 1558 | sel->r.top = 21; |
---|
1564 | 1559 | else |
---|
.. | .. |
---|
1594 | 1589 | static const struct v4l2_subdev_video_ops imx327_video_ops = { |
---|
1595 | 1590 | .s_stream = imx327_s_stream, |
---|
1596 | 1591 | .g_frame_interval = imx327_g_frame_interval, |
---|
1597 | | - .g_mbus_config = imx327_g_mbus_config, |
---|
1598 | 1592 | }; |
---|
1599 | 1593 | |
---|
1600 | 1594 | static const struct v4l2_subdev_pad_ops imx327_pad_ops = { |
---|
.. | .. |
---|
1604 | 1598 | .get_fmt = imx327_get_fmt, |
---|
1605 | 1599 | .set_fmt = imx327_set_fmt, |
---|
1606 | 1600 | .get_selection = imx327_get_selection, |
---|
| 1601 | + .get_mbus_config = imx327_g_mbus_config, |
---|
1607 | 1602 | }; |
---|
1608 | 1603 | |
---|
1609 | 1604 | static const struct v4l2_subdev_ops imx327_subdev_ops = { |
---|
.. | .. |
---|
1640 | 1635 | |
---|
1641 | 1636 | switch (ctrl->id) { |
---|
1642 | 1637 | case V4L2_CID_EXPOSURE: |
---|
1643 | | - shs1 = imx327->cur_vts - ctrl->val - 1; |
---|
1644 | | - ret = imx327_write_reg(imx327->client, |
---|
1645 | | - IMX327_REG_SHS1_H, |
---|
1646 | | - IMX327_REG_VALUE_08BIT, |
---|
1647 | | - IMX327_FETCH_HIGH_BYTE_EXP(shs1)); |
---|
1648 | | - ret |= imx327_write_reg(imx327->client, |
---|
1649 | | - IMX327_REG_SHS1_M, |
---|
1650 | | - IMX327_REG_VALUE_08BIT, |
---|
1651 | | - IMX327_FETCH_MID_BYTE_EXP(shs1)); |
---|
1652 | | - ret |= imx327_write_reg(imx327->client, |
---|
1653 | | - IMX327_REG_SHS1_L, |
---|
1654 | | - IMX327_REG_VALUE_08BIT, |
---|
1655 | | - IMX327_FETCH_LOW_BYTE_EXP(shs1)); |
---|
1656 | | - dev_dbg(&client->dev, "set exposure 0x%x, cur_vts 0x%x,shs1 0x%x\n", |
---|
1657 | | - ctrl->val, imx327->cur_vts, shs1); |
---|
| 1638 | + if (imx327->cur_mode->hdr_mode == NO_HDR) { |
---|
| 1639 | + shs1 = imx327->cur_vts - ctrl->val - 1; |
---|
| 1640 | + ret = imx327_write_reg(imx327->client, |
---|
| 1641 | + IMX327_REG_SHS1_H, |
---|
| 1642 | + IMX327_REG_VALUE_08BIT, |
---|
| 1643 | + IMX327_FETCH_HIGH_BYTE_EXP(shs1)); |
---|
| 1644 | + ret |= imx327_write_reg(imx327->client, |
---|
| 1645 | + IMX327_REG_SHS1_M, |
---|
| 1646 | + IMX327_REG_VALUE_08BIT, |
---|
| 1647 | + IMX327_FETCH_MID_BYTE_EXP(shs1)); |
---|
| 1648 | + ret |= imx327_write_reg(imx327->client, |
---|
| 1649 | + IMX327_REG_SHS1_L, |
---|
| 1650 | + IMX327_REG_VALUE_08BIT, |
---|
| 1651 | + IMX327_FETCH_LOW_BYTE_EXP(shs1)); |
---|
| 1652 | + dev_dbg(&client->dev, "set exposure 0x%x, cur_vts 0x%x,shs1 0x%x\n", |
---|
| 1653 | + ctrl->val, imx327->cur_vts, shs1); |
---|
| 1654 | + } |
---|
1658 | 1655 | break; |
---|
1659 | 1656 | case V4L2_CID_ANALOGUE_GAIN: |
---|
1660 | | - ret = imx327_write_reg(imx327->client, |
---|
1661 | | - IMX327_REG_LF_GAIN, |
---|
1662 | | - IMX327_REG_VALUE_08BIT, |
---|
1663 | | - ctrl->val); |
---|
1664 | | - dev_dbg(&client->dev, "set analog gain 0x%x\n", |
---|
1665 | | - ctrl->val); |
---|
| 1657 | + if (imx327->cur_mode->hdr_mode == NO_HDR) { |
---|
| 1658 | + ret = imx327_write_reg(imx327->client, |
---|
| 1659 | + IMX327_REG_LF_GAIN, |
---|
| 1660 | + IMX327_REG_VALUE_08BIT, |
---|
| 1661 | + ctrl->val); |
---|
| 1662 | + dev_dbg(&client->dev, "set analog gain 0x%x\n", |
---|
| 1663 | + ctrl->val); |
---|
| 1664 | + } |
---|
1666 | 1665 | break; |
---|
1667 | 1666 | case V4L2_CID_VBLANK: |
---|
1668 | 1667 | vts = ctrl->val + imx327->cur_mode->height; |
---|
.. | .. |
---|
1893 | 1892 | |
---|
1894 | 1893 | ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), |
---|
1895 | 1894 | &imx327->bus_cfg); |
---|
1896 | | - if (imx327->bus_cfg.bus_type == 3) { |
---|
| 1895 | + if (imx327->bus_cfg.bus_type == V4L2_MBUS_CCP2) { |
---|
1897 | 1896 | imx327->support_modes = lvds_supported_modes; |
---|
1898 | 1897 | imx327->support_modes_num = ARRAY_SIZE(lvds_supported_modes); |
---|
1899 | 1898 | } else { |
---|