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2024-05-14 bedbef8ad3e75a304af6361af235302bcc61d06b 
 kernel/drivers/infiniband/hw/mlx5/cmd.c
....@@ -1,46 +1,19 @@
1
+// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
12 /*
2
- * Copyright (c) 2017, Mellanox Technologies. All rights reserved.
3
- *
4
- * This software is available to you under a choice of one of two
5
- * licenses.  You may choose to be licensed under the terms of the GNU
6
- * General Public License (GPL) Version 2, available from the file
7
- * COPYING in the main directory of this source tree, or the
8
- * OpenIB.org BSD license below:
9
- *
10
- *     Redistribution and use in source and binary forms, with or
11
- *     without modification, are permitted provided that the following
12
- *     conditions are met:
13
- *
14
- *      - Redistributions of source code must retain the above
15
- *        copyright notice, this list of conditions and the following
16
- *        disclaimer.
17
- *
18
- *      - Redistributions in binary form must reproduce the above
19
- *        copyright notice, this list of conditions and the following
20
- *        disclaimer in the documentation and/or other materials
21
- *        provided with the distribution.
22
- *
23
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30
- * SOFTWARE.
3
+ * Copyright (c) 2017-2020, Mellanox Technologies inc. All rights reserved.
314  */
325 
336 #include "cmd.h"
347 
358 int mlx5_cmd_dump_fill_mkey(struct mlx5_core_dev *dev, u32 *mkey)
369 {
37
-	u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {0};
38
-	u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)]   = {0};
10
+	u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {};
11
+	u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)] = {};
3912 	int err;
4013 
4114 	MLX5_SET(query_special_contexts_in, in, opcode,
4215 		 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS);
43
-	err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
16
+	err = mlx5_cmd_exec_inout(dev, query_special_contexts, in, out);
4417 	if (!err)
4518 		*mkey = MLX5_GET(query_special_contexts_out, out,
4619 				 dump_fill_mkey);
....@@ -50,12 +23,12 @@
5023 int mlx5_cmd_null_mkey(struct mlx5_core_dev *dev, u32 *null_mkey)
5124 {
5225 	u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {};
53
-	u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)]   = {};
26
+	u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)] = {};
5427 	int err;
5528 
5629 	MLX5_SET(query_special_contexts_in, in, opcode,
5730 		 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS);
58
-	err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
31
+	err = mlx5_cmd_exec_inout(dev, query_special_contexts, in, out);
5932 	if (!err)
6033 		*null_mkey = MLX5_GET(query_special_contexts_out, out,
6134 				      null_mkey);
....@@ -63,29 +36,21 @@
6336 }
6437 
6538 int mlx5_cmd_query_cong_params(struct mlx5_core_dev *dev, int cong_point,
66
-			       void *out, int out_size)
39
+			       void *out)
6740 {
68
-	u32 in[MLX5_ST_SZ_DW(query_cong_params_in)] = { };
41
+	u32 in[MLX5_ST_SZ_DW(query_cong_params_in)] = {};
6942 
7043 	MLX5_SET(query_cong_params_in, in, opcode,
7144 		 MLX5_CMD_OP_QUERY_CONG_PARAMS);
7245 	MLX5_SET(query_cong_params_in, in, cong_protocol, cong_point);
7346 
74
-	return mlx5_cmd_exec(dev, in, sizeof(in), out, out_size);
47
+	return mlx5_cmd_exec_inout(dev, query_cong_params, in, out);
7548 }
7649 
77
-int mlx5_cmd_modify_cong_params(struct mlx5_core_dev *dev,
78
-				void *in, int in_size)
50
+int mlx5_cmd_alloc_memic(struct mlx5_dm *dm, phys_addr_t *addr,
51
+			 u64 length, u32 alignment)
7952 {
80
-	u32 out[MLX5_ST_SZ_DW(modify_cong_params_out)] = { };
81
-
82
-	return mlx5_cmd_exec(dev, in, in_size, out, sizeof(out));
83
-}
84
-
85
-int mlx5_cmd_alloc_memic(struct mlx5_memic *memic, phys_addr_t *addr,
86
-			  u64 length, u32 alignment)
87
-{
88
-	struct mlx5_core_dev *dev = memic->dev;
53
+	struct mlx5_core_dev *dev = dm->dev;
8954 	u64 num_memic_hw_pages = MLX5_CAP_DEV_MEM(dev, memic_bar_size)
9055 					>> PAGE_SHIFT;
9156 	u64 hw_start_addr = MLX5_CAP64_DEV_MEM(dev, memic_bar_start_addr);
....@@ -115,17 +80,17 @@
11580 		 mlx5_alignment);
11681 
11782 	while (page_idx < num_memic_hw_pages) {
118
-		spin_lock(&memic->memic_lock);
119
-		page_idx = bitmap_find_next_zero_area(memic->memic_alloc_pages,
83
+		spin_lock(&dm->lock);
84
+		page_idx = bitmap_find_next_zero_area(dm->memic_alloc_pages,
12085 						      num_memic_hw_pages,
12186 						      page_idx,
12287 						      num_pages, 0);
12388 
12489 		if (page_idx < num_memic_hw_pages)
125
-			bitmap_set(memic->memic_alloc_pages,
90
+			bitmap_set(dm->memic_alloc_pages,
12691 				   page_idx, num_pages);
12792 
128
-		spin_unlock(&memic->memic_lock);
93
+		spin_unlock(&dm->lock);
12994 
13095 		if (page_idx >= num_memic_hw_pages)
13196 			break;
....@@ -133,12 +98,12 @@
13398 		MLX5_SET64(alloc_memic_in, in, range_start_addr,
13499 			   hw_start_addr + (page_idx * PAGE_SIZE));
135100 
136
-		ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
101
+		ret = mlx5_cmd_exec_inout(dev, alloc_memic, in, out);
137102 		if (ret) {
138
-			spin_lock(&memic->memic_lock);
139
-			bitmap_clear(memic->memic_alloc_pages,
103
+			spin_lock(&dm->lock);
104
+			bitmap_clear(dm->memic_alloc_pages,
140105 				     page_idx, num_pages);
141
-			spin_unlock(&memic->memic_lock);
106
+			spin_unlock(&dm->lock);
142107 
143108 			if (ret == -EAGAIN) {
144109 				page_idx++;
....@@ -148,7 +113,7 @@
148113 			return ret;
149114 		}
150115 
151
-		*addr = pci_resource_start(dev->pdev, 0) +
116
+		*addr = dev->bar_addr +
152117 			MLX5_GET64(alloc_memic_out, out, memic_start_addr);
153118 
154119 		return 0;
....@@ -157,43 +122,188 @@
157122 	return -ENOMEM;
158123 }
159124 
160
-int mlx5_cmd_dealloc_memic(struct mlx5_memic *memic, u64 addr, u64 length)
125
+void mlx5_cmd_dealloc_memic(struct mlx5_dm *dm, phys_addr_t addr, u64 length)
161126 {
162
-	struct mlx5_core_dev *dev = memic->dev;
127
+	struct mlx5_core_dev *dev = dm->dev;
163128 	u64 hw_start_addr = MLX5_CAP64_DEV_MEM(dev, memic_bar_start_addr);
164129 	u32 num_pages = DIV_ROUND_UP(length, PAGE_SIZE);
165
-	u32 out[MLX5_ST_SZ_DW(dealloc_memic_out)] = {0};
166
-	u32 in[MLX5_ST_SZ_DW(dealloc_memic_in)] = {0};
130
+	u32 in[MLX5_ST_SZ_DW(dealloc_memic_in)] = {};
167131 	u64 start_page_idx;
168132 	int err;
169133 
170
-	addr -= pci_resource_start(dev->pdev, 0);
134
+	addr -= dev->bar_addr;
171135 	start_page_idx = (addr - hw_start_addr) >> PAGE_SHIFT;
172136 
173137 	MLX5_SET(dealloc_memic_in, in, opcode, MLX5_CMD_OP_DEALLOC_MEMIC);
174138 	MLX5_SET64(dealloc_memic_in, in, memic_start_addr, addr);
175139 	MLX5_SET(dealloc_memic_in, in, memic_size, length);
176140 
177
-	err =  mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
141
+	err =  mlx5_cmd_exec_in(dev, dealloc_memic, in);
142
+	if (err)
143
+		return;
178144 
179
-	if (!err) {
180
-		spin_lock(&memic->memic_lock);
181
-		bitmap_clear(memic->memic_alloc_pages,
182
-			     start_page_idx, num_pages);
183
-		spin_unlock(&memic->memic_lock);
184
-	}
145
+	spin_lock(&dm->lock);
146
+	bitmap_clear(dm->memic_alloc_pages,
147
+		     start_page_idx, num_pages);
148
+	spin_unlock(&dm->lock);
149
+}
150
+
151
+void mlx5_cmd_destroy_tir(struct mlx5_core_dev *dev, u32 tirn, u16 uid)
152
+{
153
+	u32 in[MLX5_ST_SZ_DW(destroy_tir_in)] = {};
154
+
155
+	MLX5_SET(destroy_tir_in, in, opcode, MLX5_CMD_OP_DESTROY_TIR);
156
+	MLX5_SET(destroy_tir_in, in, tirn, tirn);
157
+	MLX5_SET(destroy_tir_in, in, uid, uid);
158
+	mlx5_cmd_exec_in(dev, destroy_tir, in);
159
+}
160
+
161
+void mlx5_cmd_destroy_tis(struct mlx5_core_dev *dev, u32 tisn, u16 uid)
162
+{
163
+	u32 in[MLX5_ST_SZ_DW(destroy_tis_in)] = {};
164
+
165
+	MLX5_SET(destroy_tis_in, in, opcode, MLX5_CMD_OP_DESTROY_TIS);
166
+	MLX5_SET(destroy_tis_in, in, tisn, tisn);
167
+	MLX5_SET(destroy_tis_in, in, uid, uid);
168
+	mlx5_cmd_exec_in(dev, destroy_tis, in);
169
+}
170
+
171
+int mlx5_cmd_destroy_rqt(struct mlx5_core_dev *dev, u32 rqtn, u16 uid)
172
+{
173
+	u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {};
174
+
175
+	MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
176
+	MLX5_SET(destroy_rqt_in, in, rqtn, rqtn);
177
+	MLX5_SET(destroy_rqt_in, in, uid, uid);
178
+	return mlx5_cmd_exec_in(dev, destroy_rqt, in);
179
+}
180
+
181
+int mlx5_cmd_alloc_transport_domain(struct mlx5_core_dev *dev, u32 *tdn,
182
+				    u16 uid)
183
+{
184
+	u32 in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {};
185
+	u32 out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {};
186
+	int err;
187
+
188
+	MLX5_SET(alloc_transport_domain_in, in, opcode,
189
+		 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
190
+	MLX5_SET(alloc_transport_domain_in, in, uid, uid);
191
+
192
+	err = mlx5_cmd_exec_inout(dev, alloc_transport_domain, in, out);
193
+	if (!err)
194
+		*tdn = MLX5_GET(alloc_transport_domain_out, out,
195
+				transport_domain);
185196 
186197 	return err;
187198 }
188199 
189
-int mlx5_cmd_query_ext_ppcnt_counters(struct mlx5_core_dev *dev, void *out)
200
+void mlx5_cmd_dealloc_transport_domain(struct mlx5_core_dev *dev, u32 tdn,
201
+				       u16 uid)
190202 {
191
-	u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
192
-	int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
203
+	u32 in[MLX5_ST_SZ_DW(dealloc_transport_domain_in)] = {};
193204 
194
-	MLX5_SET(ppcnt_reg, in, local_port, 1);
205
+	MLX5_SET(dealloc_transport_domain_in, in, opcode,
206
+		 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN);
207
+	MLX5_SET(dealloc_transport_domain_in, in, uid, uid);
208
+	MLX5_SET(dealloc_transport_domain_in, in, transport_domain, tdn);
209
+	mlx5_cmd_exec_in(dev, dealloc_transport_domain, in);
210
+}
195211 
196
-	MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
197
-	return  mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PPCNT,
198
-				     0, 0);
212
+int mlx5_cmd_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn, u16 uid)
213
+{
214
+	u32 in[MLX5_ST_SZ_DW(dealloc_pd_in)] = {};
215
+
216
+	MLX5_SET(dealloc_pd_in, in, opcode, MLX5_CMD_OP_DEALLOC_PD);
217
+	MLX5_SET(dealloc_pd_in, in, pd, pdn);
218
+	MLX5_SET(dealloc_pd_in, in, uid, uid);
219
+	return mlx5_cmd_exec_in(dev, dealloc_pd, in);
220
+}
221
+
222
+int mlx5_cmd_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid,
223
+			u32 qpn, u16 uid)
224
+{
225
+	u32 in[MLX5_ST_SZ_DW(attach_to_mcg_in)] = {};
226
+	void *gid;
227
+
228
+	MLX5_SET(attach_to_mcg_in, in, opcode, MLX5_CMD_OP_ATTACH_TO_MCG);
229
+	MLX5_SET(attach_to_mcg_in, in, qpn, qpn);
230
+	MLX5_SET(attach_to_mcg_in, in, uid, uid);
231
+	gid = MLX5_ADDR_OF(attach_to_mcg_in, in, multicast_gid);
232
+	memcpy(gid, mgid, sizeof(*mgid));
233
+	return mlx5_cmd_exec_in(dev, attach_to_mcg, in);
234
+}
235
+
236
+int mlx5_cmd_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid,
237
+			u32 qpn, u16 uid)
238
+{
239
+	u32 in[MLX5_ST_SZ_DW(detach_from_mcg_in)] = {};
240
+	void *gid;
241
+
242
+	MLX5_SET(detach_from_mcg_in, in, opcode, MLX5_CMD_OP_DETACH_FROM_MCG);
243
+	MLX5_SET(detach_from_mcg_in, in, qpn, qpn);
244
+	MLX5_SET(detach_from_mcg_in, in, uid, uid);
245
+	gid = MLX5_ADDR_OF(detach_from_mcg_in, in, multicast_gid);
246
+	memcpy(gid, mgid, sizeof(*mgid));
247
+	return mlx5_cmd_exec_in(dev, detach_from_mcg, in);
248
+}
249
+
250
+int mlx5_cmd_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn, u16 uid)
251
+{
252
+	u32 out[MLX5_ST_SZ_DW(alloc_xrcd_out)] = {};
253
+	u32 in[MLX5_ST_SZ_DW(alloc_xrcd_in)] = {};
254
+	int err;
255
+
256
+	MLX5_SET(alloc_xrcd_in, in, opcode, MLX5_CMD_OP_ALLOC_XRCD);
257
+	MLX5_SET(alloc_xrcd_in, in, uid, uid);
258
+	err = mlx5_cmd_exec_inout(dev, alloc_xrcd, in, out);
259
+	if (!err)
260
+		*xrcdn = MLX5_GET(alloc_xrcd_out, out, xrcd);
261
+	return err;
262
+}
263
+
264
+int mlx5_cmd_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn, u16 uid)
265
+{
266
+	u32 in[MLX5_ST_SZ_DW(dealloc_xrcd_in)] = {};
267
+
268
+	MLX5_SET(dealloc_xrcd_in, in, opcode, MLX5_CMD_OP_DEALLOC_XRCD);
269
+	MLX5_SET(dealloc_xrcd_in, in, xrcd, xrcdn);
270
+	MLX5_SET(dealloc_xrcd_in, in, uid, uid);
271
+	return mlx5_cmd_exec_in(dev, dealloc_xrcd, in);
272
+}
273
+
274
+int mlx5_cmd_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
275
+		     u16 opmod, u8 port)
276
+{
277
+	int outlen = MLX5_ST_SZ_BYTES(mad_ifc_out);
278
+	int inlen = MLX5_ST_SZ_BYTES(mad_ifc_in);
279
+	int err = -ENOMEM;
280
+	void *data;
281
+	void *resp;
282
+	u32 *out;
283
+	u32 *in;
284
+
285
+	in = kzalloc(inlen, GFP_KERNEL);
286
+	out = kzalloc(outlen, GFP_KERNEL);
287
+	if (!in || !out)
288
+		goto out;
289
+
290
+	MLX5_SET(mad_ifc_in, in, opcode, MLX5_CMD_OP_MAD_IFC);
291
+	MLX5_SET(mad_ifc_in, in, op_mod, opmod);
292
+	MLX5_SET(mad_ifc_in, in, port, port);
293
+
294
+	data = MLX5_ADDR_OF(mad_ifc_in, in, mad);
295
+	memcpy(data, inb, MLX5_FLD_SZ_BYTES(mad_ifc_in, mad));
296
+
297
+	err = mlx5_cmd_exec_inout(dev, mad_ifc, in, out);
298
+	if (err)
299
+		goto out;
300
+
301
+	resp = MLX5_ADDR_OF(mad_ifc_out, out, response_mad_packet);
302
+	memcpy(outb, resp,
303
+	       MLX5_FLD_SZ_BYTES(mad_ifc_out, response_mad_packet));
304
+
305
+out:
306
+	kfree(out);
307
+	kfree(in);
308
+	return err;
199309 }