~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,24 +1,16 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
1	2	/*
2	3	* Copyright (C) 2016 Chris Zhong <zyw@rock-chips.com>
3	4	* Copyright (C) 2016 ROCKCHIP, Inc.
4		- *
5		- * This program is free software; you can redistribute it and/or modify
6		- * it under the terms of the GNU General Public License as published by
7		- * the Free Software Foundation; either version 2 of the License.
8		- *
9		- * This program is distributed in the hope that it will be useful,
10		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12		- * GNU General Public License for more details.
13	5	*/
14	6
15	7	#ifndef _CDN_DP_CORE_H
16	8	#define _CDN_DP_CORE_H
17	9
18		-#include <drm/drmP.h>
19		-#include <drm/drm_crtc_helper.h>
20	10	#include <drm/drm_dp_helper.h>
21	11	#include <drm/drm_panel.h>
	12	+#include <drm/drm_probe_helper.h>
	13	+
22	14	#include "rockchip_drm_drv.h"
23	15
24	16	#define MAX_PHY 2
..	..	@@ -61,8 +53,6 @@
61	53
62	54	struct cdn_dp_port {
63	55	struct cdn_dp_device *dp;
64		- struct notifier_block event_nb;
65		- struct extcon_dev *extcon;
66	56	struct phy *phy;
67	57	u8 lanes;
68	58	bool phy_enabled;
..	..	@@ -76,16 +66,16 @@
76	66	struct drm_encoder encoder;
77	67	struct drm_display_mode mode;
78	68	struct platform_device *audio_pdev;
79		- struct work_struct event_work;
	69	+ struct delayed_work event_work;
80	70	struct edid *edid;
81	71	struct drm_dp_aux aux;
	72	+ struct rockchip_drm_sub_dev sub_dev;
82	73
83	74	struct mutex lock;
84	75	bool connected;
85	76	bool active;
86	77	bool suspended;
87	78	bool use_fw_training;
88		- u8 id;
89	79
90	80	const struct firmware fw; / cdn dp firmware */
91	81	unsigned int fw_version; /* cdn fw version */
..	..	@@ -103,9 +93,10 @@
103	93	struct reset_control *core_rst;
104	94	struct audio_info audio_info;
105	95	struct video_info video_info;
106		- struct drm_dp_link link;
107	96	struct cdn_dp_port *port[MAX_PHY];
108	97	u8 ports;
	98	+ u8 max_lanes;
	99	+ unsigned int max_rate;
109	100	u8 lanes;
110	101	int active_port;
111	102	u8 train_set[4];